2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/immap_85xx.h>
24 #include <asm/fsl_serdes.h>
26 u32 port_to_devdisr[] = {
27 [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
28 [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
29 [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
30 [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
31 [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
32 [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
33 [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
34 [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
35 [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
36 [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
37 [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
38 [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2,
41 static int is_device_disabled(enum fm_port port)
43 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
44 u32 devdisr2 = in_be32(&gur->devdisr2);
46 return port_to_devdisr[port] & devdisr2;
49 void fman_disable_port(enum fm_port port)
51 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
53 /* don't allow disabling of DTSEC1 as its needed for MDIO */
54 if (port == FM1_DTSEC1)
57 setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
60 phy_interface_t fman_port_enet_if(enum fm_port port)
62 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
63 u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
65 if (is_device_disabled(port))
66 return PHY_INTERFACE_MODE_NONE;
68 if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
69 return PHY_INTERFACE_MODE_XGMII;
71 if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2)))
72 return PHY_INTERFACE_MODE_XGMII;
74 /* handle RGMII first */
75 if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
76 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII))
77 return PHY_INTERFACE_MODE_RGMII;
79 if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
80 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII))
81 return PHY_INTERFACE_MODE_MII;
83 if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
84 FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII))
85 return PHY_INTERFACE_MODE_RGMII;
87 if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
88 FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII))
89 return PHY_INTERFACE_MODE_MII;
97 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
98 return PHY_INTERFACE_MODE_SGMII;
105 if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
106 return PHY_INTERFACE_MODE_SGMII;
109 return PHY_INTERFACE_MODE_NONE;
112 return PHY_INTERFACE_MODE_NONE;