1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright 2014 Freescale Semiconductor, Inc.
4 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
10 #include <asm/immap_85xx.h>
11 #include <asm/fsl_serdes.h>
13 u32 port_to_devdisr[] = {
14 [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
15 [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
16 [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
17 [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
18 [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, /* MAC1 */
21 static int is_device_disabled(enum fm_port port)
23 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
24 u32 devdisr2 = in_be32(&gur->devdisr2);
26 return port_to_devdisr[port] & devdisr2;
29 void fman_disable_port(enum fm_port port)
31 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
33 setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
36 phy_interface_t fman_port_enet_if(enum fm_port port)
38 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
39 u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
41 if (is_device_disabled(port))
42 return PHY_INTERFACE_MODE_NONE;
44 if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1)))
45 return PHY_INTERFACE_MODE_XGMII;
47 if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
48 FSL_CORENET_RCWSR13_EC2_RGMII) &&
49 (!is_serdes_configured(QSGMII_FM1_A)))
50 return PHY_INTERFACE_MODE_RGMII;
52 if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
53 FSL_CORENET_RCWSR13_EC1_RGMII) &&
54 (!is_serdes_configured(QSGMII_FM1_A)))
55 return PHY_INTERFACE_MODE_RGMII;
62 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
63 return PHY_INTERFACE_MODE_SGMII;
64 else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1
66 return PHY_INTERFACE_MODE_SGMII_2500;
78 /* check lane A on SerDes1 */
79 if (is_serdes_configured(QSGMII_FM1_A))
80 return PHY_INTERFACE_MODE_QSGMII;
86 return PHY_INTERFACE_MODE_NONE;