2 * Copyright (C) 2014 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
10 DECLARE_GLOBAL_DATA_PTR;
11 static int mc_boot_status;
14 * Copying MC firmware or DPL image to DDR
16 static int mc_copy_image(const char *title,
17 u64 image_addr, u32 image_size, u64 mc_ram_addr)
19 debug("%s copied to address %p\n", title, (void *)mc_ram_addr);
20 memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
25 * MC firmware FIT image parser checks if the image is in FIT
26 * format, verifies integrity of the image and calculates
27 * raw image address and size values.
28 * Returns 0 if success and 1 if any of the above mentioned
32 int parse_mc_firmware_fit_image(const void **raw_image_addr,
33 size_t *raw_image_size)
40 const char *uname = "firmware";
42 /* Check if the image is in NOR flash*/
43 #ifdef CONFIG_SYS_LS_MC_FW_IN_NOR
44 fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR;
46 #error "No CONFIG_SYS_LS_MC_FW_IN_xxx defined"
49 /* Check if Image is in FIT format */
50 format = genimg_get_format(fit_hdr);
52 if (format != IMAGE_FORMAT_FIT) {
53 debug("Not a FIT image\n");
57 if (!fit_check_format(fit_hdr)) {
58 debug("Bad FIT image format\n");
62 node_offset = fit_image_get_node(fit_hdr, uname);
64 if (node_offset < 0) {
65 debug("Can not find %s subimage\n", uname);
69 /* Verify MC firmware image */
70 if (!(fit_image_verify(fit_hdr, node_offset))) {
71 debug("Bad MC firmware hash");
75 /* Get address and size of raw image */
76 fit_image_get_data(fit_hdr, node_offset, &data, &size);
78 *raw_image_addr = data;
79 *raw_image_size = size;
84 int mc_init(bd_t *bis)
88 struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
92 u32 mc_fw_boot_status;
95 const void *raw_image_addr;
96 size_t raw_image_size = 0;
98 BUILD_BUG_ON(CONFIG_SYS_LS_MC_FW_LENGTH % 4 != 0);
101 * The MC private DRAM block was already carved at the end of DRAM
102 * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
104 if (gd->bd->bi_dram[1].start) {
106 gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
109 gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
113 * Management Complex cores should be held at reset out of POR.
114 * U-boot should be the first software to touch MC. To be safe,
115 * we reset all cores again by setting GCR1 to 0. It doesn't do
116 * anything if they are held at reset. After we setup the firmware
117 * we kick off MC by deasserting the reset bit for core 0, and
118 * deasserting the reset bits for Command Portal Managers.
119 * The stop bits are not touched here. They are used to stop the
120 * cores when they are active. Setting stop bits doesn't stop the
121 * cores from fetching instructions when they are released from
124 out_le32(&mc_ccsr_regs->reg_gcr1, 0);
127 error = parse_mc_firmware_fit_image(&raw_image_addr, &raw_image_size);
131 * Load the MC FW at the beginning of the MC private DRAM block:
140 * Calculate offset in the MC private DRAM block at which the MC DPL
141 * blob is to be placed:
143 #ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
145 (CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
146 CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
148 mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
150 mc_dpl_offset = mc_get_dram_block_size() -
151 roundup(CONFIG_SYS_LS_MC_DPL_LENGTH, 4096);
153 if ((mc_dpl_offset & 0x3) != 0 || mc_dpl_offset > 0xffffffff) {
154 printf("%s: Invalid MC DPL offset: %llu\n",
155 __func__, mc_dpl_offset);
161 /* Check if DPL image is in NOR flash */
162 #ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR
163 fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR;
165 #error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined"
168 dpl_size = fdt_totalsize(fdt_hdr);
171 * Load the MC DPL blob at the far end of the MC private DRAM block:
177 mc_ram_addr + mc_dpl_offset);
179 debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
182 * Tell MC where the MC Firmware image was loaded in DDR:
184 out_le32(&mc_ccsr_regs->reg_mcfbalr, (u32)mc_ram_addr);
185 out_le32(&mc_ccsr_regs->reg_mcfbahr, (u32)((u64)mc_ram_addr >> 32));
186 out_le32(&mc_ccsr_regs->reg_mcfapr, MCFAPR_BYPASS_ICID_MASK);
189 * Tell MC where the DPL blob was loaded in DDR, by indicating
190 * its offset relative to the beginning of the DDR block
191 * allocated to the MC firmware. The MC firmware is responsible
192 * for checking that there is no overlap between the DPL blob
193 * and the runtime heap and stack of the MC firmware itself.
195 * NOTE: bits [31:2] of this offset need to be stored in bits [29:0] of
196 * the GSR MC CCSR register. So, this offset is assumed to be 4-byte
198 * Care must be taken not to write 1s into bits 31 and 30 of the GSR in
199 * this case as the SoC COP or PIC will be signaled.
201 out_le32(&mc_ccsr_regs->reg_gsr, (u32)(mc_dpl_offset >> 2));
204 * Deassert reset and release MC core 0 to run
206 out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST);
208 debug("Polling mc_ccsr_regs->reg_gsr ...\n");
211 reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr);
212 mc_fw_boot_status = (reg_gsr & GSR_FS_MASK);
213 if (mc_fw_boot_status & 0x1)
216 udelay(1000); /* throttle polling */
222 printf("%s: timeout booting management complex firmware\n",
225 /* TODO: Get an error status from an MC CCSR register */
230 printf("Management complex booted (boot status: %#x)\n",
233 if (mc_fw_boot_status != 0x1) {
235 * TODO: Identify critical errors from the GSR register's FS
236 * field and for those errors, set error to -ENODEV or other
237 * appropriate errno, so that the status property is set to
238 * failure in the fsl,dprc device tree node.
244 mc_boot_status = -error;
251 int get_mc_boot_status(void)
253 return mc_boot_status;
257 * Return the actual size of the MC private DRAM block.
259 * NOTE: For now this function always returns the minimum required size,
260 * However, in the future, the actual size may be obtained from an environment
263 unsigned long mc_get_dram_block_size(void)
265 return CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;