2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
4 * SPDX-License-Identifier: GPL-2.0+
6 * Rockchip GMAC ethernet IP driver for U-Boot
15 #include <asm/arch/periph.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/grf_rk3288.h>
19 #include <asm/arch/grf_rk3399.h>
20 #include <dm/pinctrl.h>
21 #include <dt-bindings/clock/rk3288-cru.h>
22 #include "designware.h"
24 DECLARE_GLOBAL_DATA_PTR;
27 * Platform data for the gmac
29 * dw_eth_pdata: Required platform data for designware driver (must be first)
31 struct gmac_rockchip_platdata {
32 struct dw_eth_pdata dw_eth_pdata;
38 int (*fix_mac_speed)(struct dw_eth_dev *priv);
39 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
43 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
45 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
46 const void *blob = gd->fdt_blob;
47 int node = dev_of_offset(dev);
49 /* Check the new naming-style first... */
50 pdata->tx_delay = fdtdec_get_int(blob, node, "tx_delay", -ENOENT);
51 pdata->rx_delay = fdtdec_get_int(blob, node, "rx_delay", -ENOENT);
53 /* ... and fall back to the old naming style or default, if necessary */
54 if (pdata->tx_delay == -ENOENT)
55 pdata->tx_delay = fdtdec_get_int(blob, node, "tx-delay", 0x30);
56 if (pdata->rx_delay == -ENOENT)
57 pdata->rx_delay = fdtdec_get_int(blob, node, "rx-delay", 0x10);
59 return designware_eth_ofdata_to_platdata(dev);
62 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
64 struct rk3288_grf *grf;
67 switch (priv->phydev->speed) {
69 clk = RK3288_GMAC_CLK_SEL_2_5M;
72 clk = RK3288_GMAC_CLK_SEL_25M;
75 clk = RK3288_GMAC_CLK_SEL_125M;
78 debug("Unknown phy speed: %d\n", priv->phydev->speed);
82 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
83 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
88 static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
90 struct rk3399_grf_regs *grf;
93 switch (priv->phydev->speed) {
95 clk = RK3399_GMAC_CLK_SEL_2_5M;
98 clk = RK3399_GMAC_CLK_SEL_25M;
101 clk = RK3399_GMAC_CLK_SEL_125M;
104 debug("Unknown phy speed: %d\n", priv->phydev->speed);
108 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
109 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);
114 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
116 struct rk3288_grf *grf;
118 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
119 rk_clrsetreg(&grf->soc_con1,
120 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,
121 RK3288_GMAC_PHY_INTF_SEL_RGMII);
123 rk_clrsetreg(&grf->soc_con3,
124 RK3288_RXCLK_DLY_ENA_GMAC_MASK |
125 RK3288_TXCLK_DLY_ENA_GMAC_MASK |
126 RK3288_CLK_RX_DL_CFG_GMAC_MASK |
127 RK3288_CLK_TX_DL_CFG_GMAC_MASK,
128 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE |
129 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE |
130 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
131 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
134 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
136 struct rk3399_grf_regs *grf;
138 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
140 rk_clrsetreg(&grf->soc_con5,
141 RK3399_GMAC_PHY_INTF_SEL_MASK,
142 RK3399_GMAC_PHY_INTF_SEL_RGMII);
144 rk_clrsetreg(&grf->soc_con6,
145 RK3399_RXCLK_DLY_ENA_GMAC_MASK |
146 RK3399_TXCLK_DLY_ENA_GMAC_MASK |
147 RK3399_CLK_RX_DL_CFG_GMAC_MASK |
148 RK3399_CLK_TX_DL_CFG_GMAC_MASK,
149 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE |
150 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE |
151 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
152 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
155 static int gmac_rockchip_probe(struct udevice *dev)
157 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
158 struct rk_gmac_ops *ops =
159 (struct rk_gmac_ops *)dev_get_driver_data(dev);
163 ret = clk_get_by_index(dev, 0, &clk);
167 /* Since mac_clk is fed by an external clock we can use 0 here */
168 ret = clk_set_rate(&clk, 0);
172 /* Set to RGMII mode */
173 ops->set_to_rgmii(pdata);
175 return designware_eth_probe(dev);
178 static int gmac_rockchip_eth_start(struct udevice *dev)
180 struct eth_pdata *pdata = dev_get_platdata(dev);
181 struct dw_eth_dev *priv = dev_get_priv(dev);
182 struct rk_gmac_ops *ops =
183 (struct rk_gmac_ops *)dev_get_driver_data(dev);
186 ret = designware_eth_init(priv, pdata->enetaddr);
189 ret = ops->fix_mac_speed(priv);
192 ret = designware_eth_enable(priv);
199 const struct eth_ops gmac_rockchip_eth_ops = {
200 .start = gmac_rockchip_eth_start,
201 .send = designware_eth_send,
202 .recv = designware_eth_recv,
203 .free_pkt = designware_eth_free_pkt,
204 .stop = designware_eth_stop,
205 .write_hwaddr = designware_eth_write_hwaddr,
208 const struct rk_gmac_ops rk3288_gmac_ops = {
209 .fix_mac_speed = rk3288_gmac_fix_mac_speed,
210 .set_to_rgmii = rk3288_gmac_set_to_rgmii,
213 const struct rk_gmac_ops rk3399_gmac_ops = {
214 .fix_mac_speed = rk3399_gmac_fix_mac_speed,
215 .set_to_rgmii = rk3399_gmac_set_to_rgmii,
218 static const struct udevice_id rockchip_gmac_ids[] = {
219 { .compatible = "rockchip,rk3288-gmac",
220 .data = (ulong)&rk3288_gmac_ops },
221 { .compatible = "rockchip,rk3399-gmac",
222 .data = (ulong)&rk3399_gmac_ops },
226 U_BOOT_DRIVER(eth_gmac_rockchip) = {
227 .name = "gmac_rockchip",
229 .of_match = rockchip_gmac_ids,
230 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata,
231 .probe = gmac_rockchip_probe,
232 .ops = &gmac_rockchip_eth_ops,
233 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
234 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata),
235 .flags = DM_FLAG_ALLOC_PRIV_DMA,