git.sur5r.net Git - u-boot/blob - drivers/net/gmac_rockchip.c

   1 /*
   2  * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  * Rockchip GMAC ethernet IP driver for U-Boot
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <clk.h>
  12 #include <phy.h>
  13 #include <syscon.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/periph.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/hardware.h>
  18 #include <asm/arch/grf_rk3288.h>
  19 #include <asm/arch/grf_rk3328.h>
  20 #include <asm/arch/grf_rk3368.h>
  21 #include <asm/arch/grf_rk3399.h>
  22 #include <asm/arch/grf_rv1108.h>
  23 #include <dm/pinctrl.h>
  24 #include <dt-bindings/clock/rk3288-cru.h>
  25 #include "designware.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 /*
  30  * Platform data for the gmac
  31  *
  32  * dw_eth_pdata: Required platform data for designware driver (must be first)
  33  */
  34 struct gmac_rockchip_platdata {
  35         struct dw_eth_pdata dw_eth_pdata;
  36         bool clock_input;
  37         int tx_delay;
  38         int rx_delay;
  39 };
  40
  41 struct rk_gmac_ops {
  42         int (*fix_mac_speed)(struct dw_eth_dev *priv);
  43         void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
  44         void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
  45 };
  46
  47
  48 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
  49 {
  50         struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
  51         const char *string;
  52
  53         string = dev_read_string(dev, "clock_in_out");
  54         if (!strcmp(string, "input"))
  55                 pdata->clock_input = true;
  56         else
  57                 pdata->clock_input = false;
  58
  59         /* Check the new naming-style first... */
  60         pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
  61         pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
  62
  63         /* ... and fall back to the old naming style or default, if necessary */
  64         if (pdata->tx_delay == -ENOENT)
  65                 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30);
  66         if (pdata->rx_delay == -ENOENT)
  67                 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
  68
  69         return designware_eth_ofdata_to_platdata(dev);
  70 }
  71
  72 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  73 {
  74         struct rk3288_grf *grf;
  75         int clk;
  76
  77         switch (priv->phydev->speed) {
  78         case 10:
  79                 clk = RK3288_GMAC_CLK_SEL_2_5M;
  80                 break;
  81         case 100:
  82                 clk = RK3288_GMAC_CLK_SEL_25M;
  83                 break;
  84         case 1000:
  85                 clk = RK3288_GMAC_CLK_SEL_125M;
  86                 break;
  87         default:
  88                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
  89                 return -EINVAL;
  90         }
  91
  92         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  93         rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
  94
  95         return 0;
  96 }
  97
  98 static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  99 {
 100         struct rk3328_grf_regs *grf;
 101         int clk;
 102         enum {
 103                 RK3328_GMAC_CLK_SEL_SHIFT = 11,
 104                 RK3328_GMAC_CLK_SEL_MASK  = GENMASK(12, 11),
 105                 RK3328_GMAC_CLK_SEL_125M  = 0 << 11,
 106                 RK3328_GMAC_CLK_SEL_25M   = 3 << 11,
 107                 RK3328_GMAC_CLK_SEL_2_5M  = 2 << 11,
 108         };
 109
 110         switch (priv->phydev->speed) {
 111         case 10:
 112                 clk = RK3328_GMAC_CLK_SEL_2_5M;
 113                 break;
 114         case 100:
 115                 clk = RK3328_GMAC_CLK_SEL_25M;
 116                 break;
 117         case 1000:
 118                 clk = RK3328_GMAC_CLK_SEL_125M;
 119                 break;
 120         default:
 121                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 122                 return -EINVAL;
 123         }
 124
 125         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 126         rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
 127
 128         return 0;
 129 }
 130
 131 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 132 {
 133         struct rk3368_grf *grf;
 134         int clk;
 135         enum {
 136                 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
 137                 RK3368_GMAC_CLK_SEL_25M = 3 << 4,
 138                 RK3368_GMAC_CLK_SEL_125M = 0 << 4,
 139                 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
 140         };
 141
 142         switch (priv->phydev->speed) {
 143         case 10:
 144                 clk = RK3368_GMAC_CLK_SEL_2_5M;
 145                 break;
 146         case 100:
 147                 clk = RK3368_GMAC_CLK_SEL_25M;
 148                 break;
 149         case 1000:
 150                 clk = RK3368_GMAC_CLK_SEL_125M;
 151                 break;
 152         default:
 153                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 154                 return -EINVAL;
 155         }
 156
 157         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 158         rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
 159
 160         return 0;
 161 }
 162
 163 static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 164 {
 165         struct rk3399_grf_regs *grf;
 166         int clk;
 167
 168         switch (priv->phydev->speed) {
 169         case 10:
 170                 clk = RK3399_GMAC_CLK_SEL_2_5M;
 171                 break;
 172         case 100:
 173                 clk = RK3399_GMAC_CLK_SEL_25M;
 174                 break;
 175         case 1000:
 176                 clk = RK3399_GMAC_CLK_SEL_125M;
 177                 break;
 178         default:
 179                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 180                 return -EINVAL;
 181         }
 182
 183         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 184         rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);
 185
 186         return 0;
 187 }
 188
 189 static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
 190 {
 191         struct rv1108_grf *grf;
 192         int clk, speed;
 193         enum {
 194                 RV1108_GMAC_SPEED_MASK          = BIT(2),
 195                 RV1108_GMAC_SPEED_10M           = 0 << 2,
 196                 RV1108_GMAC_SPEED_100M          = 1 << 2,
 197                 RV1108_GMAC_CLK_SEL_MASK        = BIT(7),
 198                 RV1108_GMAC_CLK_SEL_2_5M        = 0 << 7,
 199                 RV1108_GMAC_CLK_SEL_25M         = 1 << 7,
 200         };
 201
 202         switch (priv->phydev->speed) {
 203         case 10:
 204                 clk = RV1108_GMAC_CLK_SEL_2_5M;
 205                 speed = RV1108_GMAC_SPEED_10M;
 206                 break;
 207         case 100:
 208                 clk = RV1108_GMAC_CLK_SEL_25M;
 209                 speed = RV1108_GMAC_SPEED_100M;
 210                 break;
 211         default:
 212                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 213                 return -EINVAL;
 214         }
 215
 216         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 217         rk_clrsetreg(&grf->gmac_con0,
 218                      RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
 219                      clk | speed);
 220
 221         return 0;
 222 }
 223
 224 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 225 {
 226         struct rk3288_grf *grf;
 227
 228         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 229         rk_clrsetreg(&grf->soc_con1,
 230                      RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,
 231                      RK3288_GMAC_PHY_INTF_SEL_RGMII);
 232
 233         rk_clrsetreg(&grf->soc_con3,
 234                      RK3288_RXCLK_DLY_ENA_GMAC_MASK |
 235                      RK3288_TXCLK_DLY_ENA_GMAC_MASK |
 236                      RK3288_CLK_RX_DL_CFG_GMAC_MASK |
 237                      RK3288_CLK_TX_DL_CFG_GMAC_MASK,
 238                      RK3288_RXCLK_DLY_ENA_GMAC_ENABLE |
 239                      RK3288_TXCLK_DLY_ENA_GMAC_ENABLE |
 240                      pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
 241                      pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
 242 }
 243
 244 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 245 {
 246         struct rk3328_grf_regs *grf;
 247         enum {
 248                 RK3328_RMII_MODE_SHIFT = 9,
 249                 RK3328_RMII_MODE_MASK  = BIT(9),
 250
 251                 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
 252                 RK3328_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
 253                 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
 254
 255                 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
 256                 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
 257                 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
 258
 259                 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
 260                 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
 261                 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
 262         };
 263         enum {
 264                 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
 265                 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
 266
 267                 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
 268                 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
 269         };
 270
 271         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 272         rk_clrsetreg(&grf->mac_con[1],
 273                      RK3328_RMII_MODE_MASK |
 274                      RK3328_GMAC_PHY_INTF_SEL_MASK |
 275                      RK3328_RXCLK_DLY_ENA_GMAC_MASK |
 276                      RK3328_TXCLK_DLY_ENA_GMAC_MASK,
 277                      RK3328_GMAC_PHY_INTF_SEL_RGMII |
 278                      RK3328_RXCLK_DLY_ENA_GMAC_MASK |
 279                      RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
 280
 281         rk_clrsetreg(&grf->mac_con[0],
 282                      RK3328_CLK_RX_DL_CFG_GMAC_MASK |
 283                      RK3328_CLK_TX_DL_CFG_GMAC_MASK,
 284                      pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
 285                      pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
 286 }
 287
 288 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 289 {
 290         struct rk3368_grf *grf;
 291         enum {
 292                 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
 293                 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
 294                 RK3368_RMII_MODE_MASK  = BIT(6),
 295                 RK3368_RMII_MODE       = BIT(6),
 296         };
 297         enum {
 298                 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
 299                 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
 300                 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
 301                 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
 302                 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
 303                 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
 304                 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
 305                 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
 306                 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
 307                 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
 308         };
 309
 310         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 311         rk_clrsetreg(&grf->soc_con15,
 312                      RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
 313                      RK3368_GMAC_PHY_INTF_SEL_RGMII);
 314
 315         rk_clrsetreg(&grf->soc_con16,
 316                      RK3368_RXCLK_DLY_ENA_GMAC_MASK |
 317                      RK3368_TXCLK_DLY_ENA_GMAC_MASK |
 318                      RK3368_CLK_RX_DL_CFG_GMAC_MASK |
 319                      RK3368_CLK_TX_DL_CFG_GMAC_MASK,
 320                      RK3368_RXCLK_DLY_ENA_GMAC_ENABLE |
 321                      RK3368_TXCLK_DLY_ENA_GMAC_ENABLE |
 322                      pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
 323                      pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
 324 }
 325
 326 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 327 {
 328         struct rk3399_grf_regs *grf;
 329
 330         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 331
 332         rk_clrsetreg(&grf->soc_con5,
 333                      RK3399_GMAC_PHY_INTF_SEL_MASK,
 334                      RK3399_GMAC_PHY_INTF_SEL_RGMII);
 335
 336         rk_clrsetreg(&grf->soc_con6,
 337                      RK3399_RXCLK_DLY_ENA_GMAC_MASK |
 338                      RK3399_TXCLK_DLY_ENA_GMAC_MASK |
 339                      RK3399_CLK_RX_DL_CFG_GMAC_MASK |
 340                      RK3399_CLK_TX_DL_CFG_GMAC_MASK,
 341                      RK3399_RXCLK_DLY_ENA_GMAC_ENABLE |
 342                      RK3399_TXCLK_DLY_ENA_GMAC_ENABLE |
 343                      pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
 344                      pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
 345 }
 346
 347 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
 348 {
 349         struct rv1108_grf *grf;
 350
 351         enum {
 352                 RV1108_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
 353                 RV1108_GMAC_PHY_INTF_SEL_RMII  = 4 << 4,
 354         };
 355
 356         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 357         rk_clrsetreg(&grf->gmac_con0,
 358                      RV1108_GMAC_PHY_INTF_SEL_MASK,
 359                      RV1108_GMAC_PHY_INTF_SEL_RMII);
 360 }
 361
 362 static int gmac_rockchip_probe(struct udevice *dev)
 363 {
 364         struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
 365         struct rk_gmac_ops *ops =
 366                 (struct rk_gmac_ops *)dev_get_driver_data(dev);
 367         struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
 368         struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata;
 369         struct clk clk;
 370         ulong rate;
 371         int ret;
 372
 373         ret = clk_get_by_index(dev, 0, &clk);
 374         if (ret)
 375                 return ret;
 376
 377         switch (eth_pdata->phy_interface) {
 378         case PHY_INTERFACE_MODE_RGMII:
 379                 /*
 380                  * If the gmac clock is from internal pll, need to set and
 381                  * check the return value for gmac clock at RGMII mode. If
 382                  * the gmac clock is from external source, the clock rate
 383                  * is not set, because of it is bypassed.
 384                  */
 385                 if (!pdata->clock_input) {
 386                         rate = clk_set_rate(&clk, 125000000);
 387                         if (rate != 125000000)
 388                                 return -EINVAL;
 389                 }
 390
 391                 /* Set to RGMII mode */
 392                 if (ops->set_to_rgmii)
 393                         ops->set_to_rgmii(pdata);
 394                 else
 395                         return -EPERM;
 396
 397                 break;
 398         case PHY_INTERFACE_MODE_RMII:
 399                 /* The commet is the same as RGMII mode */
 400                 if (!pdata->clock_input) {
 401                         rate = clk_set_rate(&clk, 50000000);
 402                         if (rate != 50000000)
 403                                 return -EINVAL;
 404                 }
 405
 406                 /* Set to RMII mode */
 407                 if (ops->set_to_rmii)
 408                         ops->set_to_rmii(pdata);
 409                 else
 410                         return -EPERM;
 411
 412                 break;
 413         default:
 414                 debug("NO interface defined!\n");
 415                 return -ENXIO;
 416         }
 417
 418         return designware_eth_probe(dev);
 419 }
 420
 421 static int gmac_rockchip_eth_start(struct udevice *dev)
 422 {
 423         struct eth_pdata *pdata = dev_get_platdata(dev);
 424         struct dw_eth_dev *priv = dev_get_priv(dev);
 425         struct rk_gmac_ops *ops =
 426                 (struct rk_gmac_ops *)dev_get_driver_data(dev);
 427         int ret;
 428
 429         ret = designware_eth_init(priv, pdata->enetaddr);
 430         if (ret)
 431                 return ret;
 432         ret = ops->fix_mac_speed(priv);
 433         if (ret)
 434                 return ret;
 435         ret = designware_eth_enable(priv);
 436         if (ret)
 437                 return ret;
 438
 439         return 0;
 440 }
 441
 442 const struct eth_ops gmac_rockchip_eth_ops = {
 443         .start                  = gmac_rockchip_eth_start,
 444         .send                   = designware_eth_send,
 445         .recv                   = designware_eth_recv,
 446         .free_pkt               = designware_eth_free_pkt,
 447         .stop                   = designware_eth_stop,
 448         .write_hwaddr           = designware_eth_write_hwaddr,
 449 };
 450
 451 const struct rk_gmac_ops rk3288_gmac_ops = {
 452         .fix_mac_speed = rk3288_gmac_fix_mac_speed,
 453         .set_to_rgmii = rk3288_gmac_set_to_rgmii,
 454 };
 455
 456 const struct rk_gmac_ops rk3328_gmac_ops = {
 457         .fix_mac_speed = rk3328_gmac_fix_mac_speed,
 458         .set_to_rgmii = rk3328_gmac_set_to_rgmii,
 459 };
 460
 461 const struct rk_gmac_ops rk3368_gmac_ops = {
 462         .fix_mac_speed = rk3368_gmac_fix_mac_speed,
 463         .set_to_rgmii = rk3368_gmac_set_to_rgmii,
 464 };
 465
 466 const struct rk_gmac_ops rk3399_gmac_ops = {
 467         .fix_mac_speed = rk3399_gmac_fix_mac_speed,
 468         .set_to_rgmii = rk3399_gmac_set_to_rgmii,
 469 };
 470
 471 const struct rk_gmac_ops rv1108_gmac_ops = {
 472         .fix_mac_speed = rv1108_set_rmii_speed,
 473         .set_to_rmii = rv1108_gmac_set_to_rmii,
 474 };
 475
 476 static const struct udevice_id rockchip_gmac_ids[] = {
 477         { .compatible = "rockchip,rk3288-gmac",
 478           .data = (ulong)&rk3288_gmac_ops },
 479         { .compatible = "rockchip,rk3328-gmac",
 480           .data = (ulong)&rk3328_gmac_ops },
 481         { .compatible = "rockchip,rk3368-gmac",
 482           .data = (ulong)&rk3368_gmac_ops },
 483         { .compatible = "rockchip,rk3399-gmac",
 484           .data = (ulong)&rk3399_gmac_ops },
 485         { .compatible = "rockchip,rv1108-gmac",
 486           .data = (ulong)&rv1108_gmac_ops },
 487         { }
 488 };
 489
 490 U_BOOT_DRIVER(eth_gmac_rockchip) = {
 491         .name   = "gmac_rockchip",
 492         .id     = UCLASS_ETH,
 493         .of_match = rockchip_gmac_ids,
 494         .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata,
 495         .probe  = gmac_rockchip_probe,
 496         .ops    = &gmac_rockchip_eth_ops,
 497         .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
 498         .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata),
 499         .flags = DM_FLAG_ALLOC_PRIV_DMA,
 500 };