2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
4 * SPDX-License-Identifier: GPL-2.0+
6 * Rockchip GMAC ethernet IP driver for U-Boot
15 #include <asm/arch/periph.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/grf_rk322x.h>
19 #include <asm/arch/grf_rk3288.h>
20 #include <asm/arch/grf_rk3328.h>
21 #include <asm/arch/grf_rk3368.h>
22 #include <asm/arch/grf_rk3399.h>
23 #include <asm/arch/grf_rv1108.h>
24 #include <dm/pinctrl.h>
25 #include <dt-bindings/clock/rk3288-cru.h>
26 #include "designware.h"
29 * Platform data for the gmac
31 * dw_eth_pdata: Required platform data for designware driver (must be first)
33 struct gmac_rockchip_platdata {
34 struct dw_eth_pdata dw_eth_pdata;
41 int (*fix_mac_speed)(struct dw_eth_dev *priv);
42 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
43 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
47 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
49 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
52 string = dev_read_string(dev, "clock_in_out");
53 if (!strcmp(string, "input"))
54 pdata->clock_input = true;
56 pdata->clock_input = false;
58 /* Check the new naming-style first... */
59 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
60 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
62 /* ... and fall back to the old naming style or default, if necessary */
63 if (pdata->tx_delay == -ENOENT)
64 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30);
65 if (pdata->rx_delay == -ENOENT)
66 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
68 return designware_eth_ofdata_to_platdata(dev);
71 static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
73 struct rk322x_grf *grf;
76 RK3228_GMAC_CLK_SEL_SHIFT = 8,
77 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8),
78 RK3228_GMAC_CLK_SEL_125M = 0 << 8,
79 RK3228_GMAC_CLK_SEL_25M = 3 << 8,
80 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8,
83 switch (priv->phydev->speed) {
85 clk = RK3228_GMAC_CLK_SEL_2_5M;
88 clk = RK3228_GMAC_CLK_SEL_25M;
91 clk = RK3228_GMAC_CLK_SEL_125M;
94 debug("Unknown phy speed: %d\n", priv->phydev->speed);
98 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
99 rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk);
104 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
106 struct rk3288_grf *grf;
109 switch (priv->phydev->speed) {
111 clk = RK3288_GMAC_CLK_SEL_2_5M;
114 clk = RK3288_GMAC_CLK_SEL_25M;
117 clk = RK3288_GMAC_CLK_SEL_125M;
120 debug("Unknown phy speed: %d\n", priv->phydev->speed);
124 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
125 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
130 static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
132 struct rk3328_grf_regs *grf;
135 RK3328_GMAC_CLK_SEL_SHIFT = 11,
136 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11),
137 RK3328_GMAC_CLK_SEL_125M = 0 << 11,
138 RK3328_GMAC_CLK_SEL_25M = 3 << 11,
139 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11,
142 switch (priv->phydev->speed) {
144 clk = RK3328_GMAC_CLK_SEL_2_5M;
147 clk = RK3328_GMAC_CLK_SEL_25M;
150 clk = RK3328_GMAC_CLK_SEL_125M;
153 debug("Unknown phy speed: %d\n", priv->phydev->speed);
157 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
158 rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
163 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
165 struct rk3368_grf *grf;
168 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
169 RK3368_GMAC_CLK_SEL_25M = 3 << 4,
170 RK3368_GMAC_CLK_SEL_125M = 0 << 4,
171 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
174 switch (priv->phydev->speed) {
176 clk = RK3368_GMAC_CLK_SEL_2_5M;
179 clk = RK3368_GMAC_CLK_SEL_25M;
182 clk = RK3368_GMAC_CLK_SEL_125M;
185 debug("Unknown phy speed: %d\n", priv->phydev->speed);
189 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
190 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
195 static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
197 struct rk3399_grf_regs *grf;
200 switch (priv->phydev->speed) {
202 clk = RK3399_GMAC_CLK_SEL_2_5M;
205 clk = RK3399_GMAC_CLK_SEL_25M;
208 clk = RK3399_GMAC_CLK_SEL_125M;
211 debug("Unknown phy speed: %d\n", priv->phydev->speed);
215 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
216 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);
221 static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
223 struct rv1108_grf *grf;
226 RV1108_GMAC_SPEED_MASK = BIT(2),
227 RV1108_GMAC_SPEED_10M = 0 << 2,
228 RV1108_GMAC_SPEED_100M = 1 << 2,
229 RV1108_GMAC_CLK_SEL_MASK = BIT(7),
230 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7,
231 RV1108_GMAC_CLK_SEL_25M = 1 << 7,
234 switch (priv->phydev->speed) {
236 clk = RV1108_GMAC_CLK_SEL_2_5M;
237 speed = RV1108_GMAC_SPEED_10M;
240 clk = RV1108_GMAC_CLK_SEL_25M;
241 speed = RV1108_GMAC_SPEED_100M;
244 debug("Unknown phy speed: %d\n", priv->phydev->speed);
248 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
249 rk_clrsetreg(&grf->gmac_con0,
250 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
256 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
258 struct rk322x_grf *grf;
260 RK3228_RMII_MODE_SHIFT = 10,
261 RK3228_RMII_MODE_MASK = BIT(10),
263 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
264 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
265 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
267 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
268 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
269 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
271 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
272 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
273 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
276 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
277 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
279 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
280 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
283 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
284 rk_clrsetreg(&grf->mac_con[1],
285 RK3228_RMII_MODE_MASK |
286 RK3228_GMAC_PHY_INTF_SEL_MASK |
287 RK3228_RXCLK_DLY_ENA_GMAC_MASK |
288 RK3228_TXCLK_DLY_ENA_GMAC_MASK,
289 RK3228_GMAC_PHY_INTF_SEL_RGMII |
290 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE |
291 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE);
293 rk_clrsetreg(&grf->mac_con[0],
294 RK3228_CLK_RX_DL_CFG_GMAC_MASK |
295 RK3228_CLK_TX_DL_CFG_GMAC_MASK,
296 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
297 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
300 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
302 struct rk3288_grf *grf;
304 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
305 rk_clrsetreg(&grf->soc_con1,
306 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,
307 RK3288_GMAC_PHY_INTF_SEL_RGMII);
309 rk_clrsetreg(&grf->soc_con3,
310 RK3288_RXCLK_DLY_ENA_GMAC_MASK |
311 RK3288_TXCLK_DLY_ENA_GMAC_MASK |
312 RK3288_CLK_RX_DL_CFG_GMAC_MASK |
313 RK3288_CLK_TX_DL_CFG_GMAC_MASK,
314 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE |
315 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE |
316 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
317 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
320 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
322 struct rk3328_grf_regs *grf;
324 RK3328_RMII_MODE_SHIFT = 9,
325 RK3328_RMII_MODE_MASK = BIT(9),
327 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
328 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
329 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
331 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
332 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
333 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
335 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
336 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
337 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
340 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
341 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
343 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
344 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
347 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
348 rk_clrsetreg(&grf->mac_con[1],
349 RK3328_RMII_MODE_MASK |
350 RK3328_GMAC_PHY_INTF_SEL_MASK |
351 RK3328_RXCLK_DLY_ENA_GMAC_MASK |
352 RK3328_TXCLK_DLY_ENA_GMAC_MASK,
353 RK3328_GMAC_PHY_INTF_SEL_RGMII |
354 RK3328_RXCLK_DLY_ENA_GMAC_MASK |
355 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
357 rk_clrsetreg(&grf->mac_con[0],
358 RK3328_CLK_RX_DL_CFG_GMAC_MASK |
359 RK3328_CLK_TX_DL_CFG_GMAC_MASK,
360 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
361 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
364 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
366 struct rk3368_grf *grf;
368 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
369 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
370 RK3368_RMII_MODE_MASK = BIT(6),
371 RK3368_RMII_MODE = BIT(6),
374 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
375 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
376 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
377 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
378 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
379 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
380 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
381 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
382 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
383 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
386 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
387 rk_clrsetreg(&grf->soc_con15,
388 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
389 RK3368_GMAC_PHY_INTF_SEL_RGMII);
391 rk_clrsetreg(&grf->soc_con16,
392 RK3368_RXCLK_DLY_ENA_GMAC_MASK |
393 RK3368_TXCLK_DLY_ENA_GMAC_MASK |
394 RK3368_CLK_RX_DL_CFG_GMAC_MASK |
395 RK3368_CLK_TX_DL_CFG_GMAC_MASK,
396 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE |
397 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE |
398 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
399 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
402 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
404 struct rk3399_grf_regs *grf;
406 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
408 rk_clrsetreg(&grf->soc_con5,
409 RK3399_GMAC_PHY_INTF_SEL_MASK,
410 RK3399_GMAC_PHY_INTF_SEL_RGMII);
412 rk_clrsetreg(&grf->soc_con6,
413 RK3399_RXCLK_DLY_ENA_GMAC_MASK |
414 RK3399_TXCLK_DLY_ENA_GMAC_MASK |
415 RK3399_CLK_RX_DL_CFG_GMAC_MASK |
416 RK3399_CLK_TX_DL_CFG_GMAC_MASK,
417 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE |
418 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE |
419 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
420 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
423 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
425 struct rv1108_grf *grf;
428 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
429 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4,
432 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
433 rk_clrsetreg(&grf->gmac_con0,
434 RV1108_GMAC_PHY_INTF_SEL_MASK,
435 RV1108_GMAC_PHY_INTF_SEL_RMII);
438 static int gmac_rockchip_probe(struct udevice *dev)
440 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
441 struct rk_gmac_ops *ops =
442 (struct rk_gmac_ops *)dev_get_driver_data(dev);
443 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
444 struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata;
449 ret = clk_get_by_index(dev, 0, &clk);
453 switch (eth_pdata->phy_interface) {
454 case PHY_INTERFACE_MODE_RGMII:
456 * If the gmac clock is from internal pll, need to set and
457 * check the return value for gmac clock at RGMII mode. If
458 * the gmac clock is from external source, the clock rate
459 * is not set, because of it is bypassed.
461 if (!pdata->clock_input) {
462 rate = clk_set_rate(&clk, 125000000);
463 if (rate != 125000000)
467 /* Set to RGMII mode */
468 if (ops->set_to_rgmii)
469 ops->set_to_rgmii(pdata);
474 case PHY_INTERFACE_MODE_RMII:
475 /* The commet is the same as RGMII mode */
476 if (!pdata->clock_input) {
477 rate = clk_set_rate(&clk, 50000000);
478 if (rate != 50000000)
482 /* Set to RMII mode */
483 if (ops->set_to_rmii)
484 ops->set_to_rmii(pdata);
490 debug("NO interface defined!\n");
494 return designware_eth_probe(dev);
497 static int gmac_rockchip_eth_start(struct udevice *dev)
499 struct eth_pdata *pdata = dev_get_platdata(dev);
500 struct dw_eth_dev *priv = dev_get_priv(dev);
501 struct rk_gmac_ops *ops =
502 (struct rk_gmac_ops *)dev_get_driver_data(dev);
505 ret = designware_eth_init(priv, pdata->enetaddr);
508 ret = ops->fix_mac_speed(priv);
511 ret = designware_eth_enable(priv);
518 const struct eth_ops gmac_rockchip_eth_ops = {
519 .start = gmac_rockchip_eth_start,
520 .send = designware_eth_send,
521 .recv = designware_eth_recv,
522 .free_pkt = designware_eth_free_pkt,
523 .stop = designware_eth_stop,
524 .write_hwaddr = designware_eth_write_hwaddr,
527 const struct rk_gmac_ops rk3228_gmac_ops = {
528 .fix_mac_speed = rk3228_gmac_fix_mac_speed,
529 .set_to_rgmii = rk3228_gmac_set_to_rgmii,
532 const struct rk_gmac_ops rk3288_gmac_ops = {
533 .fix_mac_speed = rk3288_gmac_fix_mac_speed,
534 .set_to_rgmii = rk3288_gmac_set_to_rgmii,
537 const struct rk_gmac_ops rk3328_gmac_ops = {
538 .fix_mac_speed = rk3328_gmac_fix_mac_speed,
539 .set_to_rgmii = rk3328_gmac_set_to_rgmii,
542 const struct rk_gmac_ops rk3368_gmac_ops = {
543 .fix_mac_speed = rk3368_gmac_fix_mac_speed,
544 .set_to_rgmii = rk3368_gmac_set_to_rgmii,
547 const struct rk_gmac_ops rk3399_gmac_ops = {
548 .fix_mac_speed = rk3399_gmac_fix_mac_speed,
549 .set_to_rgmii = rk3399_gmac_set_to_rgmii,
552 const struct rk_gmac_ops rv1108_gmac_ops = {
553 .fix_mac_speed = rv1108_set_rmii_speed,
554 .set_to_rmii = rv1108_gmac_set_to_rmii,
557 static const struct udevice_id rockchip_gmac_ids[] = {
558 { .compatible = "rockchip,rk3228-gmac",
559 .data = (ulong)&rk3228_gmac_ops },
560 { .compatible = "rockchip,rk3288-gmac",
561 .data = (ulong)&rk3288_gmac_ops },
562 { .compatible = "rockchip,rk3328-gmac",
563 .data = (ulong)&rk3328_gmac_ops },
564 { .compatible = "rockchip,rk3368-gmac",
565 .data = (ulong)&rk3368_gmac_ops },
566 { .compatible = "rockchip,rk3399-gmac",
567 .data = (ulong)&rk3399_gmac_ops },
568 { .compatible = "rockchip,rv1108-gmac",
569 .data = (ulong)&rv1108_gmac_ops },
573 U_BOOT_DRIVER(eth_gmac_rockchip) = {
574 .name = "gmac_rockchip",
576 .of_match = rockchip_gmac_ids,
577 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata,
578 .probe = gmac_rockchip_probe,
579 .ops = &gmac_rockchip_eth_ops,
580 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
581 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata),
582 .flags = DM_FLAG_ALLOC_PRIV_DMA,