1 /* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver
3 * Driver use polling mode (no Interrupt)
6 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
8 * SPDX-License-Identifier: GPL-2.0+
19 #include <asm/processor.h>
25 /* Default to 3s timeout on autonegotiation */
26 #ifndef GRETH_PHY_TIMEOUT_MS
27 #define GRETH_PHY_TIMEOUT_MS 3000
30 /* Default to PHY adrress 0 not not specified */
31 #ifdef CONFIG_SYS_GRLIB_GRETH_PHYADDR
32 #define GRETH_PHY_ADR_DEFAULT CONFIG_SYS_GRLIB_GRETH_PHYADDR
34 #define GRETH_PHY_ADR_DEFAULT 0
37 /* ByPass Cache when reading regs */
38 #define GRETH_REGLOAD(addr) SPARC_NOCACHE_READ(addr)
39 /* Write-through cache ==> no bypassing needed on writes */
40 #define GRETH_REGSAVE(addr,data) (*(volatile unsigned int *)(addr) = (data))
41 #define GRETH_REGORIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)|data)
42 #define GRETH_REGANDIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)&data)
44 #define GRETH_RXBD_CNT 4
45 #define GRETH_TXBD_CNT 1
47 #define GRETH_RXBUF_SIZE 1540
48 #define GRETH_BUF_ALIGN 4
49 #define GRETH_RXBUF_EFF_SIZE \
50 ( (GRETH_RXBUF_SIZE&~(GRETH_BUF_ALIGN-1))+GRETH_BUF_ALIGN )
55 struct eth_device *dev;
58 unsigned char phyaddr;
61 /* Current operating Mode */
63 int fd; /* Full Duplex */
64 int sp; /* 10/100Mbps speed (1=100,0=10) */
65 int auto_neg; /* Auto negotiate done */
67 unsigned char hwaddr[6]; /* MAC Address */
70 greth_bd *rxbd_base, *rxbd_max;
71 greth_bd *txbd_base, *txbd_max;
75 /* rx buffers in rx descriptors */
76 void *rxbuf_base; /* (GRETH_RXBUF_SIZE+ALIGNBYTES) * GRETH_RXBD_CNT */
78 /* unused for gbit_mac, temp buffer for sending packets with unligned
80 * Pointer to packet allocated with malloc.
86 unsigned int rx_packets,
87 rx_crc_errors, rx_frame_errors, rx_length_errors, rx_errors;
90 unsigned int tx_packets,
92 tx_underrun_errors, tx_limit_errors, tx_errors;
96 /* Read MII register 'addr' from core 'regs' */
97 static int read_mii(int phyaddr, int regaddr, volatile greth_regs * regs)
99 while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
102 GRETH_REGSAVE(®s->mdio, ((phyaddr & 0x1F) << 11) | ((regaddr & 0x1F) << 6) | 2);
104 while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
107 if (!(GRETH_REGLOAD(®s->mdio) & GRETH_MII_NVALID)) {
108 return (GRETH_REGLOAD(®s->mdio) >> 16) & 0xFFFF;
114 static void write_mii(int phyaddr, int regaddr, int data, volatile greth_regs * regs)
116 while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
119 GRETH_REGSAVE(®s->mdio,
120 ((data & 0xFFFF) << 16) | ((phyaddr & 0x1F) << 11) |
121 ((regaddr & 0x1F) << 6) | 1);
123 while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
128 /* init/start hardware and allocate descriptor buffers for rx side
131 int greth_init(struct eth_device *dev, bd_t * bis)
135 greth_priv *greth = dev->priv;
136 greth_regs *regs = greth->regs;
138 debug("greth_init\n");
141 GRETH_REGSAVE(®s->control, (GRETH_RESET | (greth->gb << 8) |
142 (greth->sp << 7) | (greth->fd << 4)));
144 /* Wait for Reset to complete */
145 while ( GRETH_REGLOAD(®s->control) & GRETH_RESET) ;
147 GRETH_REGSAVE(®s->control,
148 ((greth->gb << 8) | (greth->sp << 7) | (greth->fd << 4)));
150 if (!greth->rxbd_base) {
152 /* allocate descriptors */
153 greth->rxbd_base = (greth_bd *)
154 memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd));
155 greth->txbd_base = (greth_bd *)
156 memalign(0x1000, GRETH_TXBD_CNT * sizeof(greth_bd));
158 /* allocate buffers to all descriptors */
160 malloc(GRETH_RXBUF_EFF_SIZE * GRETH_RXBD_CNT);
163 /* initate rx decriptors */
164 for (i = 0; i < GRETH_RXBD_CNT; i++) {
165 greth->rxbd_base[i].addr = (unsigned int)
166 greth->rxbuf_base + (GRETH_RXBUF_EFF_SIZE * i);
167 /* enable desciptor & set wrap bit if last descriptor */
168 if (i >= (GRETH_RXBD_CNT - 1)) {
169 greth->rxbd_base[i].stat = GRETH_BD_EN | GRETH_BD_WR;
171 greth->rxbd_base[i].stat = GRETH_BD_EN;
175 /* initiate indexes */
176 greth->rxbd_curr = greth->rxbd_base;
177 greth->rxbd_max = greth->rxbd_base + (GRETH_RXBD_CNT - 1);
178 greth->txbd_max = greth->txbd_base + (GRETH_TXBD_CNT - 1);
180 * greth->txbd_base->addr = 0;
181 * greth->txbd_base->stat = GRETH_BD_WR;
184 /* initate tx decriptors */
185 for (i = 0; i < GRETH_TXBD_CNT; i++) {
186 greth->txbd_base[i].addr = 0;
187 /* enable desciptor & set wrap bit if last descriptor */
188 if (i >= (GRETH_TXBD_CNT - 1)) {
189 greth->txbd_base[i].stat = GRETH_BD_WR;
191 greth->txbd_base[i].stat = 0;
195 /**** SET HARDWARE REGS ****/
197 /* Set pointer to tx/rx descriptor areas */
198 GRETH_REGSAVE(®s->rx_desc_p, (unsigned int)&greth->rxbd_base[0]);
199 GRETH_REGSAVE(®s->tx_desc_p, (unsigned int)&greth->txbd_base[0]);
201 /* Enable Transmitter, GRETH will now scan descriptors for packets
203 debug("greth_init: enabling receiver\n");
204 GRETH_REGORIN(®s->control, GRETH_RXEN);
209 /* Initiate PHY to a relevant speed
214 int greth_init_phy(greth_priv * dev, bd_t * bis)
216 greth_regs *regs = dev->regs;
217 int tmp, tmp1, tmp2, i;
218 unsigned int start, timeout;
219 int phyaddr = GRETH_PHY_ADR_DEFAULT;
221 #ifndef CONFIG_SYS_GRLIB_GRETH_PHYADDR
222 /* If BSP doesn't provide a hardcoded PHY address the driver will
223 * try to autodetect PHY address by stopping the search on the first
224 * PHY address which has REG0 implemented.
226 for (i=0; i<32; i++) {
227 tmp = read_mii(i, 0, regs);
228 if ( (tmp != 0) && (tmp != 0xffff) ) {
235 /* Save PHY Address */
236 dev->phyaddr = phyaddr;
238 debug("GRETH PHY ADDRESS: %d\n", phyaddr);
240 /* X msecs to ticks */
241 timeout = usec2ticks(GRETH_PHY_TIMEOUT_MS * 1000);
243 /* Get system timer0 current value
244 * Total timeout is 5s
246 start = get_timer(0);
248 /* get phy control register default values */
250 while ((tmp = read_mii(phyaddr, 0, regs)) & 0x8000) {
251 if (get_timer(start) > timeout) {
252 debug("greth_init_phy: PHY read 1 failed\n");
257 /* reset PHY and wait for completion */
258 write_mii(phyaddr, 0, 0x8000 | tmp, regs);
260 while (((tmp = read_mii(phyaddr, 0, regs))) & 0x8000) {
261 if (get_timer(start) > timeout) {
262 debug("greth_init_phy: PHY read 2 failed\n");
267 /* Check if PHY is autoneg capable and then determine operating
268 * mode, otherwise force it to 10 Mbit halfduplex
274 if (!((tmp >> 12) & 1)) {
275 write_mii(phyaddr, 0, 0, regs);
277 /* wait for auto negotiation to complete and then check operating mode */
280 while (!(((tmp = read_mii(phyaddr, 1, regs)) >> 5) & 1)) {
281 if (get_timer(start) > timeout) {
282 printf("Auto negotiation timed out. "
283 "Selecting default config\n");
284 tmp = read_mii(phyaddr, 0, regs);
285 dev->gb = ((tmp >> 6) & 1)
286 && !((tmp >> 13) & 1);
287 dev->sp = !((tmp >> 6) & 1)
288 && ((tmp >> 13) & 1);
289 dev->fd = (tmp >> 8) & 1;
293 if ((tmp >> 8) & 1) {
294 tmp1 = read_mii(phyaddr, 9, regs);
295 tmp2 = read_mii(phyaddr, 10, regs);
296 if ((tmp1 & GRETH_MII_EXTADV_1000FD) &&
297 (tmp2 & GRETH_MII_EXTPRT_1000FD)) {
301 if ((tmp1 & GRETH_MII_EXTADV_1000HD) &&
302 (tmp2 & GRETH_MII_EXTPRT_1000HD)) {
307 if ((dev->gb == 0) || ((dev->gb == 1) && (dev->gbit_mac == 0))) {
308 tmp1 = read_mii(phyaddr, 4, regs);
309 tmp2 = read_mii(phyaddr, 5, regs);
310 if ((tmp1 & GRETH_MII_100TXFD) &&
311 (tmp2 & GRETH_MII_100TXFD)) {
315 if ((tmp1 & GRETH_MII_100TXHD) &&
316 (tmp2 & GRETH_MII_100TXHD)) {
320 if ((tmp1 & GRETH_MII_10FD) && (tmp2 & GRETH_MII_10FD)) {
323 if ((dev->gb == 1) && (dev->gbit_mac == 0)) {
326 write_mii(phyaddr, 0, dev->sp << 13, regs);
332 debug("%s GRETH Ethermac at [0x%x] irq %d. Running \
333 %d Mbps %s duplex\n", dev->gbit_mac ? "10/100/1000" : "10/100", (unsigned int)(regs), (unsigned int)(dev->irq), dev->gb ? 1000 : (dev->sp ? 100 : 10), dev->fd ? "full" : "half");
334 /* Read out PHY info if extended registers are available */
336 tmp1 = read_mii(phyaddr, 2, regs);
337 tmp2 = read_mii(phyaddr, 3, regs);
338 tmp1 = (tmp1 << 6) | ((tmp2 >> 10) & 0x3F);
341 tmp2 = (tmp2 >> 4) & 0x3F;
342 debug("PHY: Vendor %x Device %x Revision %d\n", tmp1,
345 printf("PHY info not available\n");
348 /* set speed and duplex bits in control register */
349 GRETH_REGORIN(®s->control,
350 (dev->gb << 8) | (dev->sp << 7) | (dev->fd << 4));
355 void greth_halt(struct eth_device *dev)
361 debug("greth_halt\n");
363 if (!dev || !dev->priv)
372 /* disable receiver/transmitter by clearing the enable bits */
373 GRETH_REGANDIN(®s->control, ~(GRETH_RXEN | GRETH_TXEN));
375 /* reset rx/tx descriptors */
376 if (greth->rxbd_base) {
377 for (i = 0; i < GRETH_RXBD_CNT; i++) {
378 greth->rxbd_base[i].stat =
379 (i >= (GRETH_RXBD_CNT - 1)) ? GRETH_BD_WR : 0;
383 if (greth->txbd_base) {
384 for (i = 0; i < GRETH_TXBD_CNT; i++) {
385 greth->txbd_base[i].stat =
386 (i >= (GRETH_TXBD_CNT - 1)) ? GRETH_BD_WR : 0;
391 int greth_send(struct eth_device *dev, void *eth_data, int data_length)
393 greth_priv *greth = dev->priv;
394 greth_regs *regs = greth->regs;
399 debug("greth_send\n");
401 /* send data, wait for data to be sent, then return */
402 if (((unsigned int)eth_data & (GRETH_BUF_ALIGN - 1))
403 && !greth->gbit_mac) {
404 /* data not aligned as needed by GRETH 10/100, solve this by allocating 4 byte aligned buffer
405 * and copy data to before giving it to GRETH.
408 greth->txbuf = malloc(GRETH_RXBUF_SIZE);
411 txbuf = greth->txbuf;
413 /* copy data info buffer */
414 memcpy((char *)txbuf, (char *)eth_data, data_length);
416 /* keep buffer to next time */
418 txbuf = (void *)eth_data;
420 /* get descriptor to use, only 1 supported... hehe easy */
421 txbd = greth->txbd_base;
423 /* setup descriptor to wrap around to it self */
424 txbd->addr = (unsigned int)txbuf;
425 txbd->stat = GRETH_BD_EN | GRETH_BD_WR | data_length;
427 /* Remind Core which descriptor to use when sending */
428 GRETH_REGSAVE(®s->tx_desc_p, (unsigned int)txbd);
430 /* initate send by enabling transmitter */
431 GRETH_REGORIN(®s->control, GRETH_TXEN);
433 /* Wait for data to be sent */
434 while ((status = GRETH_REGLOAD(&txbd->stat)) & GRETH_BD_EN) {
438 /* was the packet transmitted succesfully? */
439 if (status & GRETH_TXBD_ERR_AL) {
440 greth->stats.tx_limit_errors++;
443 if (status & GRETH_TXBD_ERR_UE) {
444 greth->stats.tx_underrun_errors++;
447 if (status & GRETH_TXBD_ERR_LC) {
448 greth->stats.tx_latecol_errors++;
452 (GRETH_TXBD_ERR_LC | GRETH_TXBD_ERR_UE | GRETH_TXBD_ERR_AL)) {
454 greth->stats.tx_errors++;
458 /* bump tx packet counter */
459 greth->stats.tx_packets++;
461 /* return succefully */
465 int greth_recv(struct eth_device *dev)
467 greth_priv *greth = dev->priv;
468 greth_regs *regs = greth->regs;
470 unsigned int status, len = 0, bad;
475 /* Receive One packet only, but clear as many error packets as there are
479 /* current receive descriptor */
480 rxbd = greth->rxbd_curr;
482 /* get status of next received packet */
483 status = GRETH_REGLOAD(&rxbd->stat);
487 /* stop if no more packets received */
488 if (status & GRETH_BD_EN) {
492 debug("greth_recv: packet 0x%x, 0x%x, len: %d\n",
493 (unsigned int)rxbd, status, status & GRETH_BD_LEN);
495 /* Check status for errors.
497 if (status & GRETH_RXBD_ERR_FT) {
498 greth->stats.rx_length_errors++;
501 if (status & (GRETH_RXBD_ERR_AE | GRETH_RXBD_ERR_OE)) {
502 greth->stats.rx_frame_errors++;
505 if (status & GRETH_RXBD_ERR_CRC) {
506 greth->stats.rx_crc_errors++;
510 greth->stats.rx_errors++;
512 ("greth_recv: Bad packet (%d, %d, %d, 0x%08x, %d)\n",
513 greth->stats.rx_length_errors,
514 greth->stats.rx_frame_errors,
515 greth->stats.rx_crc_errors, status,
516 greth->stats.rx_packets);
517 /* print all rx descriptors */
518 for (i = 0; i < GRETH_RXBD_CNT; i++) {
519 printf("[%d]: Stat=0x%lx, Addr=0x%lx\n", i,
520 GRETH_REGLOAD(&greth->rxbd_base[i].stat),
521 GRETH_REGLOAD(&greth->rxbd_base[i].addr));
524 /* Process the incoming packet. */
525 len = status & GRETH_BD_LEN;
526 d = (char *)rxbd->addr;
529 ("greth_recv: new packet, length: %d. data: %x %x %x %x %x %x %x %x\n",
530 len, d[0], d[1], d[2], d[3], d[4], d[5], d[6],
533 /* flush all data cache to make sure we're not reading old packet data */
534 sparc_dcache_flush_all();
536 /* pass packet on to network subsystem */
537 net_process_received_packet((void *)d, len);
539 /* bump stats counters */
540 greth->stats.rx_packets++;
542 /* bad is now 0 ==> will stop loop */
545 /* reenable descriptor to receive more packet with this descriptor, wrap around if needed */
548 (((unsigned int)greth->rxbd_curr >=
549 (unsigned int)greth->rxbd_max) ? GRETH_BD_WR : 0);
554 ((unsigned int)greth->rxbd_curr >=
555 (unsigned int)greth->rxbd_max) ? greth->
556 rxbd_base : (greth->rxbd_curr + 1);
561 GRETH_REGORIN(®s->control, GRETH_RXEN);
564 /* return positive length of packet or 0 if non received */
568 void greth_set_hwaddr(greth_priv * greth, unsigned char *mac)
570 /* save new MAC address */
571 greth->dev->enetaddr[0] = greth->hwaddr[0] = mac[0];
572 greth->dev->enetaddr[1] = greth->hwaddr[1] = mac[1];
573 greth->dev->enetaddr[2] = greth->hwaddr[2] = mac[2];
574 greth->dev->enetaddr[3] = greth->hwaddr[3] = mac[3];
575 greth->dev->enetaddr[4] = greth->hwaddr[4] = mac[4];
576 greth->dev->enetaddr[5] = greth->hwaddr[5] = mac[5];
577 greth->regs->esa_msb = (mac[0] << 8) | mac[1];
578 greth->regs->esa_lsb =
579 (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5];
581 debug("GRETH: New MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",
582 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
585 int greth_initialize(bd_t * bis)
588 ambapp_apbdev apbdev;
589 struct eth_device *dev;
591 char *addr_str, *end;
592 unsigned char addr[6];
594 debug("Scanning for GRETH\n");
596 /* Find Device & IRQ via AMBA Plug&Play information */
597 if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_ETHMAC, &apbdev) != 1) {
598 return -1; /* GRETH not found */
601 greth = (greth_priv *) malloc(sizeof(greth_priv));
602 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
603 memset(dev, 0, sizeof(struct eth_device));
604 memset(greth, 0, sizeof(greth_priv));
606 greth->regs = (greth_regs *) apbdev.address;
607 greth->irq = apbdev.irq;
608 debug("Found GRETH at %p, irq %d\n", greth->regs, greth->irq);
609 dev->priv = (void *)greth;
610 dev->iobase = (unsigned int)greth->regs;
611 dev->init = greth_init;
612 dev->halt = greth_halt;
613 dev->send = greth_send;
614 dev->recv = greth_recv;
618 GRETH_REGSAVE(&greth->regs->control, GRETH_RESET);
620 /* Wait for core to finish reset cycle */
621 while (GRETH_REGLOAD(&greth->regs->control) & GRETH_RESET) ;
623 /* Get the phy address which assumed to have been set
624 correctly with the reset value in hardware */
625 greth->phyaddr = (GRETH_REGLOAD(&greth->regs->mdio) >> 11) & 0x1F;
627 /* Check if mac is gigabit capable */
628 greth->gbit_mac = (GRETH_REGLOAD(&greth->regs->control) >> 27) & 1;
630 /* Make descriptor string */
631 if (greth->gbit_mac) {
632 sprintf(dev->name, "GRETH_10/100/GB");
634 sprintf(dev->name, "GRETH_10/100");
637 /* initiate PHY, select speed/duplex depending on connected PHY */
638 if (greth_init_phy(greth, bis)) {
639 /* Failed to init PHY (timedout) */
640 debug("GRETH[%p]: Failed to init PHY\n", greth->regs);
644 /* Register Device to EtherNet subsystem */
647 /* Get MAC address */
648 if ((addr_str = getenv("ethaddr")) != NULL) {
649 for (i = 0; i < 6; i++) {
651 addr_str ? simple_strtoul(addr_str, &end, 16) : 0;
653 addr_str = (*end) ? end + 1 : end;
661 /* set and remember MAC address */
662 greth_set_hwaddr(greth, addr);
664 debug("GRETH[%p]: Initialized successfully\n", greth->regs);