2 * Ethernet driver for TI K2HK EVM.
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/ti-common/keystone_nav.h>
18 #include <asm/ti-common/keystone_net.h>
19 #include <asm/ti-common/keystone_serdes.h>
21 unsigned int emac_open;
22 static struct mii_dev *mdio_bus;
23 static unsigned int sys_has_mdio = 1;
25 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
26 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
28 #define emac_gigabit_enable(x) /* no gigabit to enable */
31 #define RX_BUFF_NUMS 24
32 #define RX_BUFF_LEN 1520
33 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
34 #define SGMII_ANEG_TIMEOUT 4000
36 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
38 struct rx_buff_desc net_rx_buffs = {
40 .num_buffs = RX_BUFF_NUMS,
41 .buff_len = RX_BUFF_LEN,
45 #ifndef CONFIG_SOC_K2G
46 static void keystone2_net_serdes_setup(void);
49 int keystone2_eth_read_mac_addr(struct eth_device *dev)
51 struct eth_priv_t *eth_priv;
55 eth_priv = (struct eth_priv_t *)dev->priv;
57 /* Read the e-fuse mac address */
58 if (eth_priv->slave_port == 1) {
59 maca = __raw_readl(MAC_ID_BASE_ADDR);
60 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
63 dev->enetaddr[0] = (macb >> 8) & 0xff;
64 dev->enetaddr[1] = (macb >> 0) & 0xff;
65 dev->enetaddr[2] = (maca >> 24) & 0xff;
66 dev->enetaddr[3] = (maca >> 16) & 0xff;
67 dev->enetaddr[4] = (maca >> 8) & 0xff;
68 dev->enetaddr[5] = (maca >> 0) & 0xff;
75 static int keystone2_mdio_reset(struct mii_dev *bus)
78 struct mdio_regs *adap_mdio = bus->priv;
80 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
82 writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE |
83 MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
86 while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
93 * keystone2_mdio_read - read a PHY register via MDIO interface.
94 * Blocks until operation is complete.
96 static int keystone2_mdio_read(struct mii_dev *bus,
97 int addr, int devad, int reg)
100 struct mdio_regs *adap_mdio = bus->priv;
102 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
105 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
106 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
107 &adap_mdio->useraccess0);
109 /* Wait for command to complete */
110 while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
113 if (tmp & MDIO_USERACCESS0_ACK)
120 * keystone2_mdio_write - write to a PHY register via MDIO interface.
121 * Blocks until operation is complete.
123 static int keystone2_mdio_write(struct mii_dev *bus,
124 int addr, int devad, int reg, u16 val)
126 struct mdio_regs *adap_mdio = bus->priv;
128 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
131 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
132 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
133 (val & 0xffff), &adap_mdio->useraccess0);
135 /* Wait for command to complete */
136 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
142 static void __attribute__((unused))
143 keystone2_eth_gigabit_enable(struct eth_device *dev)
146 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
149 data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
151 /* speed selection MSB */
152 if (!(data & (1 << 6)))
157 * Check if link detected is giga-bit
158 * If Gigabit mode detected, enable gigbit in MAC
160 writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
162 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
163 DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
166 #ifdef CONFIG_SOC_K2G
167 int keystone_rgmii_config(struct phy_device *phy_dev)
169 unsigned int i, status;
173 if (i > SGMII_ANEG_TIMEOUT) {
174 puts(" TIMEOUT !\n");
180 puts("user interrupt!\n");
185 if ((i++ % 500) == 0)
188 udelay(1000); /* 1 ms */
189 status = readl(RGMII_STATUS_REG);
190 } while (!(status & RGMII_REG_STATUS_LINK));
197 int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
199 unsigned int i, status, mask;
200 unsigned int mr_adv_ability, control;
203 case SGMII_LINK_MAC_MAC_AUTONEG:
204 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
205 SGMII_REG_MR_ADV_LINK |
206 SGMII_REG_MR_ADV_FULL_DUPLEX |
207 SGMII_REG_MR_ADV_GIG_MODE);
208 control = (SGMII_REG_CONTROL_MASTER |
209 SGMII_REG_CONTROL_AUTONEG);
212 case SGMII_LINK_MAC_PHY:
213 case SGMII_LINK_MAC_PHY_FORCED:
214 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
215 control = SGMII_REG_CONTROL_AUTONEG;
218 case SGMII_LINK_MAC_MAC_FORCED:
219 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
220 SGMII_REG_MR_ADV_LINK |
221 SGMII_REG_MR_ADV_FULL_DUPLEX |
222 SGMII_REG_MR_ADV_GIG_MODE);
223 control = SGMII_REG_CONTROL_MASTER;
226 case SGMII_LINK_MAC_FIBER:
227 mr_adv_ability = 0x20;
228 control = SGMII_REG_CONTROL_AUTONEG;
232 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
233 control = SGMII_REG_CONTROL_AUTONEG;
236 __raw_writel(0, SGMII_CTL_REG(port));
239 * Wait for the SerDes pll to lock,
240 * but don't trap if lock is never read
242 for (i = 0; i < 1000; i++) {
244 status = __raw_readl(SGMII_STATUS_REG(port));
245 if ((status & SGMII_REG_STATUS_LOCK) != 0)
249 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
250 __raw_writel(control, SGMII_CTL_REG(port));
253 mask = SGMII_REG_STATUS_LINK;
255 if (control & SGMII_REG_CONTROL_AUTONEG)
256 mask |= SGMII_REG_STATUS_AUTONEG;
258 status = __raw_readl(SGMII_STATUS_REG(port));
259 if ((status & mask) == mask)
262 printf("\n%s Waiting for SGMII auto negotiation to complete",
264 while ((status & mask) != mask) {
268 if (i > SGMII_ANEG_TIMEOUT) {
269 puts(" TIMEOUT !\n");
275 puts("user interrupt!\n");
280 if ((i++ % 500) == 0)
283 udelay(1000); /* 1 ms */
284 status = __raw_readl(SGMII_STATUS_REG(port));
292 int mac_sl_reset(u32 port)
296 if (port >= DEVICE_N_GMACSL_PORTS)
297 return GMACSL_RET_INVALID_PORT;
299 /* Set the soft reset bit */
300 writel(CPGMAC_REG_RESET_VAL_RESET,
301 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
303 /* Wait for the bit to clear */
304 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
305 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
306 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
307 CPGMAC_REG_RESET_VAL_RESET)
308 return GMACSL_RET_OK;
311 /* Timeout on the reset */
312 return GMACSL_RET_WARN_RESET_INCOMPLETE;
315 int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
318 int ret = GMACSL_RET_OK;
320 if (port >= DEVICE_N_GMACSL_PORTS)
321 return GMACSL_RET_INVALID_PORT;
323 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
324 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
325 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
328 /* Must wait if the device is undergoing reset */
329 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
330 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
331 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
332 CPGMAC_REG_RESET_VAL_RESET)
336 if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
337 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
339 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
340 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
342 #ifndef CONFIG_SOC_K2HK
343 /* Map RX packet flow priority to 0 */
344 writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
350 int ethss_config(u32 ctl, u32 max_pkt_size)
354 /* Max length register */
355 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
357 /* Control register */
358 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
360 /* All statistics enabled by default */
361 writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
362 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
364 /* Reset and enable the ALE */
365 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
366 CPSW_REG_VAL_ALE_CTL_BYPASS,
367 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
369 /* All ports put into forward mode */
370 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
371 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
372 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
377 int ethss_start(void)
380 struct mac_sl_cfg cfg;
382 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
383 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
385 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
387 mac_sl_config(i, &cfg);
397 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
403 int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
405 if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
406 num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
408 return ksnav_send(&netcp_pktdma, buffer,
409 num_bytes, (slave_port_num) << 16);
412 /* Eth device open */
413 static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
415 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
416 struct phy_device *phy_dev = eth_priv->phy_dev;
418 debug("+ emac_open\n");
420 net_rx_buffs.rx_flow = eth_priv->rx_flow;
423 (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
426 keystone2_mdio_reset(mdio_bus);
428 #ifdef CONFIG_SOC_K2G
429 keystone_rgmii_config(phy_dev);
431 keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
432 eth_priv->sgmii_link_type);
437 /* On chip switch configuration */
438 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
440 /* TODO: add error handling code */
442 printf("ERROR: qm_init()\n");
445 if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
447 printf("ERROR: netcp_init()\n");
452 * Streaming switch configuration. If not present this
453 * statement is defined to void in target.h.
454 * If present this is usually defined to a series of register writes
456 hw_config_streaming_switch();
459 keystone2_mdio_reset(mdio_bus);
461 phy_startup(phy_dev);
462 if (phy_dev->link == 0) {
463 ksnav_close(&netcp_pktdma);
469 emac_gigabit_enable(dev);
473 debug("- emac_open\n");
480 /* Eth device close */
481 void keystone2_eth_close(struct eth_device *dev)
483 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
484 struct phy_device *phy_dev = eth_priv->phy_dev;
486 debug("+ emac_close\n");
493 ksnav_close(&netcp_pktdma);
495 phy_shutdown(phy_dev);
499 debug("- emac_close\n");
503 * This function sends a single packet on the network and returns
504 * positive number (number of bytes transmitted) or negative for error
506 static int keystone2_eth_send_packet(struct eth_device *dev,
507 void *packet, int length)
510 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
511 struct phy_device *phy_dev = eth_priv->phy_dev;
513 genphy_update_link(phy_dev);
514 if (phy_dev->link == 0)
517 if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
524 * This function handles receipt of a packet from the network
526 static int keystone2_eth_rcv_packet(struct eth_device *dev)
532 hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
536 net_process_received_packet((uchar *)pkt, pkt_size);
538 ksnav_release_rxhd(&netcp_pktdma, hd);
543 #ifdef CONFIG_MCAST_TFTP
544 static int keystone2_eth_bcast_addr(struct eth_device *dev, u32 ip, u8 set)
551 * This function initializes the EMAC hardware.
553 int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
556 struct eth_device *dev;
557 struct phy_device *phy_dev;
559 dev = malloc(sizeof(struct eth_device));
563 memset(dev, 0, sizeof(struct eth_device));
565 strcpy(dev->name, eth_priv->int_name);
566 dev->priv = eth_priv;
568 keystone2_eth_read_mac_addr(dev);
571 dev->init = keystone2_eth_open;
572 dev->halt = keystone2_eth_close;
573 dev->send = keystone2_eth_send_packet;
574 dev->recv = keystone2_eth_rcv_packet;
575 #ifdef CONFIG_MCAST_TFTP
576 dev->mcast = keystone2_eth_bcast_addr;
581 /* Register MDIO bus if it's not registered yet */
583 mdio_bus = mdio_alloc();
584 mdio_bus->read = keystone2_mdio_read;
585 mdio_bus->write = keystone2_mdio_write;
586 mdio_bus->reset = keystone2_mdio_reset;
587 mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR;
588 sprintf(mdio_bus->name, "ethernet-mdio");
590 res = mdio_register(mdio_bus);
595 #ifndef CONFIG_SOC_K2G
596 keystone2_net_serdes_setup();
599 /* Create phy device and bind it with driver */
600 #ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
601 phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
602 dev, eth_priv->phy_if);
605 phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
609 eth_priv->phy_dev = phy_dev;
614 struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
615 .clk = SERDES_CLOCK_156P25M,
616 .rate = SERDES_RATE_5G,
617 .rate_mode = SERDES_QUARTER_RATE,
618 .intf = SERDES_PHY_SGMII,
622 #ifndef CONFIG_SOC_K2G
623 static void keystone2_net_serdes_setup(void)
625 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
626 &ks2_serdes_sgmii_156p25mhz,
627 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
629 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
630 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
631 &ks2_serdes_sgmii_156p25mhz,
632 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
635 /* wait till setup */