3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
7 * Ingo Assmus <ingo.assmus@keymile.com>
9 * based on - Driver for MV64360X ethernet ports
10 * Copyright (C) 2002 rabeeh@galileo.co.il
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
35 #include <asm/errno.h>
36 #include <asm/types.h>
37 #include <asm/byteorder.h>
38 #include <asm/arch/kirkwood.h>
39 #include "kirkwood_egiga.h"
41 #define KIRKWOOD_PHY_ADR_REQUEST 0xee
44 * smi_reg_read - miiphy_read callback function.
46 * Returns 16bit phy register value, or 0xffff on error
48 static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
50 struct eth_device *dev = eth_get_dev_by_name(devname);
51 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
52 struct kwgbe_registers *regs = dkwgbe->regs;
56 /* Phyadr read request */
57 if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
58 reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
60 *data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK);
63 /* check parameters */
64 if (phy_adr > PHYADR_MASK) {
65 printf("Err..(%s) Invalid PHY address %d\n",
66 __FUNCTION__, phy_adr);
69 if (reg_ofs > PHYREG_MASK) {
70 printf("Err..(%s) Invalid register offset %d\n",
71 __FUNCTION__, reg_ofs);
75 timeout = KWGBE_PHY_SMI_TIMEOUT;
76 /* wait till the SMI is not busy */
78 /* read smi register */
79 smi_reg = KWGBEREG_RD(regs->smi);
81 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
84 } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
86 /* fill the phy address and regiser offset and read opcode */
87 smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
88 | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS)
89 | KWGBE_PHY_SMI_OPCODE_READ;
91 /* write the smi register */
92 KWGBEREG_WR(regs->smi, smi_reg);
94 /*wait till read value is ready */
95 timeout = KWGBE_PHY_SMI_TIMEOUT;
98 /* read smi register */
99 smi_reg = KWGBEREG_RD(regs->smi);
100 if (timeout-- == 0) {
101 printf("Err..(%s) SMI read ready timeout\n",
105 } while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK));
107 /* Wait for the data to update in the SMI register */
108 for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ;
110 *data = (u16) (KWGBEREG_RD(regs->smi) & KWGBE_PHY_SMI_DATA_MASK);
112 debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
119 * smi_reg_write - imiiphy_write callback function.
121 * Returns 0 if write succeed, -EINVAL on bad parameters
124 static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
126 struct eth_device *dev = eth_get_dev_by_name(devname);
127 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
128 struct kwgbe_registers *regs = dkwgbe->regs;
132 /* Phyadr write request*/
133 if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
134 reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
135 KWGBEREG_WR(regs->phyadr, data);
139 /* check parameters */
140 if (phy_adr > PHYADR_MASK) {
141 printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
144 if (reg_ofs > PHYREG_MASK) {
145 printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
149 /* wait till the SMI is not busy */
150 timeout = KWGBE_PHY_SMI_TIMEOUT;
152 /* read smi register */
153 smi_reg = KWGBEREG_RD(regs->smi);
154 if (timeout-- == 0) {
155 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
158 } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
160 /* fill the phy addr and reg offset and write opcode and data */
161 smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS);
162 smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
163 | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS);
164 smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ;
166 /* write the smi register */
167 KWGBEREG_WR(regs->smi, smi_reg);
172 /* Stop and checks all queues */
173 static void stop_queue(u32 * qreg)
177 reg_data = readl(qreg);
179 if (reg_data & 0xFF) {
180 /* Issue stop command for active channels only */
181 writel((reg_data << 8), qreg);
183 /* Wait for all queue activity to terminate. */
186 * Check port cause register that all queues
189 reg_data = readl(qreg);
191 while (reg_data & 0xFF);
196 * set_access_control - Config address decode parameters for Ethernet unit
198 * This function configures the address decode parameters for the Gigabit
199 * Ethernet Controller according the given parameters struct.
201 * @regs Register struct pointer.
202 * @param Address decode parameter struct.
204 static void set_access_control(struct kwgbe_registers *regs,
205 struct kwgbe_winparam *param)
209 /* Set access control register */
210 access_prot_reg = KWGBEREG_RD(regs->epap);
211 /* clear window permission */
212 access_prot_reg &= (~(3 << (param->win * 2)));
213 access_prot_reg |= (param->access_ctrl << (param->win * 2));
214 KWGBEREG_WR(regs->epap, access_prot_reg);
216 /* Set window Size reg (SR) */
217 KWGBEREG_WR(regs->barsz[param->win].size,
218 (((param->size / 0x10000) - 1) << 16));
220 /* Set window Base address reg (BA) */
221 KWGBEREG_WR(regs->barsz[param->win].bar,
222 (param->target | param->attrib | param->base_addr));
223 /* High address remap reg (HARR) */
225 KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr);
227 /* Base address enable reg (BARER) */
228 if (param->enable == 1)
229 KWGBEREG_BITS_RESET(regs->bare, (1 << param->win));
231 KWGBEREG_BITS_SET(regs->bare, (1 << param->win));
234 static void set_dram_access(struct kwgbe_registers *regs)
236 struct kwgbe_winparam win_param;
239 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
240 /* Set access parameters for DRAM bank i */
241 win_param.win = i; /* Use Ethernet window i */
242 /* Window target - DDR */
243 win_param.target = KWGBE_TARGET_DRAM;
244 /* Enable full access */
245 win_param.access_ctrl = EWIN_ACCESS_FULL;
246 win_param.high_addr = 0;
248 win_param.base_addr = kw_sdram_bar(i);
249 win_param.size = kw_sdram_bs(i); /* Get bank size */
250 if (win_param.size == 0)
251 win_param.enable = 0;
253 win_param.enable = 1; /* Enable the access */
255 /* Enable DRAM bank */
258 win_param.attrib = EBAR_DRAM_CS0;
261 win_param.attrib = EBAR_DRAM_CS1;
264 win_param.attrib = EBAR_DRAM_CS2;
267 win_param.attrib = EBAR_DRAM_CS3;
270 /* invalide bank, disable access */
271 win_param.enable = 0;
272 win_param.attrib = 0;
275 /* Set the access control for address window(EPAPR) RD/WR */
276 set_access_control(regs, &win_param);
281 * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
283 * Go through all the DA filter tables (Unicast, Special Multicast & Other
284 * Multicast) and set each entry to 0.
286 static void port_init_mac_tables(struct kwgbe_registers *regs)
290 /* Clear DA filter unicast table (Ex_dFUT) */
291 for (table_index = 0; table_index < 4; ++table_index)
292 KWGBEREG_WR(regs->dfut[table_index], 0);
294 for (table_index = 0; table_index < 64; ++table_index) {
295 /* Clear DA filter special multicast table (Ex_dFSMT) */
296 KWGBEREG_WR(regs->dfsmt[table_index], 0);
297 /* Clear DA filter other multicast table (Ex_dFOMT) */
298 KWGBEREG_WR(regs->dfomt[table_index], 0);
303 * port_uc_addr - This function Set the port unicast address table
305 * This function locates the proper entry in the Unicast table for the
306 * specified MAC nibble and sets its properties according to function
308 * This function add/removes MAC addresses from the port unicast address
311 * @uc_nibble Unicast MAC Address last nibble.
312 * @option 0 = Add, 1 = remove address.
314 * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
316 static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
323 /* Locate the Unicast table entry */
324 uc_nibble = (0xf & uc_nibble);
325 /* Register offset from unicast table base */
326 tbl_offset = (uc_nibble / 4);
327 /* Entry offset within the above register */
328 reg_offset = uc_nibble % 4;
331 case REJECT_MAC_ADDR:
333 * Clear accepts frame bit at specified unicast
336 unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
337 unicast_reg &= (0xFF << (8 * reg_offset));
338 KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
340 case ACCEPT_MAC_ADDR:
341 /* Set accepts frame bit at unicast DA filter table entry */
342 unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
343 unicast_reg &= (0xFF << (8 * reg_offset));
344 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
345 KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
354 * port_uc_addr_set - This function Set the port Unicast address.
356 static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
361 mac_l = (p_addr[4] << 8) | (p_addr[5]);
362 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
365 KWGBEREG_WR(regs->macal, mac_l);
366 KWGBEREG_WR(regs->macah, mac_h);
368 /* Accept frames of this address */
369 port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
373 * kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
375 static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe)
377 struct kwgbe_rxdesc *p_rx_desc;
380 /* initialize the Rx descriptors ring */
381 p_rx_desc = dkwgbe->p_rxdesc;
382 for (i = 0; i < RINGSZ; i++) {
384 KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
385 p_rx_desc->buf_size = PKTSIZE_ALIGN;
386 p_rx_desc->byte_cnt = 0;
387 p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN;
388 if (i == (RINGSZ - 1))
389 p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc;
391 p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *)
392 ((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE);
393 p_rx_desc = p_rx_desc->nxtdesc_p;
396 dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc;
399 static int kwgbe_init(struct eth_device *dev)
401 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
402 struct kwgbe_registers *regs = dkwgbe->regs;
406 kwgbe_init_rx_desc_ring(dkwgbe);
408 /* Clear the ethernet port interrupts */
409 KWGBEREG_WR(regs->ic, 0);
410 KWGBEREG_WR(regs->ice, 0);
411 /* Unmask RX buffer and TX end interrupt */
412 KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
413 /* Unmask phy and link status changes interrupts */
414 KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
416 set_dram_access(regs);
417 port_init_mac_tables(regs);
418 port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
420 /* Assign port configuration and command. */
421 KWGBEREG_WR(regs->pxc, PRT_CFG_VAL);
422 KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
423 KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
424 /* Disable port initially */
425 KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN);
427 /* Assign port SDMA configuration */
428 KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
429 KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
430 KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
431 /* Turn off the port/RXUQ bandwidth limitation */
432 KWGBEREG_WR(regs->pmtu, 0);
434 /* Set maximum receive buffer to 9700 bytes */
435 KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE
436 | (KWGBEREG_RD(regs->psc0) & MRU_MASK));
439 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
440 * disable the leaky bucket mechanism .
442 KWGBEREG_WR(regs->pmtu, 0);
444 /* Assignment of Rx CRDB of given RXUQ */
445 KWGBEREG_WR(regs->rxcdp[RXUQ].rxcdp, (u32) dkwgbe->p_rxdesc_curr);
446 /* Enable port Rx. */
447 KWGBEREG_WR(regs->rqc, (1 << RXUQ));
449 #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
450 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
451 /* Wait up to 5s for the link status */
452 for (i = 0; i < 5; i++) {
455 miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
456 KIRKWOOD_PHY_ADR_REQUEST, &phyadr);
457 /* Return if we get link up */
458 if (miiphy_link(dev->name, phyadr))
463 printf("No link on %s\n", dev->name);
469 static int kwgbe_halt(struct eth_device *dev)
471 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
472 struct kwgbe_registers *regs = dkwgbe->regs;
474 /* Disable all gigE address decoder */
475 KWGBEREG_WR(regs->bare, 0x3f);
477 stop_queue(®s->tqc);
478 stop_queue(®s->rqc);
481 KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN);
482 /* Set port is not reset */
483 KWGBEREG_BITS_RESET(regs->psc1, 1 << 4);
484 #ifdef CONFIG_SYS_MII_MODE
485 /* Set MMI interface up */
486 KWGBEREG_BITS_RESET(regs->psc1, 1 << 3);
488 /* Disable & mask ethernet port interrupts */
489 KWGBEREG_WR(regs->ic, 0);
490 KWGBEREG_WR(regs->ice, 0);
491 KWGBEREG_WR(regs->pim, 0);
492 KWGBEREG_WR(regs->peim, 0);
497 static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
500 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
501 struct kwgbe_registers *regs = dkwgbe->regs;
502 struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc;
505 if ((u32) dataptr & 0x07) {
506 printf("Err..(%s) xmit dataptr not 64bit aligned\n",
510 p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC;
511 p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC;
512 p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA;
513 p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT;
514 p_txdesc->buf_ptr = (u8 *) dataptr;
515 p_txdesc->byte_cnt = datasize;
517 /* Apply send command using zeroth RXUQ */
518 KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
519 KWGBEREG_WR(regs->tqc, (1 << TXUQ));
522 * wait for packet xmit completion
524 cmd_sts = readl(&p_txdesc->cmd_sts);
525 while (cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) {
526 /* return fail if error is detected */
527 if ((cmd_sts & (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME)) ==
528 (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME) &&
529 cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) {
530 printf("Err..(%s) in xmit packet\n", __FUNCTION__);
533 cmd_sts = readl(&p_txdesc->cmd_sts);
538 static int kwgbe_recv(struct eth_device *dev)
540 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
541 struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr;
545 /* wait untill rx packet available or timeout */
547 if (timeout < KWGBE_PHY_SMI_TIMEOUT)
550 debug("%s time out...\n", __FUNCTION__);
553 } while (readl(&p_rxdesc_curr->cmd_sts) & KWGBE_BUFFER_OWNED_BY_DMA);
555 if (p_rxdesc_curr->byte_cnt != 0) {
556 debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
557 __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
558 (u32) p_rxdesc_curr->buf_ptr,
559 (u32) p_rxdesc_curr->cmd_sts);
563 * In case received a packet without first/last bits on
564 * OR the error summary bit is on,
565 * the packets needs to be dropeed.
567 cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
570 (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC))
571 != (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) {
573 printf("Err..(%s) Dropping packet spread on"
574 " multiple descriptors\n", __FUNCTION__);
576 } else if (cmd_sts & KWGBE_ERROR_SUMMARY) {
578 printf("Err..(%s) Dropping packet with errors\n",
582 /* !!! call higher layer processing */
583 debug("%s: Sending Received packet to"
584 " upper layer (NetReceive)\n", __FUNCTION__);
586 /* let the upper layer handle the packet */
587 NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
588 (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
591 * free these descriptors and point next in the ring
593 p_rxdesc_curr->cmd_sts =
594 KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
595 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
596 p_rxdesc_curr->byte_cnt = 0;
598 writel((unsigned)p_rxdesc_curr->nxtdesc_p, &dkwgbe->p_rxdesc_curr);
603 int kirkwood_egiga_initialize(bd_t * bis)
605 struct kwgbe_device *dkwgbe;
606 struct eth_device *dev;
609 u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS;
611 for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) {
612 /*skip if port is configured not to use */
613 if (used_ports[devnum] == 0)
616 if (!(dkwgbe = malloc(sizeof(struct kwgbe_device))))
619 memset(dkwgbe, 0, sizeof(struct kwgbe_device));
621 if (!(dkwgbe->p_rxdesc =
622 (struct kwgbe_rxdesc *)memalign(PKTALIGN,
623 KW_RXQ_DESC_ALIGNED_SIZE
627 if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
628 * PKTSIZE_ALIGN + 1)))
631 if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *)
632 memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) {
633 free(dkwgbe->p_rxbuf);
635 free(dkwgbe->p_rxdesc);
639 printf("Err.. %s Failed to allocate memory\n",
646 /* must be less than NAMESIZE (16) */
647 sprintf(dev->name, "egiga%d", devnum);
649 /* Extract the MAC address from the environment */
652 dkwgbe->regs = (void *)KW_EGIGA0_BASE;
656 dkwgbe->regs = (void *)KW_EGIGA1_BASE;
659 default: /* this should never happen */
660 printf("Err..(%s) Invalid device number %d\n",
661 __FUNCTION__, devnum);
665 while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
666 /* Generate Random Private MAC addr if not set */
667 dev->enetaddr[0] = 0x02;
668 dev->enetaddr[1] = 0x50;
669 dev->enetaddr[2] = 0x43;
670 dev->enetaddr[3] = get_random_hex();
671 dev->enetaddr[4] = get_random_hex();
672 dev->enetaddr[5] = get_random_hex();
673 eth_setenv_enetaddr(s, dev->enetaddr);
676 dev->init = (void *)kwgbe_init;
677 dev->halt = (void *)kwgbe_halt;
678 dev->send = (void *)kwgbe_send;
679 dev->recv = (void *)kwgbe_recv;
683 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
684 miiphy_register(dev->name, smi_reg_read, smi_reg_write);
685 /* Set phy address of the port */
686 miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
687 KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);