2 * Copyright (C) 2005-2006 Atmel Corporation
4 * SPDX-License-Identifier: GPL-2.0+
10 * The u-boot networking stack is a little weird. It seems like the
11 * networking core allocates receive buffers up front without any
12 * regard to the hardware that's supposed to actually receive those
15 * The MACB receives packets into 128-byte receive buffers, so the
16 * buffers allocated by the core isn't very practical to use. We'll
17 * allocate our own, but we need one such buffer in case a packet
18 * wraps around the DMA ring so that we have to copy it.
20 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
21 * configuration header. This way, the core allocates one RX buffer
22 * and one TX buffer, each of which can hold a ethernet packet of
25 * For some reason, the networking core unconditionally specifies a
26 * 32-byte packet "alignment" (which really should be called
27 * "padding"). MACB shouldn't need that, but we'll refrain from any
28 * core modifications here...
38 #include <linux/mii.h>
40 #include <asm/dma-mapping.h>
41 #include <asm/arch/clk.h>
42 #include <asm-generic/errno.h>
46 DECLARE_GLOBAL_DATA_PTR;
48 #define MACB_RX_BUFFER_SIZE 4096
49 #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
50 #define MACB_TX_RING_SIZE 16
51 #define MACB_TX_TIMEOUT 1000
52 #define MACB_AUTONEG_TIMEOUT 5000000
54 struct macb_dma_desc {
59 #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
60 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
61 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
62 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
64 #define RXADDR_USED 0x00000001
65 #define RXADDR_WRAP 0x00000002
67 #define RXBUF_FRMLEN_MASK 0x00000fff
68 #define RXBUF_FRAME_START 0x00004000
69 #define RXBUF_FRAME_END 0x00008000
70 #define RXBUF_TYPEID_MATCH 0x00400000
71 #define RXBUF_ADDR4_MATCH 0x00800000
72 #define RXBUF_ADDR3_MATCH 0x01000000
73 #define RXBUF_ADDR2_MATCH 0x02000000
74 #define RXBUF_ADDR1_MATCH 0x04000000
75 #define RXBUF_BROADCAST 0x80000000
77 #define TXBUF_FRMLEN_MASK 0x000007ff
78 #define TXBUF_FRAME_END 0x00008000
79 #define TXBUF_NOCRC 0x00010000
80 #define TXBUF_EXHAUSTED 0x08000000
81 #define TXBUF_UNDERRUN 0x10000000
82 #define TXBUF_MAXRETRY 0x20000000
83 #define TXBUF_WRAP 0x40000000
84 #define TXBUF_USED 0x80000000
92 unsigned int next_rx_tail;
97 struct macb_dma_desc *rx_ring;
98 struct macb_dma_desc *tx_ring;
100 unsigned long rx_buffer_dma;
101 unsigned long rx_ring_dma;
102 unsigned long tx_ring_dma;
104 struct macb_dma_desc *dummy_desc;
105 unsigned long dummy_desc_dma;
107 const struct device *dev;
108 #ifndef CONFIG_DM_ETH
109 struct eth_device netdev;
111 unsigned short phy_addr;
115 phy_interface_t phy_interface;
118 #ifndef CONFIG_DM_ETH
119 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
122 static int macb_is_gem(struct macb_device *macb)
124 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
127 #ifndef cpu_is_sama5d2
128 #define cpu_is_sama5d2() 0
131 #ifndef cpu_is_sama5d4
132 #define cpu_is_sama5d4() 0
135 static int gem_is_gigabit_capable(struct macb_device *macb)
138 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
139 * configured to support only 10/100.
141 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
144 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
146 unsigned long netctl;
147 unsigned long netstat;
150 netctl = macb_readl(macb, NCR);
151 netctl |= MACB_BIT(MPE);
152 macb_writel(macb, NCR, netctl);
154 frame = (MACB_BF(SOF, 1)
156 | MACB_BF(PHYA, macb->phy_addr)
159 | MACB_BF(DATA, value));
160 macb_writel(macb, MAN, frame);
163 netstat = macb_readl(macb, NSR);
164 } while (!(netstat & MACB_BIT(IDLE)));
166 netctl = macb_readl(macb, NCR);
167 netctl &= ~MACB_BIT(MPE);
168 macb_writel(macb, NCR, netctl);
171 static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
173 unsigned long netctl;
174 unsigned long netstat;
177 netctl = macb_readl(macb, NCR);
178 netctl |= MACB_BIT(MPE);
179 macb_writel(macb, NCR, netctl);
181 frame = (MACB_BF(SOF, 1)
183 | MACB_BF(PHYA, macb->phy_addr)
186 macb_writel(macb, MAN, frame);
189 netstat = macb_readl(macb, NSR);
190 } while (!(netstat & MACB_BIT(IDLE)));
192 frame = macb_readl(macb, MAN);
194 netctl = macb_readl(macb, NCR);
195 netctl &= ~MACB_BIT(MPE);
196 macb_writel(macb, NCR, netctl);
198 return MACB_BFEXT(DATA, frame);
201 void __weak arch_get_mdio_control(const char *name)
206 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
208 int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
212 struct udevice *dev = eth_get_dev_by_name(bus->name);
213 struct macb_device *macb = dev_get_priv(dev);
215 struct eth_device *dev = eth_get_dev_by_name(bus->name);
216 struct macb_device *macb = to_macb(dev);
219 if (macb->phy_addr != phy_adr)
222 arch_get_mdio_control(bus->name);
223 value = macb_mdio_read(macb, reg);
228 int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
232 struct udevice *dev = eth_get_dev_by_name(bus->name);
233 struct macb_device *macb = dev_get_priv(dev);
235 struct eth_device *dev = eth_get_dev_by_name(bus->name);
236 struct macb_device *macb = to_macb(dev);
239 if (macb->phy_addr != phy_adr)
242 arch_get_mdio_control(bus->name);
243 macb_mdio_write(macb, reg, value);
251 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
254 invalidate_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
255 MACB_RX_DMA_DESC_SIZE);
257 invalidate_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
258 MACB_TX_DMA_DESC_SIZE);
261 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
264 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
265 MACB_RX_DMA_DESC_SIZE);
267 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
268 MACB_TX_DMA_DESC_SIZE);
271 static inline void macb_flush_rx_buffer(struct macb_device *macb)
273 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
274 MACB_RX_BUFFER_SIZE);
277 static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
279 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
280 MACB_RX_BUFFER_SIZE);
283 #if defined(CONFIG_CMD_NET)
285 static int _macb_send(struct macb_device *macb, const char *name, void *packet,
288 unsigned long paddr, ctrl;
289 unsigned int tx_head = macb->tx_head;
292 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
294 ctrl = length & TXBUF_FRMLEN_MASK;
295 ctrl |= TXBUF_FRAME_END;
296 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
303 macb->tx_ring[tx_head].ctrl = ctrl;
304 macb->tx_ring[tx_head].addr = paddr;
306 macb_flush_ring_desc(macb, TX);
307 /* Do we need check paddr and length is dcache line aligned? */
308 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
309 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
312 * I guess this is necessary because the networking core may
313 * re-use the transmit buffer as soon as we return...
315 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
317 macb_invalidate_ring_desc(macb, TX);
318 ctrl = macb->tx_ring[tx_head].ctrl;
319 if (ctrl & TXBUF_USED)
324 dma_unmap_single(packet, length, paddr);
326 if (i <= MACB_TX_TIMEOUT) {
327 if (ctrl & TXBUF_UNDERRUN)
328 printf("%s: TX underrun\n", name);
329 if (ctrl & TXBUF_EXHAUSTED)
330 printf("%s: TX buffers exhausted in mid frame\n", name);
332 printf("%s: TX timeout\n", name);
335 /* No one cares anyway */
339 static void reclaim_rx_buffers(struct macb_device *macb,
340 unsigned int new_tail)
346 macb_invalidate_ring_desc(macb, RX);
347 while (i > new_tail) {
348 macb->rx_ring[i].addr &= ~RXADDR_USED;
350 if (i > MACB_RX_RING_SIZE)
354 while (i < new_tail) {
355 macb->rx_ring[i].addr &= ~RXADDR_USED;
360 macb_flush_ring_desc(macb, RX);
361 macb->rx_tail = new_tail;
364 static int _macb_recv(struct macb_device *macb, uchar **packetp)
366 unsigned int next_rx_tail = macb->next_rx_tail;
371 macb->wrapped = false;
373 macb_invalidate_ring_desc(macb, RX);
375 if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED))
378 status = macb->rx_ring[next_rx_tail].ctrl;
379 if (status & RXBUF_FRAME_START) {
380 if (next_rx_tail != macb->rx_tail)
381 reclaim_rx_buffers(macb, next_rx_tail);
382 macb->wrapped = false;
385 if (status & RXBUF_FRAME_END) {
386 buffer = macb->rx_buffer + 128 * macb->rx_tail;
387 length = status & RXBUF_FRMLEN_MASK;
389 macb_invalidate_rx_buffer(macb);
391 unsigned int headlen, taillen;
393 headlen = 128 * (MACB_RX_RING_SIZE
395 taillen = length - headlen;
396 memcpy((void *)net_rx_packets[0],
398 memcpy((void *)net_rx_packets[0] + headlen,
399 macb->rx_buffer, taillen);
400 *packetp = (void *)net_rx_packets[0];
405 if (++next_rx_tail >= MACB_RX_RING_SIZE)
407 macb->next_rx_tail = next_rx_tail;
410 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
411 macb->wrapped = true;
419 static void macb_phy_reset(struct macb_device *macb, const char *name)
424 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
425 macb_mdio_write(macb, MII_ADVERTISE, adv);
426 printf("%s: Starting autonegotiation...\n", name);
427 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
430 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
431 status = macb_mdio_read(macb, MII_BMSR);
432 if (status & BMSR_ANEGCOMPLETE)
437 if (status & BMSR_ANEGCOMPLETE)
438 printf("%s: Autonegotiation complete\n", name);
440 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
444 #ifdef CONFIG_MACB_SEARCH_PHY
445 static int macb_phy_find(struct macb_device *macb, const char *name)
450 /* Search for PHY... */
451 for (i = 0; i < 32; i++) {
453 phy_id = macb_mdio_read(macb, MII_PHYSID1);
454 if (phy_id != 0xffff) {
455 printf("%s: PHY present at %d\n", name, i);
460 /* PHY isn't up to snuff */
461 printf("%s: PHY not found\n", name);
465 #endif /* CONFIG_MACB_SEARCH_PHY */
468 static int macb_phy_init(struct udevice *dev, const char *name)
470 static int macb_phy_init(struct macb_device *macb, const char *name)
474 struct macb_device *macb = dev_get_priv(dev);
477 struct phy_device *phydev;
480 u16 phy_id, status, adv, lpa;
481 int media, speed, duplex;
484 arch_get_mdio_control(name);
485 #ifdef CONFIG_MACB_SEARCH_PHY
486 /* Auto-detect phy_addr */
487 if (!macb_phy_find(macb, name))
489 #endif /* CONFIG_MACB_SEARCH_PHY */
491 /* Check if the PHY is up to snuff... */
492 phy_id = macb_mdio_read(macb, MII_PHYSID1);
493 if (phy_id == 0xffff) {
494 printf("%s: No PHY present\n", name);
500 phydev = phy_connect(macb->bus, macb->phy_addr, dev,
501 macb->phy_interface);
503 /* need to consider other phy interface mode */
504 phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
505 PHY_INTERFACE_MODE_RGMII);
508 printf("phy_connect failed\n");
515 status = macb_mdio_read(macb, MII_BMSR);
516 if (!(status & BMSR_LSTATUS)) {
517 /* Try to re-negotiate if we don't have link already. */
518 macb_phy_reset(macb, name);
520 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
521 status = macb_mdio_read(macb, MII_BMSR);
522 if (status & BMSR_LSTATUS)
528 if (!(status & BMSR_LSTATUS)) {
529 printf("%s: link down (status: 0x%04x)\n",
534 /* First check for GMAC and that it is GiB capable */
535 if (gem_is_gigabit_capable(macb)) {
536 lpa = macb_mdio_read(macb, MII_STAT1000);
538 if (lpa & (LPA_1000FULL | LPA_1000HALF)) {
539 duplex = ((lpa & LPA_1000FULL) ? 1 : 0);
541 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
543 duplex ? "full" : "half",
546 ncfgr = macb_readl(macb, NCFGR);
547 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
548 ncfgr |= GEM_BIT(GBE);
551 ncfgr |= MACB_BIT(FD);
553 macb_writel(macb, NCFGR, ncfgr);
559 /* fall back for EMAC checking */
560 adv = macb_mdio_read(macb, MII_ADVERTISE);
561 lpa = macb_mdio_read(macb, MII_LPA);
562 media = mii_nway_result(lpa & adv);
563 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
565 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
566 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
568 speed ? "100" : "10",
569 duplex ? "full" : "half",
572 ncfgr = macb_readl(macb, NCFGR);
573 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
575 ncfgr |= MACB_BIT(SPD);
577 ncfgr |= MACB_BIT(FD);
578 macb_writel(macb, NCFGR, ncfgr);
583 static int gmac_init_multi_queues(struct macb_device *macb)
585 int i, num_queues = 1;
588 /* bit 0 is never set but queue 0 always exists */
589 queue_mask = gem_readl(macb, DCFG6) & 0xff;
592 for (i = 1; i < MACB_MAX_QUEUES; i++)
593 if (queue_mask & (1 << i))
596 macb->dummy_desc->ctrl = TXBUF_USED;
597 macb->dummy_desc->addr = 0;
598 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
599 MACB_TX_DUMMY_DMA_DESC_SIZE);
601 for (i = 1; i < num_queues; i++)
602 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
608 static int _macb_init(struct udevice *dev, const char *name)
610 static int _macb_init(struct macb_device *macb, const char *name)
614 struct macb_device *macb = dev_get_priv(dev);
620 * macb_halt should have been called at some point before now,
621 * so we'll assume the controller is idle.
624 /* initialize DMA descriptors */
625 paddr = macb->rx_buffer_dma;
626 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
627 if (i == (MACB_RX_RING_SIZE - 1))
628 paddr |= RXADDR_WRAP;
629 macb->rx_ring[i].addr = paddr;
630 macb->rx_ring[i].ctrl = 0;
633 macb_flush_ring_desc(macb, RX);
634 macb_flush_rx_buffer(macb);
636 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
637 macb->tx_ring[i].addr = 0;
638 if (i == (MACB_TX_RING_SIZE - 1))
639 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
641 macb->tx_ring[i].ctrl = TXBUF_USED;
643 macb_flush_ring_desc(macb, TX);
648 macb->next_rx_tail = 0;
650 macb_writel(macb, RBQP, macb->rx_ring_dma);
651 macb_writel(macb, TBQP, macb->tx_ring_dma);
653 if (macb_is_gem(macb)) {
654 /* Check the multi queue and initialize the queue for tx */
655 gmac_init_multi_queues(macb);
658 * When the GMAC IP with GE feature, this bit is used to
659 * select interface between RGMII and GMII.
660 * When the GMAC IP without GE feature, this bit is used
661 * to select interface between RMII and MII.
664 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
665 gem_writel(macb, UR, GEM_BIT(RGMII));
667 gem_writel(macb, UR, 0);
669 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
670 gem_writel(macb, UR, GEM_BIT(RGMII));
672 gem_writel(macb, UR, 0);
676 /* choose RMII or MII mode. This depends on the board */
678 #ifdef CONFIG_AT91FAMILY
679 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
680 macb_writel(macb, USRIO,
681 MACB_BIT(RMII) | MACB_BIT(CLKEN));
683 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
686 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
687 macb_writel(macb, USRIO, 0);
689 macb_writel(macb, USRIO, MACB_BIT(MII));
693 #ifdef CONFIG_AT91FAMILY
694 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
696 macb_writel(macb, USRIO, 0);
699 #ifdef CONFIG_AT91FAMILY
700 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
702 macb_writel(macb, USRIO, MACB_BIT(MII));
704 #endif /* CONFIG_RMII */
709 if (!macb_phy_init(dev, name))
711 if (!macb_phy_init(macb, name))
715 /* Enable TX and RX */
716 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
721 static void _macb_halt(struct macb_device *macb)
725 /* Halt the controller and wait for any ongoing transmission to end. */
726 ncr = macb_readl(macb, NCR);
727 ncr |= MACB_BIT(THALT);
728 macb_writel(macb, NCR, ncr);
731 tsr = macb_readl(macb, TSR);
732 } while (tsr & MACB_BIT(TGO));
734 /* Disable TX and RX, and clear statistics */
735 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
738 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
743 /* set hardware address */
744 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
745 enetaddr[2] << 16 | enetaddr[3] << 24;
746 macb_writel(macb, SA1B, hwaddr_bottom);
747 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
748 macb_writel(macb, SA1T, hwaddr_top);
752 static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
755 unsigned long macb_hz = get_macb_pclk_rate(id);
757 if (macb_hz < 20000000)
758 config = MACB_BF(CLK, MACB_CLK_DIV8);
759 else if (macb_hz < 40000000)
760 config = MACB_BF(CLK, MACB_CLK_DIV16);
761 else if (macb_hz < 80000000)
762 config = MACB_BF(CLK, MACB_CLK_DIV32);
764 config = MACB_BF(CLK, MACB_CLK_DIV64);
769 static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
772 unsigned long macb_hz = get_macb_pclk_rate(id);
774 if (macb_hz < 20000000)
775 config = GEM_BF(CLK, GEM_CLK_DIV8);
776 else if (macb_hz < 40000000)
777 config = GEM_BF(CLK, GEM_CLK_DIV16);
778 else if (macb_hz < 80000000)
779 config = GEM_BF(CLK, GEM_CLK_DIV32);
780 else if (macb_hz < 120000000)
781 config = GEM_BF(CLK, GEM_CLK_DIV48);
782 else if (macb_hz < 160000000)
783 config = GEM_BF(CLK, GEM_CLK_DIV64);
785 config = GEM_BF(CLK, GEM_CLK_DIV96);
791 * Get the DMA bus width field of the network configuration register that we
792 * should program. We find the width from decoding the design configuration
793 * register to find the maximum supported data bus width.
795 static u32 macb_dbw(struct macb_device *macb)
797 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
799 return GEM_BF(DBW, GEM_DBW128);
801 return GEM_BF(DBW, GEM_DBW64);
804 return GEM_BF(DBW, GEM_DBW32);
808 static void _macb_eth_initialize(struct macb_device *macb)
810 int id = 0; /* This is not used by functions we call */
813 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
814 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
815 &macb->rx_buffer_dma);
816 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
818 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
820 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
821 &macb->dummy_desc_dma);
824 * Do some basic initialization so that we at least can talk
827 if (macb_is_gem(macb)) {
828 ncfgr = gem_mdc_clk_div(id, macb);
829 ncfgr |= macb_dbw(macb);
831 ncfgr = macb_mdc_clk_div(id, macb);
834 macb_writel(macb, NCFGR, ncfgr);
837 #ifndef CONFIG_DM_ETH
838 static int macb_send(struct eth_device *netdev, void *packet, int length)
840 struct macb_device *macb = to_macb(netdev);
842 return _macb_send(macb, netdev->name, packet, length);
845 static int macb_recv(struct eth_device *netdev)
847 struct macb_device *macb = to_macb(netdev);
851 macb->wrapped = false;
853 macb->next_rx_tail = macb->rx_tail;
854 length = _macb_recv(macb, &packet);
856 net_process_received_packet(packet, length);
857 reclaim_rx_buffers(macb, macb->next_rx_tail);
858 } else if (length < 0) {
864 static int macb_init(struct eth_device *netdev, bd_t *bd)
866 struct macb_device *macb = to_macb(netdev);
868 return _macb_init(macb, netdev->name);
871 static void macb_halt(struct eth_device *netdev)
873 struct macb_device *macb = to_macb(netdev);
875 return _macb_halt(macb);
878 static int macb_write_hwaddr(struct eth_device *netdev)
880 struct macb_device *macb = to_macb(netdev);
882 return _macb_write_hwaddr(macb, netdev->enetaddr);
885 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
887 struct macb_device *macb;
888 struct eth_device *netdev;
890 macb = malloc(sizeof(struct macb_device));
892 printf("Error: Failed to allocate memory for MACB%d\n", id);
895 memset(macb, 0, sizeof(struct macb_device));
897 netdev = &macb->netdev;
900 macb->phy_addr = phy_addr;
902 if (macb_is_gem(macb))
903 sprintf(netdev->name, "gmac%d", id);
905 sprintf(netdev->name, "macb%d", id);
907 netdev->init = macb_init;
908 netdev->halt = macb_halt;
909 netdev->send = macb_send;
910 netdev->recv = macb_recv;
911 netdev->write_hwaddr = macb_write_hwaddr;
913 _macb_eth_initialize(macb);
915 eth_register(netdev);
917 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
919 struct mii_dev *mdiodev = mdio_alloc();
922 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
923 mdiodev->read = macb_miiphy_read;
924 mdiodev->write = macb_miiphy_write;
926 retval = mdio_register(mdiodev);
929 macb->bus = miiphy_get_dev_by_name(netdev->name);
933 #endif /* !CONFIG_DM_ETH */
937 static int macb_start(struct udevice *dev)
939 return _macb_init(dev, dev->name);
942 static int macb_send(struct udevice *dev, void *packet, int length)
944 struct macb_device *macb = dev_get_priv(dev);
946 return _macb_send(macb, dev->name, packet, length);
949 static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
951 struct macb_device *macb = dev_get_priv(dev);
953 macb->next_rx_tail = macb->rx_tail;
954 macb->wrapped = false;
956 return _macb_recv(macb, packetp);
959 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
961 struct macb_device *macb = dev_get_priv(dev);
963 reclaim_rx_buffers(macb, macb->next_rx_tail);
968 static void macb_stop(struct udevice *dev)
970 struct macb_device *macb = dev_get_priv(dev);
975 static int macb_write_hwaddr(struct udevice *dev)
977 struct eth_pdata *plat = dev_get_platdata(dev);
978 struct macb_device *macb = dev_get_priv(dev);
980 return _macb_write_hwaddr(macb, plat->enetaddr);
983 static const struct eth_ops macb_eth_ops = {
988 .free_pkt = macb_free_pkt,
989 .write_hwaddr = macb_write_hwaddr,
992 static int macb_eth_probe(struct udevice *dev)
994 struct eth_pdata *pdata = dev_get_platdata(dev);
995 struct macb_device *macb = dev_get_priv(dev);
998 const char *phy_mode;
1000 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
1002 macb->phy_interface = phy_get_interface_by_name(phy_mode);
1003 if (macb->phy_interface == -1) {
1004 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1009 macb->regs = (void *)pdata->iobase;
1011 _macb_eth_initialize(macb);
1012 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1014 struct mii_dev *mdiodev = mdio_alloc();
1017 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
1018 mdiodev->read = macb_miiphy_read;
1019 mdiodev->write = macb_miiphy_write;
1021 retval = mdio_register(mdiodev);
1024 macb->bus = miiphy_get_dev_by_name(dev->name);
1030 static int macb_eth_ofdata_to_platdata(struct udevice *dev)
1032 struct eth_pdata *pdata = dev_get_platdata(dev);
1034 pdata->iobase = dev_get_addr(dev);
1038 static const struct udevice_id macb_eth_ids[] = {
1039 { .compatible = "cdns,macb" },
1043 U_BOOT_DRIVER(eth_macb) = {
1046 .of_match = macb_eth_ids,
1047 .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
1048 .probe = macb_eth_probe,
1049 .ops = &macb_eth_ops,
1050 .priv_auto_alloc_size = sizeof(struct macb_device),
1051 .platdata_auto_alloc_size = sizeof(struct eth_pdata),