2 * Copyright (C) 2005-2006 Atmel Corporation
4 * SPDX-License-Identifier: GPL-2.0+
11 * The u-boot networking stack is a little weird. It seems like the
12 * networking core allocates receive buffers up front without any
13 * regard to the hardware that's supposed to actually receive those
16 * The MACB receives packets into 128-byte receive buffers, so the
17 * buffers allocated by the core isn't very practical to use. We'll
18 * allocate our own, but we need one such buffer in case a packet
19 * wraps around the DMA ring so that we have to copy it.
21 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
22 * configuration header. This way, the core allocates one RX buffer
23 * and one TX buffer, each of which can hold a ethernet packet of
26 * For some reason, the networking core unconditionally specifies a
27 * 32-byte packet "alignment" (which really should be called
28 * "padding"). MACB shouldn't need that, but we'll refrain from any
29 * core modifications here...
39 #include <linux/mii.h>
41 #include <asm/dma-mapping.h>
42 #include <asm/arch/clk.h>
43 #include <linux/errno.h>
47 DECLARE_GLOBAL_DATA_PTR;
49 #define MACB_RX_BUFFER_SIZE 4096
50 #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
51 #define MACB_TX_RING_SIZE 16
52 #define MACB_TX_TIMEOUT 1000
53 #define MACB_AUTONEG_TIMEOUT 5000000
55 struct macb_dma_desc {
60 #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
61 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
62 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
63 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
65 #define RXADDR_USED 0x00000001
66 #define RXADDR_WRAP 0x00000002
68 #define RXBUF_FRMLEN_MASK 0x00000fff
69 #define RXBUF_FRAME_START 0x00004000
70 #define RXBUF_FRAME_END 0x00008000
71 #define RXBUF_TYPEID_MATCH 0x00400000
72 #define RXBUF_ADDR4_MATCH 0x00800000
73 #define RXBUF_ADDR3_MATCH 0x01000000
74 #define RXBUF_ADDR2_MATCH 0x02000000
75 #define RXBUF_ADDR1_MATCH 0x04000000
76 #define RXBUF_BROADCAST 0x80000000
78 #define TXBUF_FRMLEN_MASK 0x000007ff
79 #define TXBUF_FRAME_END 0x00008000
80 #define TXBUF_NOCRC 0x00010000
81 #define TXBUF_EXHAUSTED 0x08000000
82 #define TXBUF_UNDERRUN 0x10000000
83 #define TXBUF_MAXRETRY 0x20000000
84 #define TXBUF_WRAP 0x40000000
85 #define TXBUF_USED 0x80000000
93 unsigned int next_rx_tail;
98 struct macb_dma_desc *rx_ring;
99 struct macb_dma_desc *tx_ring;
101 unsigned long rx_buffer_dma;
102 unsigned long rx_ring_dma;
103 unsigned long tx_ring_dma;
105 struct macb_dma_desc *dummy_desc;
106 unsigned long dummy_desc_dma;
108 const struct device *dev;
109 #ifndef CONFIG_DM_ETH
110 struct eth_device netdev;
112 unsigned short phy_addr;
116 unsigned long pclk_rate;
117 phy_interface_t phy_interface;
120 #ifndef CONFIG_DM_ETH
121 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
124 static int macb_is_gem(struct macb_device *macb)
126 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
129 #ifndef cpu_is_sama5d2
130 #define cpu_is_sama5d2() 0
133 #ifndef cpu_is_sama5d4
134 #define cpu_is_sama5d4() 0
137 static int gem_is_gigabit_capable(struct macb_device *macb)
140 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
141 * configured to support only 10/100.
143 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
146 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
148 unsigned long netctl;
149 unsigned long netstat;
152 netctl = macb_readl(macb, NCR);
153 netctl |= MACB_BIT(MPE);
154 macb_writel(macb, NCR, netctl);
156 frame = (MACB_BF(SOF, 1)
158 | MACB_BF(PHYA, macb->phy_addr)
161 | MACB_BF(DATA, value));
162 macb_writel(macb, MAN, frame);
165 netstat = macb_readl(macb, NSR);
166 } while (!(netstat & MACB_BIT(IDLE)));
168 netctl = macb_readl(macb, NCR);
169 netctl &= ~MACB_BIT(MPE);
170 macb_writel(macb, NCR, netctl);
173 static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
175 unsigned long netctl;
176 unsigned long netstat;
179 netctl = macb_readl(macb, NCR);
180 netctl |= MACB_BIT(MPE);
181 macb_writel(macb, NCR, netctl);
183 frame = (MACB_BF(SOF, 1)
185 | MACB_BF(PHYA, macb->phy_addr)
188 macb_writel(macb, MAN, frame);
191 netstat = macb_readl(macb, NSR);
192 } while (!(netstat & MACB_BIT(IDLE)));
194 frame = macb_readl(macb, MAN);
196 netctl = macb_readl(macb, NCR);
197 netctl &= ~MACB_BIT(MPE);
198 macb_writel(macb, NCR, netctl);
200 return MACB_BFEXT(DATA, frame);
203 void __weak arch_get_mdio_control(const char *name)
208 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
210 int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
214 struct udevice *dev = eth_get_dev_by_name(bus->name);
215 struct macb_device *macb = dev_get_priv(dev);
217 struct eth_device *dev = eth_get_dev_by_name(bus->name);
218 struct macb_device *macb = to_macb(dev);
221 if (macb->phy_addr != phy_adr)
224 arch_get_mdio_control(bus->name);
225 value = macb_mdio_read(macb, reg);
230 int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
234 struct udevice *dev = eth_get_dev_by_name(bus->name);
235 struct macb_device *macb = dev_get_priv(dev);
237 struct eth_device *dev = eth_get_dev_by_name(bus->name);
238 struct macb_device *macb = to_macb(dev);
241 if (macb->phy_addr != phy_adr)
244 arch_get_mdio_control(bus->name);
245 macb_mdio_write(macb, reg, value);
253 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
256 invalidate_dcache_range(macb->rx_ring_dma,
257 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
260 invalidate_dcache_range(macb->tx_ring_dma,
261 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
265 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
268 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
269 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
271 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
272 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
275 static inline void macb_flush_rx_buffer(struct macb_device *macb)
277 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
278 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
281 static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
283 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
284 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
287 #if defined(CONFIG_CMD_NET)
289 static int _macb_send(struct macb_device *macb, const char *name, void *packet,
292 unsigned long paddr, ctrl;
293 unsigned int tx_head = macb->tx_head;
296 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
298 ctrl = length & TXBUF_FRMLEN_MASK;
299 ctrl |= TXBUF_FRAME_END;
300 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
307 macb->tx_ring[tx_head].ctrl = ctrl;
308 macb->tx_ring[tx_head].addr = paddr;
310 macb_flush_ring_desc(macb, TX);
311 /* Do we need check paddr and length is dcache line aligned? */
312 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
313 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
316 * I guess this is necessary because the networking core may
317 * re-use the transmit buffer as soon as we return...
319 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
321 macb_invalidate_ring_desc(macb, TX);
322 ctrl = macb->tx_ring[tx_head].ctrl;
323 if (ctrl & TXBUF_USED)
328 dma_unmap_single(packet, length, paddr);
330 if (i <= MACB_TX_TIMEOUT) {
331 if (ctrl & TXBUF_UNDERRUN)
332 printf("%s: TX underrun\n", name);
333 if (ctrl & TXBUF_EXHAUSTED)
334 printf("%s: TX buffers exhausted in mid frame\n", name);
336 printf("%s: TX timeout\n", name);
339 /* No one cares anyway */
343 static void reclaim_rx_buffers(struct macb_device *macb,
344 unsigned int new_tail)
350 macb_invalidate_ring_desc(macb, RX);
351 while (i > new_tail) {
352 macb->rx_ring[i].addr &= ~RXADDR_USED;
354 if (i > MACB_RX_RING_SIZE)
358 while (i < new_tail) {
359 macb->rx_ring[i].addr &= ~RXADDR_USED;
364 macb_flush_ring_desc(macb, RX);
365 macb->rx_tail = new_tail;
368 static int _macb_recv(struct macb_device *macb, uchar **packetp)
370 unsigned int next_rx_tail = macb->next_rx_tail;
375 macb->wrapped = false;
377 macb_invalidate_ring_desc(macb, RX);
379 if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED))
382 status = macb->rx_ring[next_rx_tail].ctrl;
383 if (status & RXBUF_FRAME_START) {
384 if (next_rx_tail != macb->rx_tail)
385 reclaim_rx_buffers(macb, next_rx_tail);
386 macb->wrapped = false;
389 if (status & RXBUF_FRAME_END) {
390 buffer = macb->rx_buffer + 128 * macb->rx_tail;
391 length = status & RXBUF_FRMLEN_MASK;
393 macb_invalidate_rx_buffer(macb);
395 unsigned int headlen, taillen;
397 headlen = 128 * (MACB_RX_RING_SIZE
399 taillen = length - headlen;
400 memcpy((void *)net_rx_packets[0],
402 memcpy((void *)net_rx_packets[0] + headlen,
403 macb->rx_buffer, taillen);
404 *packetp = (void *)net_rx_packets[0];
409 if (++next_rx_tail >= MACB_RX_RING_SIZE)
411 macb->next_rx_tail = next_rx_tail;
414 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
415 macb->wrapped = true;
423 static void macb_phy_reset(struct macb_device *macb, const char *name)
428 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
429 macb_mdio_write(macb, MII_ADVERTISE, adv);
430 printf("%s: Starting autonegotiation...\n", name);
431 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
434 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
435 status = macb_mdio_read(macb, MII_BMSR);
436 if (status & BMSR_ANEGCOMPLETE)
441 if (status & BMSR_ANEGCOMPLETE)
442 printf("%s: Autonegotiation complete\n", name);
444 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
448 #ifdef CONFIG_MACB_SEARCH_PHY
449 static int macb_phy_find(struct macb_device *macb, const char *name)
454 /* Search for PHY... */
455 for (i = 0; i < 32; i++) {
457 phy_id = macb_mdio_read(macb, MII_PHYSID1);
458 if (phy_id != 0xffff) {
459 printf("%s: PHY present at %d\n", name, i);
464 /* PHY isn't up to snuff */
465 printf("%s: PHY not found\n", name);
469 #endif /* CONFIG_MACB_SEARCH_PHY */
472 static int macb_phy_init(struct udevice *dev, const char *name)
474 static int macb_phy_init(struct macb_device *macb, const char *name)
478 struct macb_device *macb = dev_get_priv(dev);
481 struct phy_device *phydev;
484 u16 phy_id, status, adv, lpa;
485 int media, speed, duplex;
488 arch_get_mdio_control(name);
489 #ifdef CONFIG_MACB_SEARCH_PHY
490 /* Auto-detect phy_addr */
491 if (!macb_phy_find(macb, name))
493 #endif /* CONFIG_MACB_SEARCH_PHY */
495 /* Check if the PHY is up to snuff... */
496 phy_id = macb_mdio_read(macb, MII_PHYSID1);
497 if (phy_id == 0xffff) {
498 printf("%s: No PHY present\n", name);
504 phydev = phy_connect(macb->bus, macb->phy_addr, dev,
505 macb->phy_interface);
507 /* need to consider other phy interface mode */
508 phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
509 PHY_INTERFACE_MODE_RGMII);
512 printf("phy_connect failed\n");
519 status = macb_mdio_read(macb, MII_BMSR);
520 if (!(status & BMSR_LSTATUS)) {
521 /* Try to re-negotiate if we don't have link already. */
522 macb_phy_reset(macb, name);
524 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
525 status = macb_mdio_read(macb, MII_BMSR);
526 if (status & BMSR_LSTATUS)
532 if (!(status & BMSR_LSTATUS)) {
533 printf("%s: link down (status: 0x%04x)\n",
538 /* First check for GMAC and that it is GiB capable */
539 if (gem_is_gigabit_capable(macb)) {
540 lpa = macb_mdio_read(macb, MII_STAT1000);
542 if (lpa & (LPA_1000FULL | LPA_1000HALF)) {
543 duplex = ((lpa & LPA_1000FULL) ? 1 : 0);
545 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
547 duplex ? "full" : "half",
550 ncfgr = macb_readl(macb, NCFGR);
551 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
552 ncfgr |= GEM_BIT(GBE);
555 ncfgr |= MACB_BIT(FD);
557 macb_writel(macb, NCFGR, ncfgr);
563 /* fall back for EMAC checking */
564 adv = macb_mdio_read(macb, MII_ADVERTISE);
565 lpa = macb_mdio_read(macb, MII_LPA);
566 media = mii_nway_result(lpa & adv);
567 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
569 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
570 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
572 speed ? "100" : "10",
573 duplex ? "full" : "half",
576 ncfgr = macb_readl(macb, NCFGR);
577 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
579 ncfgr |= MACB_BIT(SPD);
581 ncfgr |= MACB_BIT(FD);
582 macb_writel(macb, NCFGR, ncfgr);
587 static int gmac_init_multi_queues(struct macb_device *macb)
589 int i, num_queues = 1;
592 /* bit 0 is never set but queue 0 always exists */
593 queue_mask = gem_readl(macb, DCFG6) & 0xff;
596 for (i = 1; i < MACB_MAX_QUEUES; i++)
597 if (queue_mask & (1 << i))
600 macb->dummy_desc->ctrl = TXBUF_USED;
601 macb->dummy_desc->addr = 0;
602 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
603 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
605 for (i = 1; i < num_queues; i++)
606 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
612 static int _macb_init(struct udevice *dev, const char *name)
614 static int _macb_init(struct macb_device *macb, const char *name)
618 struct macb_device *macb = dev_get_priv(dev);
624 * macb_halt should have been called at some point before now,
625 * so we'll assume the controller is idle.
628 /* initialize DMA descriptors */
629 paddr = macb->rx_buffer_dma;
630 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
631 if (i == (MACB_RX_RING_SIZE - 1))
632 paddr |= RXADDR_WRAP;
633 macb->rx_ring[i].addr = paddr;
634 macb->rx_ring[i].ctrl = 0;
637 macb_flush_ring_desc(macb, RX);
638 macb_flush_rx_buffer(macb);
640 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
641 macb->tx_ring[i].addr = 0;
642 if (i == (MACB_TX_RING_SIZE - 1))
643 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
645 macb->tx_ring[i].ctrl = TXBUF_USED;
647 macb_flush_ring_desc(macb, TX);
652 macb->next_rx_tail = 0;
654 macb_writel(macb, RBQP, macb->rx_ring_dma);
655 macb_writel(macb, TBQP, macb->tx_ring_dma);
657 if (macb_is_gem(macb)) {
658 /* Check the multi queue and initialize the queue for tx */
659 gmac_init_multi_queues(macb);
662 * When the GMAC IP with GE feature, this bit is used to
663 * select interface between RGMII and GMII.
664 * When the GMAC IP without GE feature, this bit is used
665 * to select interface between RMII and MII.
668 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
669 gem_writel(macb, UR, GEM_BIT(RGMII));
671 gem_writel(macb, UR, 0);
673 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
674 gem_writel(macb, UR, GEM_BIT(RGMII));
676 gem_writel(macb, UR, 0);
680 /* choose RMII or MII mode. This depends on the board */
682 #ifdef CONFIG_AT91FAMILY
683 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
684 macb_writel(macb, USRIO,
685 MACB_BIT(RMII) | MACB_BIT(CLKEN));
687 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
690 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
691 macb_writel(macb, USRIO, 0);
693 macb_writel(macb, USRIO, MACB_BIT(MII));
697 #ifdef CONFIG_AT91FAMILY
698 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
700 macb_writel(macb, USRIO, 0);
703 #ifdef CONFIG_AT91FAMILY
704 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
706 macb_writel(macb, USRIO, MACB_BIT(MII));
708 #endif /* CONFIG_RMII */
713 if (!macb_phy_init(dev, name))
715 if (!macb_phy_init(macb, name))
719 /* Enable TX and RX */
720 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
725 static void _macb_halt(struct macb_device *macb)
729 /* Halt the controller and wait for any ongoing transmission to end. */
730 ncr = macb_readl(macb, NCR);
731 ncr |= MACB_BIT(THALT);
732 macb_writel(macb, NCR, ncr);
735 tsr = macb_readl(macb, TSR);
736 } while (tsr & MACB_BIT(TGO));
738 /* Disable TX and RX, and clear statistics */
739 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
742 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
747 /* set hardware address */
748 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
749 enetaddr[2] << 16 | enetaddr[3] << 24;
750 macb_writel(macb, SA1B, hwaddr_bottom);
751 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
752 macb_writel(macb, SA1T, hwaddr_top);
756 static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
760 unsigned long macb_hz = macb->pclk_rate;
762 unsigned long macb_hz = get_macb_pclk_rate(id);
765 if (macb_hz < 20000000)
766 config = MACB_BF(CLK, MACB_CLK_DIV8);
767 else if (macb_hz < 40000000)
768 config = MACB_BF(CLK, MACB_CLK_DIV16);
769 else if (macb_hz < 80000000)
770 config = MACB_BF(CLK, MACB_CLK_DIV32);
772 config = MACB_BF(CLK, MACB_CLK_DIV64);
777 static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
782 unsigned long macb_hz = macb->pclk_rate;
784 unsigned long macb_hz = get_macb_pclk_rate(id);
787 if (macb_hz < 20000000)
788 config = GEM_BF(CLK, GEM_CLK_DIV8);
789 else if (macb_hz < 40000000)
790 config = GEM_BF(CLK, GEM_CLK_DIV16);
791 else if (macb_hz < 80000000)
792 config = GEM_BF(CLK, GEM_CLK_DIV32);
793 else if (macb_hz < 120000000)
794 config = GEM_BF(CLK, GEM_CLK_DIV48);
795 else if (macb_hz < 160000000)
796 config = GEM_BF(CLK, GEM_CLK_DIV64);
798 config = GEM_BF(CLK, GEM_CLK_DIV96);
804 * Get the DMA bus width field of the network configuration register that we
805 * should program. We find the width from decoding the design configuration
806 * register to find the maximum supported data bus width.
808 static u32 macb_dbw(struct macb_device *macb)
810 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
812 return GEM_BF(DBW, GEM_DBW128);
814 return GEM_BF(DBW, GEM_DBW64);
817 return GEM_BF(DBW, GEM_DBW32);
821 static void _macb_eth_initialize(struct macb_device *macb)
823 int id = 0; /* This is not used by functions we call */
826 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
827 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
828 &macb->rx_buffer_dma);
829 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
831 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
833 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
834 &macb->dummy_desc_dma);
837 * Do some basic initialization so that we at least can talk
840 if (macb_is_gem(macb)) {
841 ncfgr = gem_mdc_clk_div(id, macb);
842 ncfgr |= macb_dbw(macb);
844 ncfgr = macb_mdc_clk_div(id, macb);
847 macb_writel(macb, NCFGR, ncfgr);
850 #ifndef CONFIG_DM_ETH
851 static int macb_send(struct eth_device *netdev, void *packet, int length)
853 struct macb_device *macb = to_macb(netdev);
855 return _macb_send(macb, netdev->name, packet, length);
858 static int macb_recv(struct eth_device *netdev)
860 struct macb_device *macb = to_macb(netdev);
864 macb->wrapped = false;
866 macb->next_rx_tail = macb->rx_tail;
867 length = _macb_recv(macb, &packet);
869 net_process_received_packet(packet, length);
870 reclaim_rx_buffers(macb, macb->next_rx_tail);
871 } else if (length < 0) {
877 static int macb_init(struct eth_device *netdev, bd_t *bd)
879 struct macb_device *macb = to_macb(netdev);
881 return _macb_init(macb, netdev->name);
884 static void macb_halt(struct eth_device *netdev)
886 struct macb_device *macb = to_macb(netdev);
888 return _macb_halt(macb);
891 static int macb_write_hwaddr(struct eth_device *netdev)
893 struct macb_device *macb = to_macb(netdev);
895 return _macb_write_hwaddr(macb, netdev->enetaddr);
898 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
900 struct macb_device *macb;
901 struct eth_device *netdev;
903 macb = malloc(sizeof(struct macb_device));
905 printf("Error: Failed to allocate memory for MACB%d\n", id);
908 memset(macb, 0, sizeof(struct macb_device));
910 netdev = &macb->netdev;
913 macb->phy_addr = phy_addr;
915 if (macb_is_gem(macb))
916 sprintf(netdev->name, "gmac%d", id);
918 sprintf(netdev->name, "macb%d", id);
920 netdev->init = macb_init;
921 netdev->halt = macb_halt;
922 netdev->send = macb_send;
923 netdev->recv = macb_recv;
924 netdev->write_hwaddr = macb_write_hwaddr;
926 _macb_eth_initialize(macb);
928 eth_register(netdev);
930 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
932 struct mii_dev *mdiodev = mdio_alloc();
935 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
936 mdiodev->read = macb_miiphy_read;
937 mdiodev->write = macb_miiphy_write;
939 retval = mdio_register(mdiodev);
942 macb->bus = miiphy_get_dev_by_name(netdev->name);
946 #endif /* !CONFIG_DM_ETH */
950 static int macb_start(struct udevice *dev)
952 return _macb_init(dev, dev->name);
955 static int macb_send(struct udevice *dev, void *packet, int length)
957 struct macb_device *macb = dev_get_priv(dev);
959 return _macb_send(macb, dev->name, packet, length);
962 static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
964 struct macb_device *macb = dev_get_priv(dev);
966 macb->next_rx_tail = macb->rx_tail;
967 macb->wrapped = false;
969 return _macb_recv(macb, packetp);
972 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
974 struct macb_device *macb = dev_get_priv(dev);
976 reclaim_rx_buffers(macb, macb->next_rx_tail);
981 static void macb_stop(struct udevice *dev)
983 struct macb_device *macb = dev_get_priv(dev);
988 static int macb_write_hwaddr(struct udevice *dev)
990 struct eth_pdata *plat = dev_get_platdata(dev);
991 struct macb_device *macb = dev_get_priv(dev);
993 return _macb_write_hwaddr(macb, plat->enetaddr);
996 static const struct eth_ops macb_eth_ops = {
1001 .free_pkt = macb_free_pkt,
1002 .write_hwaddr = macb_write_hwaddr,
1005 static int macb_enable_clk(struct udevice *dev)
1007 struct macb_device *macb = dev_get_priv(dev);
1012 ret = clk_get_by_index(dev, 0, &clk);
1016 ret = clk_enable(&clk);
1020 clk_rate = clk_get_rate(&clk);
1024 macb->pclk_rate = clk_rate;
1029 static int macb_eth_probe(struct udevice *dev)
1031 struct eth_pdata *pdata = dev_get_platdata(dev);
1032 struct macb_device *macb = dev_get_priv(dev);
1034 #ifdef CONFIG_DM_ETH
1035 const char *phy_mode;
1038 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
1040 macb->phy_interface = phy_get_interface_by_name(phy_mode);
1041 if (macb->phy_interface == -1) {
1042 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1047 macb->regs = (void *)pdata->iobase;
1049 ret = macb_enable_clk(dev);
1053 _macb_eth_initialize(macb);
1055 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1057 struct mii_dev *mdiodev = mdio_alloc();
1060 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
1061 mdiodev->read = macb_miiphy_read;
1062 mdiodev->write = macb_miiphy_write;
1064 retval = mdio_register(mdiodev);
1067 macb->bus = miiphy_get_dev_by_name(dev->name);
1073 static int macb_eth_ofdata_to_platdata(struct udevice *dev)
1075 struct eth_pdata *pdata = dev_get_platdata(dev);
1077 pdata->iobase = dev_get_addr(dev);
1081 static const struct udevice_id macb_eth_ids[] = {
1082 { .compatible = "cdns,macb" },
1086 U_BOOT_DRIVER(eth_macb) = {
1089 .of_match = macb_eth_ids,
1090 .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
1091 .probe = macb_eth_probe,
1092 .ops = &macb_eth_ops,
1093 .priv_auto_alloc_size = sizeof(struct macb_device),
1094 .platdata_auto_alloc_size = sizeof(struct eth_pdata),