2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <environment.h>
21 #include <asm/immap.h>
26 /* Ethernet Transmit and Receive Buffers */
27 #define DBUF_LENGTH 1520
29 #define PKT_MAXBUF_SIZE 1518
30 #define PKT_MINBUF_SIZE 64
31 #define PKT_MAXBLR_SIZE 1520
32 #define LAST_PKTBUFSRX PKTBUFSRX - 1
33 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
34 #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
36 DECLARE_GLOBAL_DATA_PTR;
38 struct fec_info_s fec_info[] = {
39 #ifdef CONFIG_SYS_FEC0_IOBASE
42 CONFIG_SYS_FEC0_IOBASE, /* io base */
43 CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
44 CONFIG_SYS_FEC0_MIIBASE, /* mii base */
46 0, /* duplex and speed */
54 0, /* initialized flag */
55 (struct fec_info_s *)-1,
58 #ifdef CONFIG_SYS_FEC1_IOBASE
61 CONFIG_SYS_FEC1_IOBASE, /* io base */
62 CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
63 CONFIG_SYS_FEC1_MIIBASE, /* mii base */
65 0, /* duplex and speed */
67 0, /* phy name init */
68 #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
69 (cbd_t *)DBUF_LENGTH, /* RX BD */
77 0, /* initialized flag */
78 (struct fec_info_s *)-1,
83 int fec_recv(struct eth_device *dev);
84 int fec_init(struct eth_device *dev, bd_t * bd);
85 void fec_halt(struct eth_device *dev);
86 void fec_reset(struct eth_device *dev);
88 void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
90 if ((dup_spd >> 16) == FULL) {
91 /* Set maximum frame length */
92 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
94 fecp->tcr = FEC_TCR_FDEN;
96 /* Half duplex mode */
97 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
98 FEC_RCR_MII_MODE | FEC_RCR_DRT;
99 fecp->tcr &= ~FEC_TCR_FDEN;
102 if ((dup_spd & 0xFFFF) == _100BASET) {
103 #ifdef CONFIG_MCF5445x
104 fecp->rcr &= ~0x200; /* disabled 10T base */
109 bd->bi_ethspeed = 100;
111 #ifdef CONFIG_MCF5445x
112 fecp->rcr |= 0x200; /* enabled 10T base */
117 bd->bi_ethspeed = 10;
121 static int fec_send(struct eth_device *dev, void *packet, int length)
123 struct fec_info_s *info = dev->priv;
124 volatile fec_t *fecp = (fec_t *) (info->iobase);
128 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
134 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
135 (j < MCFFEC_TOUT_LOOP)) {
139 if (j >= MCFFEC_TOUT_LOOP) {
140 printf("TX not ready\n");
143 info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
144 info->txbd[info->txIdx].cbd_datlen = length;
145 info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;
147 /* Activate transmit Buffer Descriptor polling */
148 fecp->tdar = 0x01000000; /* Descriptor polling active */
150 #ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
152 * FEC unable to initial transmit data packet.
153 * A nop will ensure the descriptor polling active completed.
154 * CF Internal RAM has shorter cycle access than DRAM. If use
155 * DRAM as Buffer descriptor and data, a nop is a must.
156 * Affect only V2 and V3.
162 #ifdef CONFIG_SYS_UNIFY_CACHE
167 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
168 (j < MCFFEC_TOUT_LOOP)) {
172 if (j >= MCFFEC_TOUT_LOOP) {
173 printf("TX timeout\n");
177 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
178 __FILE__, __LINE__, __FUNCTION__, j,
179 info->txbd[info->txIdx].cbd_sc,
180 (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
183 /* return only status bits */
184 rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
185 info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
190 int fec_recv(struct eth_device *dev)
192 struct fec_info_s *info = dev->priv;
193 volatile fec_t *fecp = (fec_t *) (info->iobase);
197 #ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
199 #ifdef CONFIG_SYS_UNIFY_CACHE
202 /* section 16.9.23.2 */
203 if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
205 break; /* nothing received - leave for() loop */
208 length = info->rxbd[info->rxIdx].cbd_datlen;
210 if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) {
211 printf("%s[%d] err: %x\n",
212 __FUNCTION__, __LINE__,
213 info->rxbd[info->rxIdx].cbd_sc);
215 printf("%s[%d] err: %x\n",
216 __FUNCTION__, __LINE__,
217 info->rxbd[info->rxIdx].cbd_sc);
222 /* Pass the packet up to the protocol layers. */
223 net_process_received_packet(net_rx_packets[info->rxIdx],
226 fecp->eir |= FEC_EIR_RXF;
229 /* Give the buffer back to the FEC. */
230 info->rxbd[info->rxIdx].cbd_datlen = 0;
232 /* wrap around buffer index when necessary */
233 if (info->rxIdx == LAST_PKTBUFSRX) {
234 info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
237 info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
241 /* Try to fill Buffer Descriptors */
242 fecp->rdar = 0x01000000; /* Descriptor polling active */
249 void dbgFecRegs(struct eth_device *dev)
251 struct fec_info_s *info = dev->priv;
252 volatile fec_t *fecp = (fec_t *) (info->iobase);
255 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
256 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
257 printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar);
258 printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar);
259 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
260 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
261 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
262 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
263 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
264 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
265 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
266 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
267 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
268 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
269 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
270 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
271 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
272 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
273 printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr);
274 printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr);
275 printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
276 printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
277 printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);
280 printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop,
282 printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets,
283 fecp->rmon_t_packets);
284 printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt,
285 fecp->rmon_t_bc_pkt);
286 printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt,
287 fecp->rmon_t_mc_pkt);
288 printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align,
289 fecp->rmon_t_crc_align);
290 printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize,
291 fecp->rmon_t_undersize);
292 printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize,
293 fecp->rmon_t_oversize);
294 printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag,
296 printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab,
298 printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col,
300 printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64,
302 printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127,
303 fecp->rmon_t_p65to127);
304 printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255,
305 fecp->rmon_t_p128to255);
306 printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511,
307 fecp->rmon_t_p256to511);
308 printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023,
309 fecp->rmon_t_p512to1023);
310 printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047,
311 fecp->rmon_t_p1024to2047);
312 printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048,
313 fecp->rmon_t_p_gte2048);
314 printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets,
315 fecp->rmon_t_octets);
318 printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop,
320 printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok,
321 fecp->ieee_t_frame_ok);
322 printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col,
324 printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol,
326 printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def,
328 printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol,
330 printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol,
332 printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr,
333 fecp->ieee_t_macerr);
334 printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr,
336 printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe,
338 printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc,
340 printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok,
341 fecp->ieee_t_octets_ok);
344 printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop,
346 printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets,
347 fecp->rmon_r_packets);
348 printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt,
349 fecp->rmon_r_bc_pkt);
350 printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt,
351 fecp->rmon_r_mc_pkt);
352 printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align,
353 fecp->rmon_r_crc_align);
354 printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize,
355 fecp->rmon_r_undersize);
356 printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize,
357 fecp->rmon_r_oversize);
358 printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag,
360 printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab,
362 printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64,
364 printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127,
365 fecp->rmon_r_p65to127);
366 printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255,
367 fecp->rmon_r_p128to255);
368 printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511,
369 fecp->rmon_r_p256to511);
370 printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023,
371 fecp->rmon_r_p512to1023);
372 printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047,
373 fecp->rmon_r_p1024to2047);
374 printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048,
375 fecp->rmon_r_p_gte2048);
376 printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets,
377 fecp->rmon_r_octets);
380 printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop,
382 printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok,
383 fecp->ieee_r_frame_ok);
384 printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc,
386 printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align,
388 printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr,
389 fecp->ieee_r_macerr);
390 printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc,
392 printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
393 fecp->ieee_r_octets_ok);
399 int fec_init(struct eth_device *dev, bd_t * bd)
401 struct fec_info_s *info = dev->priv;
402 volatile fec_t *fecp = (fec_t *) (info->iobase);
406 fecpin_setclear(dev, 1);
410 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
411 defined (CONFIG_SYS_DISCOVER_PHY)
415 setFecDuplexSpeed(fecp, bd, info->dup_spd);
417 #ifndef CONFIG_SYS_DISCOVER_PHY
418 setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
419 #endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
420 #endif /* CONFIG_CMD_MII || CONFIG_MII */
422 /* We use strictly polling mode only */
425 /* Clear any pending interrupt */
426 fecp->eir = 0xffffffff;
428 /* Set station address */
429 if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) {
430 #ifdef CONFIG_SYS_FEC1_IOBASE
431 volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE);
432 eth_env_get_enetaddr("eth1addr", ea);
434 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
435 fecp1->paur = (ea[4] << 24) | (ea[5] << 16);
437 eth_env_get_enetaddr("ethaddr", ea);
439 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
440 fecp->paur = (ea[4] << 24) | (ea[5] << 16);
442 #ifdef CONFIG_SYS_FEC0_IOBASE
443 volatile fec_t *fecp0 = (fec_t *) (CONFIG_SYS_FEC0_IOBASE);
444 eth_env_get_enetaddr("ethaddr", ea);
446 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
447 fecp0->paur = (ea[4] << 24) | (ea[5] << 16);
449 #ifdef CONFIG_SYS_FEC1_IOBASE
450 eth_env_get_enetaddr("eth1addr", ea);
452 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
453 fecp->paur = (ea[4] << 24) | (ea[5] << 16);
457 /* Clear unicast address hash table */
461 /* Clear multicast address hash table */
465 /* Set maximum receive buffer size. */
466 fecp->emrbr = PKT_MAXBLR_SIZE;
469 * Setup Buffers and Buffer Descriptors
475 * Setup Receiver Buffer Descriptors (13.14.24.18)
479 for (i = 0; i < PKTBUFSRX; i++) {
480 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
481 info->rxbd[i].cbd_datlen = 0; /* Reset */
482 info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
484 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
487 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
491 for (i = 0; i < TX_BUF_CNT; i++) {
492 info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
493 info->txbd[i].cbd_datlen = 0; /* Reset */
494 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
496 info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
498 /* Set receive and transmit descriptor base */
499 fecp->erdsr = (unsigned int)(&info->rxbd[0]);
500 fecp->etdsr = (unsigned int)(&info->txbd[0]);
502 /* Now enable the transmit and receive processing */
503 fecp->ecr |= FEC_ECR_ETHER_EN;
505 /* And last, try to fill Rx Buffer Descriptors */
506 fecp->rdar = 0x01000000; /* Descriptor polling active */
511 void fec_reset(struct eth_device *dev)
513 struct fec_info_s *info = dev->priv;
514 volatile fec_t *fecp = (fec_t *) (info->iobase);
517 fecp->ecr = FEC_ECR_RESET;
518 for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
521 if (i == FEC_RESET_DELAY) {
522 printf("FEC_RESET_DELAY timeout\n");
526 void fec_halt(struct eth_device *dev)
528 struct fec_info_s *info = dev->priv;
532 fecpin_setclear(dev, 0);
534 info->rxIdx = info->txIdx = 0;
535 memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
536 memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
537 memset(info->txbuf, 0, DBUF_LENGTH);
540 int mcffec_initialize(bd_t * bis)
542 struct eth_device *dev;
544 #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
545 u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
548 for (i = 0; i < ARRAY_SIZE(fec_info); i++) {
551 (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
556 memset(dev, 0, sizeof(*dev));
558 sprintf(dev->name, "FEC%d", fec_info[i].index);
560 dev->priv = &fec_info[i];
561 dev->init = fec_init;
562 dev->halt = fec_halt;
563 dev->send = fec_send;
564 dev->recv = fec_recv;
566 /* setup Receive and Transmit buffer descriptor */
567 #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
568 fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
569 tmp = (u32)fec_info[i].rxbd;
571 (cbd_t *)((u32)fec_info[i].txbd + tmp +
572 (PKTBUFSRX * sizeof(cbd_t)));
573 tmp = (u32)fec_info[i].txbd;
575 (char *)((u32)fec_info[i].txbuf + tmp +
576 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
577 tmp = (u32)fec_info[i].txbuf;
580 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
581 (PKTBUFSRX * sizeof(cbd_t)));
583 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
584 (TX_BUF_CNT * sizeof(cbd_t)));
586 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
590 printf("rxbd %x txbd %x\n",
591 (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
594 fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
598 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
600 struct mii_dev *mdiodev = mdio_alloc();
603 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
604 mdiodev->read = mcffec_miiphy_read;
605 mdiodev->write = mcffec_miiphy_write;
607 retval = mdio_register(mdiodev);
612 fec_info[i - 1].next = &fec_info[i];
614 fec_info[i - 1].next = &fec_info[0];
617 bis->bi_ethspeed = 10;