2 * (C) Copyright 2003-2010
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Derived from the MPC8xx FEC driver.
6 * Adapted for MPC512x by Grzegorz Bernacki <gjb@semihalf.com>
15 #include "mpc512x_fec.h"
17 DECLARE_GLOBAL_DATA_PTR;
21 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
22 #error "CONFIG_MII has to be defined!"
25 int fec512x_miiphy_read(struct mii_dev *bus, int phyAddr, int devad,
27 int fec512x_miiphy_write(struct mii_dev *bus, int phyAddr, int devad,
28 int regAddr, u16 data);
29 int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
31 static uchar rx_buff[FEC_BUFFER_SIZE];
32 static int rx_buff_idx = 0;
34 /********************************************************************/
36 static void mpc512x_fec_phydump (char *devname)
39 u8 phyAddr = CONFIG_PHY_ADDR;
41 /* regs to print: 0...8, 21,27,31 */
42 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
43 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1,
46 for (i = 0; i < 32; i++) {
48 miiphy_read (devname, phyAddr, i, &phyStatus);
49 printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
55 /********************************************************************/
56 static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
63 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
64 fec->bdBase->rbd[ix].dataPointer =
65 (u32)&fec->bdBase->recv_frames[ix];
66 fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;
67 fec->bdBase->rbd[ix].dataLength = 0;
71 * have the last RBD to close the ring
73 fec->bdBase->rbd[ix - 1].status |= FEC_RBD_WRAP;
79 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
80 fec->bdBase->tbd[ix].status = 0;
84 * Have the last TBD to close the ring
86 fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
89 * Initialize some indices
92 fec->usedTbdIndex = 0;
93 fec->cleanTbdNum = FEC_TBD_NUM;
98 /********************************************************************/
99 static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRbd)
102 * Reset buffer descriptor as empty
104 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
105 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
107 pRbd->status = FEC_RBD_EMPTY;
109 pRbd->dataLength = 0;
114 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
117 * Now, we have an empty RxBD, notify FEC
118 * Set Descriptor polling active
120 out_be32(&fec->eth->r_des_active, 0x01000000);
123 /********************************************************************/
124 static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec)
126 volatile FEC_TBD *pUsedTbd;
129 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
130 fec->cleanTbdNum, fec->usedTbdIndex);
134 * process all the consumed TBDs
136 while (fec->cleanTbdNum < FEC_TBD_NUM) {
137 pUsedTbd = &fec->bdBase->tbd[fec->usedTbdIndex];
138 if (pUsedTbd->status & FEC_TBD_READY) {
140 printf ("Cannot clean TBD %d, in use\n", fec->usedTbdIndex);
146 * clean this buffer descriptor
148 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
149 pUsedTbd->status = FEC_TBD_WRAP;
151 pUsedTbd->status = 0;
154 * update some indeces for a correct handling of the TBD ring
157 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
161 /********************************************************************/
162 static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, unsigned char *mac)
164 u8 currByte; /* byte for which to compute the CRC */
165 int byte; /* loop - counter */
166 int bit; /* loop - counter */
167 u32 crc = 0xffffffff; /* initial value */
170 * The algorithm used is the following:
171 * we loop on each of the six bytes of the provided address,
172 * and we compute the CRC by left-shifting the previous
173 * value by one position, so that each bit in the current
174 * byte of the address may contribute the calculation. If
175 * the latter and the MSB in the CRC are different, then
176 * the CRC value so computed is also ex-ored with the
177 * "polynomium generator". The current byte of the address
178 * is also shifted right by one bit at each iteration.
179 * This is because the CRC generatore in hardware is implemented
180 * as a shift-register with as many ex-ores as the radixes
181 * in the polynomium. This suggests that we represent the
182 * polynomiumm itself as a 32-bit constant.
184 for (byte = 0; byte < 6; byte++) {
185 currByte = mac[byte];
186 for (bit = 0; bit < 8; bit++) {
187 if ((currByte & 0x01) ^ (crc & 0x01)) {
189 crc = crc ^ 0xedb88320;
200 * Set individual hash table register
203 out_be32(&fec->eth->iaddr1, (1 << (crc - 32)));
204 out_be32(&fec->eth->iaddr2, 0);
206 out_be32(&fec->eth->iaddr1, 0);
207 out_be32(&fec->eth->iaddr2, (1 << crc));
211 * Set physical address
213 out_be32(&fec->eth->paddr1, (mac[0] << 24) + (mac[1] << 16) +
214 (mac[2] << 8) + mac[3]);
215 out_be32(&fec->eth->paddr2, (mac[4] << 24) + (mac[5] << 16) +
219 /********************************************************************/
220 static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
222 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
225 printf ("mpc512x_fec_init... Begin\n");
228 mpc512x_fec_set_hwaddr (fec, dev->enetaddr);
229 out_be32(&fec->eth->gaddr1, 0x00000000);
230 out_be32(&fec->eth->gaddr2, 0x00000000);
232 mpc512x_fec_init_phy (dev, bis);
234 /* Set interrupt mask register */
235 out_be32(&fec->eth->imask, 0x00000000);
237 /* Clear FEC-Lite interrupt event register(IEVENT) */
238 out_be32(&fec->eth->ievent, 0xffffffff);
240 /* Set transmit fifo watermark register(X_WMRK), default = 64 */
241 out_be32(&fec->eth->x_wmrk, 0x0);
243 /* Set Opcode/Pause Duration Register */
244 out_be32(&fec->eth->op_pause, 0x00010020);
246 /* Frame length=1522; MII mode */
247 out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24);
249 /* Half-duplex, heartbeat disabled */
250 out_be32(&fec->eth->x_cntrl, 0x00000000);
252 /* Enable MIB counters */
253 out_be32(&fec->eth->mib_control, 0x0);
255 /* Setup recv fifo start and buff size */
256 out_be32(&fec->eth->r_fstart, 0x500);
257 out_be32(&fec->eth->r_buff_size, FEC_BUFFER_SIZE);
259 /* Setup BD base addresses */
260 out_be32(&fec->eth->r_des_start, (u32)fec->bdBase->rbd);
261 out_be32(&fec->eth->x_des_start, (u32)fec->bdBase->tbd);
264 out_be32(&fec->eth->dma_control, 0xc0000000);
267 setbits_be32(&fec->eth->ecntrl, 0x00000006);
269 /* Initilize addresses and status words of BDs */
270 mpc512x_fec_bd_init (fec);
272 /* Descriptor polling active */
273 out_be32(&fec->eth->r_des_active, 0x01000000);
276 printf("mpc512x_fec_init... Done \n");
281 /********************************************************************/
282 int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
284 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
285 const u8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
290 printf ("mpc512x_fec_init_phy... Begin\n");
294 * Clear FEC-Lite interrupt event register(IEVENT)
296 out_be32(&fec->eth->ievent, 0xffffffff);
299 * Set interrupt mask register
301 out_be32(&fec->eth->imask, 0x00000000);
303 if (fec->xcv_type != SEVENWIRE) {
305 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
306 * and do not drop the Preamble.
308 out_be32(&fec->eth->mii_speed,
309 (((gd->arch.ips_clk / 1000000) / 5) + 1) << 1);
312 * Reset PHY, then delay 300ns
314 miiphy_write (dev->name, phyAddr, 0x0, 0x8000);
317 if (fec->xcv_type == MII10) {
319 * Force 10Base-T, FDX operation
322 printf ("Forcing 10 Mbps ethernet link... ");
324 miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
326 miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
329 do { /* wait for link status to go down */
331 if ((timeout--) == 0) {
333 printf ("hmmm, should not have waited...");
337 miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
341 } while ((phyStatus & 0x0004)); /* !link up */
344 do { /* wait for link status to come back up */
346 if ((timeout--) == 0) {
347 printf ("failed. Link is down.\n");
350 miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
354 } while (!(phyStatus & 0x0004)); /* !link up */
359 } else { /* MII100 */
361 * Set the auto-negotiation advertisement register bits
363 miiphy_write (dev->name, phyAddr, 0x4, 0x01e1);
366 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
368 miiphy_write (dev->name, phyAddr, 0x0, 0x1200);
371 * Wait for AN completion
377 if ((timeout--) == 0) {
379 printf ("PHY auto neg 0 failed...\n");
384 if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != 0) {
386 printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
390 } while (!(phyStatus & 0x0004));
393 printf ("PHY auto neg complete! \n");
399 if (fec->xcv_type != SEVENWIRE)
400 mpc512x_fec_phydump (dev->name);
404 printf ("mpc512x_fec_init_phy... Done \n");
409 /********************************************************************/
410 static void mpc512x_fec_halt (struct eth_device *dev)
412 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
413 int counter = 0xffff;
416 if (fec->xcv_type != SEVENWIRE)
417 mpc512x_fec_phydump (dev->name);
421 * mask FEC chip interrupts
423 out_be32(&fec->eth->imask, 0);
426 * issue graceful stop command to the FEC transmitter if necessary
428 setbits_be32(&fec->eth->x_cntrl, 0x00000001);
431 * wait for graceful stop to register
433 while ((counter--) && (!(in_be32(&fec->eth->ievent) & 0x10000000)))
437 * Disable the Ethernet Controller
439 clrbits_be32(&fec->eth->ecntrl, 0x00000002);
442 * Issue a reset command to the FEC chip
444 setbits_be32(&fec->eth->ecntrl, 0x1);
447 * wait at least 16 clock cycles
451 printf ("Ethernet task stopped\n");
455 /********************************************************************/
457 static int mpc512x_fec_send(struct eth_device *dev, void *eth_data,
461 * This routine transmits one frame. This routine only accepts
462 * 6-byte Ethernet addresses.
464 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
465 volatile FEC_TBD *pTbd;
468 printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status);
472 * Clear Tx BD ring at first
474 mpc512x_fec_tbd_scrub (fec);
477 * Check for valid length of data.
479 if ((data_length > 1500) || (data_length <= 0)) {
484 * Check the number of vacant TxBDs.
486 if (fec->cleanTbdNum < 1) {
488 printf ("No available TxBDs ...\n");
494 * Get the first TxBD to send the mac header
496 pTbd = &fec->bdBase->tbd[fec->tbdIndex];
497 pTbd->dataLength = data_length;
498 pTbd->dataPointer = (u32)eth_data;
499 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
500 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
502 /* Activate transmit Buffer Descriptor polling */
503 out_be32(&fec->eth->x_des_active, 0x01000000);
509 fec->cleanTbdNum -= 1;
512 * wait until frame is sent .
514 while (pTbd->status & FEC_TBD_READY) {
517 printf ("TDB status = %04x\n", pTbd->status);
525 /********************************************************************/
526 static int mpc512x_fec_recv (struct eth_device *dev)
529 * This command pulls one frame from the card
531 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
532 volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex];
533 unsigned long ievent;
534 int frame_length = 0;
537 printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex);
544 * Check if any critical events have happened
546 ievent = in_be32(&fec->eth->ievent);
547 out_be32(&fec->eth->ievent, ievent);
548 if (ievent & 0x20060000) {
549 /* BABT, Rx/Tx FIFO errors */
550 mpc512x_fec_halt (dev);
551 mpc512x_fec_init (dev, NULL);
554 if (ievent & 0x80000000) {
555 /* Heartbeat error */
556 setbits_be32(&fec->eth->x_cntrl, 0x00000001);
558 if (ievent & 0x10000000) {
559 /* Graceful stop complete */
560 if (in_be32(&fec->eth->x_cntrl) & 0x00000001) {
561 mpc512x_fec_halt (dev);
562 clrbits_be32(&fec->eth->x_cntrl, 0x00000001);;
563 mpc512x_fec_init (dev, NULL);
567 if (!(pRbd->status & FEC_RBD_EMPTY)) {
568 if (!(pRbd->status & FEC_RBD_ERR) &&
569 ((pRbd->dataLength - 4) > 14)) {
574 if (pRbd->status & FEC_RBD_LAST)
575 frame_length = pRbd->dataLength - 4;
577 frame_length = pRbd->dataLength;
581 printf ("recv data length 0x%08x data hdr: ",
583 for (i = 0; i < 14; i++)
584 printf ("%x ", *((u8*)pRbd->dataPointer + i));
589 * Fill the buffer and pass it to upper layers
591 memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer,
592 frame_length - rx_buff_idx);
593 rx_buff_idx = frame_length;
595 if (pRbd->status & FEC_RBD_LAST) {
596 net_process_received_packet((uchar *)rx_buff,
603 * Reset buffer descriptor as empty
605 mpc512x_fec_rbd_clean (fec, pRbd);
608 /* Try to fill Buffer Descriptors */
609 out_be32(&fec->eth->r_des_active, 0x01000000);
614 /********************************************************************/
615 int mpc512x_fec_initialize (bd_t * bis)
617 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
618 mpc512x_fec_priv *fec;
619 struct eth_device *dev;
622 fec = (mpc512x_fec_priv *) malloc (sizeof(*fec));
623 dev = (struct eth_device *) malloc (sizeof(*dev));
624 memset (dev, 0, sizeof *dev);
628 # ifndef CONFIG_FEC_10MBIT
629 fec->xcv_type = MII100;
631 fec->xcv_type = MII10;
633 dev->priv = (void *)fec;
634 dev->iobase = (int)&im->fec;
635 dev->init = mpc512x_fec_init;
636 dev->halt = mpc512x_fec_halt;
637 dev->send = mpc512x_fec_send;
638 dev->recv = mpc512x_fec_recv;
640 strcpy(dev->name, "FEC");
643 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
645 struct mii_dev *mdiodev = mdio_alloc();
648 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
649 mdiodev->read = fec512x_miiphy_read;
650 mdiodev->write = fec512x_miiphy_write;
652 retval = mdio_register(mdiodev);
657 /* Clean up space FEC's MIB and FIFO RAM ...*/
658 memset ((void *)&im->fec.mib, 0x00, sizeof(im->fec.mib));
659 memset ((void *)&im->fec.fifo, 0x00, sizeof(im->fec.fifo));
662 * Malloc space for BDs (must be quad word-aligned)
663 * this pointer is lost, so cannot be freed
665 bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
666 fec->bdBase = (mpc512x_buff_descs*)((u32)bd & 0xfffffff0);
667 memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
670 * Set interrupt mask register
672 out_be32(&fec->eth->imask, 0x00000000);
675 * Clear FEC-Lite interrupt event register(IEVENT)
677 out_be32(&fec->eth->ievent, 0xffffffff);
682 /* MII-interface related functions */
683 /********************************************************************/
684 int fec512x_miiphy_read(struct mii_dev *bus, int phyAddr, int devad,
688 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
689 volatile fec512x_t *eth = &im->fec;
690 u32 reg; /* convenient holder for the PHY register */
691 u32 phy; /* convenient holder for the PHY */
692 int timeout = 0xffff;
695 * reading from any PHY's register is done by properly
696 * programming the FEC's MII data register.
698 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
699 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
701 out_be32(ð->mii_data, FEC_MII_DATA_ST |
707 * wait for the related interrupt
709 while ((timeout--) && (!(in_be32(ð->ievent) & 0x00800000)))
714 printf ("Read MDIO failed...\n");
720 * clear mii interrupt bit
722 out_be32(ð->ievent, 0x00800000);
725 * it's now safe to read the PHY's register
727 retVal = (u16) in_be32(ð->mii_data);
732 /********************************************************************/
733 int fec512x_miiphy_write(struct mii_dev *bus, int phyAddr, int devad,
734 int regAddr, u16 data)
736 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
737 volatile fec512x_t *eth = &im->fec;
738 u32 reg; /* convenient holder for the PHY register */
739 u32 phy; /* convenient holder for the PHY */
740 int timeout = 0xffff;
742 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
743 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
745 out_be32(ð->mii_data, FEC_MII_DATA_ST |
751 * wait for the MII interrupt
753 while ((timeout--) && (!(in_be32(ð->ievent) & 0x00800000)))
758 printf ("Write MDIO failed...\n");
764 * clear MII interrupt bit
766 out_be32(ð->ievent, 0x00800000);