3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
18 DECLARE_GLOBAL_DATA_PTR;
20 /* define WANT_MII when MII support is required */
21 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
30 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
31 #error "CONFIG_MII has to be defined!"
36 #if defined(CONFIG_RMII) && !defined(WANT_MII)
37 #error RMII support is unusable without a working PHY.
40 #ifdef CONFIG_SYS_DISCOVER_PHY
41 static int mii_discover_phy(struct eth_device *dev);
44 int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
45 int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
48 static struct ether_fcc_info_s
57 #if defined(CONFIG_ETHER_ON_FEC1)
60 offsetof(immap_t, im_cpm.cp_fec1),
67 #if defined(CONFIG_ETHER_ON_FEC2)
70 offsetof(immap_t, im_cpm.cp_fec2),
78 /* Ethernet Transmit and Receive Buffers */
79 #define DBUF_LENGTH 1520
85 #define PKT_MAXBUF_SIZE 1518
86 #define PKT_MINBUF_SIZE 64
87 #define PKT_MAXBLR_SIZE 1520
90 static char txbuf[DBUF_LENGTH] __aligned(8);
92 #error txbuf must be aligned.
95 static uint rxIdx; /* index of the current RX buffer */
96 static uint txIdx; /* index of the current TX buffer */
99 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
100 * immr->udata_bd address on Dual-Port RAM
101 * Provide for Double Buffering
104 struct common_buf_desc {
105 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
106 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
109 static struct common_buf_desc __iomem *rtx;
111 static int fec_send(struct eth_device *dev, void *packet, int length);
112 static int fec_recv(struct eth_device *dev);
113 static int fec_init(struct eth_device *dev, bd_t *bd);
114 static void fec_halt(struct eth_device *dev);
115 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
116 static void __mii_init(void);
119 int fec_initialize(bd_t *bis)
121 struct eth_device *dev;
122 struct ether_fcc_info_s *efis;
125 for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
126 dev = malloc(sizeof(*dev));
130 memset(dev, 0, sizeof(*dev));
132 /* for FEC1 make sure that the name of the interface is the same
133 as the old one for compatibility reasons */
135 strcpy(dev->name, "FEC");
137 sprintf(dev->name, "FEC%d",
138 ether_fcc_info[i].ether_index + 1);
140 efis = ðer_fcc_info[i];
143 * reset actual phy addr
145 efis->actual_phy_addr = -1;
148 dev->init = fec_init;
149 dev->halt = fec_halt;
150 dev->send = fec_send;
151 dev->recv = fec_recv;
155 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
157 struct mii_dev *mdiodev = mdio_alloc();
160 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
161 mdiodev->read = fec8xx_miiphy_read;
162 mdiodev->write = fec8xx_miiphy_write;
164 retval = mdio_register(mdiodev);
172 static int fec_send(struct eth_device *dev, void *packet, int length)
175 struct ether_fcc_info_s *efis = dev->priv;
176 fec_t __iomem *fecp =
177 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
183 while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
189 printf("TX not ready\n");
191 out_be32(&rtx->txbd[txIdx].cbd_bufaddr, (uint)packet);
192 out_be16(&rtx->txbd[txIdx].cbd_datlen, length);
193 setbits_be16(&rtx->txbd[txIdx].cbd_sc,
194 BD_ENET_TX_READY | BD_ENET_TX_LAST);
196 /* Activate transmit Buffer Descriptor polling */
197 /* Descriptor polling active */
198 out_be32(&fecp->fec_x_des_active, 0x01000000);
201 while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
207 printf("TX timeout\n");
209 /* return only status bits */;
210 rc = in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_STATS;
212 txIdx = (txIdx + 1) % TX_BUF_CNT;
217 static int fec_recv(struct eth_device *dev)
219 struct ether_fcc_info_s *efis = dev->priv;
220 fec_t __iomem *fecp =
221 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
225 /* section 16.9.23.2 */
226 if (in_be16(&rtx->rxbd[rxIdx].cbd_sc) & BD_ENET_RX_EMPTY) {
228 break; /* nothing received - leave for() loop */
231 length = in_be16(&rtx->rxbd[rxIdx].cbd_datlen);
233 if (!(in_be16(&rtx->rxbd[rxIdx].cbd_sc) & 0x003f)) {
234 uchar *rx = net_rx_packets[rxIdx];
238 #if defined(CONFIG_CMD_CDP)
239 if ((rx[0] & 1) != 0 &&
240 memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 &&
241 !is_cdp_packet((uchar *)rx))
245 * Pass the packet up to the protocol layers.
248 net_process_received_packet(rx, length);
251 /* Give the buffer back to the FEC. */
252 out_be16(&rtx->rxbd[rxIdx].cbd_datlen, 0);
254 /* wrap around buffer index when necessary */
255 if ((rxIdx + 1) >= PKTBUFSRX) {
256 out_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc,
257 BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
260 out_be16(&rtx->rxbd[rxIdx].cbd_sc, BD_ENET_RX_EMPTY);
264 /* Try to fill Buffer Descriptors */
265 /* Descriptor polling active */
266 out_be32(&fecp->fec_r_des_active, 0x01000000);
272 /**************************************************************
274 * FEC Ethernet Initialization Routine
276 *************************************************************/
278 #define FEC_ECNTRL_PINMUX 0x00000004
279 #define FEC_ECNTRL_ETHER_EN 0x00000002
280 #define FEC_ECNTRL_RESET 0x00000001
282 #define FEC_RCNTRL_BC_REJ 0x00000010
283 #define FEC_RCNTRL_PROM 0x00000008
284 #define FEC_RCNTRL_MII_MODE 0x00000004
285 #define FEC_RCNTRL_DRT 0x00000002
286 #define FEC_RCNTRL_LOOP 0x00000001
288 #define FEC_TCNTRL_FDEN 0x00000004
289 #define FEC_TCNTRL_HBC 0x00000002
290 #define FEC_TCNTRL_GTS 0x00000001
292 #define FEC_RESET_DELAY 50
294 #if defined(CONFIG_RMII)
296 static inline void fec_10Mbps(struct eth_device *dev)
298 struct ether_fcc_info_s *efis = dev->priv;
299 int fecidx = efis->ether_index;
300 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
301 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
303 if ((unsigned int)fecidx >= 2)
306 setbits_be32(&immr->im_cpm.cp_cptr, mask);
309 static inline void fec_100Mbps(struct eth_device *dev)
311 struct ether_fcc_info_s *efis = dev->priv;
312 int fecidx = efis->ether_index;
313 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
314 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
316 if ((unsigned int)fecidx >= 2)
319 clrbits_be32(&immr->im_cpm.cp_cptr, mask);
324 static inline void fec_full_duplex(struct eth_device *dev)
326 struct ether_fcc_info_s *efis = dev->priv;
327 fec_t __iomem *fecp =
328 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
330 clrbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
331 setbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
334 static inline void fec_half_duplex(struct eth_device *dev)
336 struct ether_fcc_info_s *efis = dev->priv;
337 fec_t __iomem *fecp =
338 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
340 setbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
341 clrbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
344 static void fec_pin_init(int fecidx)
347 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
350 * Set MII speed to 2.5 MHz or slightly below.
352 * According to the MPC860T (Rev. D) Fast ethernet controller user
354 * the MII management interface clock must be less than or equal
356 * This MDC frequency is equal to system clock / (2 * MII_SPEED).
357 * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
359 * All MII configuration is done via FEC1 registers:
361 out_be32(&immr->im_cpm.cp_fec1.fec_mii_speed,
362 ((bd->bi_intfreq + 4999999) / 5000000) << 1);
364 #if defined(CONFIG_MPC885) && defined(WANT_MII)
365 /* use MDC for MII */
366 setbits_be16(&immr->im_ioport.iop_pdpar, 0x0080);
367 clrbits_be16(&immr->im_ioport.iop_pddir, 0x0080);
371 #if defined(CONFIG_ETHER_ON_FEC1)
373 #if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
375 #if !defined(CONFIG_RMII)
377 setbits_be16(&immr->im_ioport.iop_papar, 0xf830);
378 setbits_be16(&immr->im_ioport.iop_padir, 0x0830);
379 clrbits_be16(&immr->im_ioport.iop_padir, 0xf000);
381 setbits_be32(&immr->im_cpm.cp_pbpar, 0x00001001);
382 clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00001001);
384 setbits_be16(&immr->im_ioport.iop_pcpar, 0x000c);
385 clrbits_be16(&immr->im_ioport.iop_pcdir, 0x000c);
387 setbits_be32(&immr->im_cpm.cp_pepar, 0x00000003);
388 setbits_be32(&immr->im_cpm.cp_pedir, 0x00000003);
389 clrbits_be32(&immr->im_cpm.cp_peso, 0x00000003);
391 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
395 #if !defined(CONFIG_FEC1_PHY_NORXERR)
396 setbits_be16(&immr->im_ioport.iop_papar, 0x1000);
397 clrbits_be16(&immr->im_ioport.iop_padir, 0x1000);
399 setbits_be16(&immr->im_ioport.iop_papar, 0xe810);
400 setbits_be16(&immr->im_ioport.iop_padir, 0x0810);
401 clrbits_be16(&immr->im_ioport.iop_padir, 0xe000);
403 setbits_be32(&immr->im_cpm.cp_pbpar, 0x00000001);
404 clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00000001);
406 setbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
407 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000050);
409 #endif /* !CONFIG_RMII */
413 * Configure all of port D for MII.
415 out_be16(&immr->im_ioport.iop_pdpar, 0x1fff);
416 out_be16(&immr->im_ioport.iop_pddir, 0x1fff);
418 #if defined(CONFIG_TARGET_MCR3000)
419 out_be16(&immr->im_ioport.iop_papar, 0xBBFF);
420 out_be16(&immr->im_ioport.iop_padir, 0x04F0);
421 out_be16(&immr->im_ioport.iop_paodr, 0x0000);
423 out_be32(&immr->im_cpm.cp_pbpar, 0x000133FF);
424 out_be32(&immr->im_cpm.cp_pbdir, 0x0003BF0F);
425 out_be16(&immr->im_cpm.cp_pbodr, 0x0000);
427 out_be16(&immr->im_ioport.iop_pcpar, 0x0400);
428 out_be16(&immr->im_ioport.iop_pcdir, 0x0080);
429 out_be16(&immr->im_ioport.iop_pcso , 0x0D53);
430 out_be16(&immr->im_ioport.iop_pcint, 0x0000);
432 out_be16(&immr->im_ioport.iop_pdpar, 0x03FE);
433 out_be16(&immr->im_ioport.iop_pddir, 0x1C09);
435 setbits_be32(&immr->im_ioport.utmode, 0x80);
439 #endif /* CONFIG_ETHER_ON_FEC1 */
440 } else if (fecidx == 1) {
441 #if defined(CONFIG_ETHER_ON_FEC2)
443 #if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
445 #if !defined(CONFIG_RMII)
446 setbits_be32(&immr->im_cpm.cp_pepar, 0x0003fffc);
447 setbits_be32(&immr->im_cpm.cp_pedir, 0x0003fffc);
448 clrbits_be32(&immr->im_cpm.cp_peso, 0x000087fc);
449 setbits_be32(&immr->im_cpm.cp_peso, 0x00037800);
451 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
454 #if !defined(CONFIG_FEC2_PHY_NORXERR)
455 setbits_be32(&immr->im_cpm.cp_pepar, 0x00000010);
456 setbits_be32(&immr->im_cpm.cp_pedir, 0x00000010);
457 clrbits_be32(&immr->im_cpm.cp_peso, 0x00000010);
459 setbits_be32(&immr->im_cpm.cp_pepar, 0x00039620);
460 setbits_be32(&immr->im_cpm.cp_pedir, 0x00039620);
461 setbits_be32(&immr->im_cpm.cp_peso, 0x00031000);
462 clrbits_be32(&immr->im_cpm.cp_peso, 0x00008620);
464 setbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
465 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000028);
466 #endif /* CONFIG_RMII */
468 #endif /* CONFIG_MPC885 */
470 #endif /* CONFIG_ETHER_ON_FEC2 */
474 static int fec_reset(fec_t __iomem *fecp)
479 * A delay is required between a reset of the FEC block and
480 * initialization of other FEC registers because the reset takes
481 * some time to complete. If you don't delay, subsequent writes
482 * to FEC registers might get killed by the reset routine which is
486 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
487 for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
488 (i < FEC_RESET_DELAY); ++i)
491 if (i == FEC_RESET_DELAY)
497 static int fec_init(struct eth_device *dev, bd_t *bd)
499 struct ether_fcc_info_s *efis = dev->priv;
500 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
501 fec_t __iomem *fecp =
502 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
505 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
506 /* the MII interface is connected to FEC1
507 * so for the miiphy_xxx function to work we must
508 * call mii_init since fec_halt messes the thing up
510 if (efis->ether_index != 0)
514 if (fec_reset(fecp) < 0)
515 printf("FEC_RESET_DELAY timeout\n");
517 /* We use strictly polling mode only
519 out_be32(&fecp->fec_imask, 0);
521 /* Clear any pending interrupt
523 out_be32(&fecp->fec_ievent, 0xffc0);
525 /* No need to set the IVEC register */
527 /* Set station address
529 #define ea dev->enetaddr
530 out_be32(&fecp->fec_addr_low, (ea[0] << 24) | (ea[1] << 16) |
531 (ea[2] << 8) | ea[3]);
532 out_be16(&fecp->fec_addr_high, (ea[4] << 8) | ea[5]);
535 #if defined(CONFIG_CMD_CDP)
537 * Turn on multicast address hash table
539 out_be32(&fecp->fec_hash_table_high, 0xffffffff);
540 out_be32(&fecp->fec_hash_table_low, 0xffffffff);
542 /* Clear multicast address hash table
544 out_be32(&fecp->fec_hash_table_high, 0);
545 out_be32(&fecp->fec_hash_table_low, 0);
548 /* Set maximum receive buffer size.
550 out_be32(&fecp->fec_r_buff_size, PKT_MAXBLR_SIZE);
552 /* Set maximum frame length
554 out_be32(&fecp->fec_r_hash, PKT_MAXBUF_SIZE);
557 * Setup Buffers and Buffer Descriptors
563 rtx = (struct common_buf_desc __iomem *)
564 (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
566 * Setup Receiver Buffer Descriptors (13.14.24.18)
570 for (i = 0; i < PKTBUFSRX; i++) {
571 out_be16(&rtx->rxbd[i].cbd_sc, BD_ENET_RX_EMPTY);
572 out_be16(&rtx->rxbd[i].cbd_datlen, 0); /* Reset */
573 out_be32(&rtx->rxbd[i].cbd_bufaddr, (uint)net_rx_packets[i]);
575 setbits_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc, BD_ENET_RX_WRAP);
578 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
582 for (i = 0; i < TX_BUF_CNT; i++) {
583 out_be16(&rtx->txbd[i].cbd_sc, BD_ENET_TX_LAST | BD_ENET_TX_TC);
584 out_be16(&rtx->txbd[i].cbd_datlen, 0); /* Reset */
585 out_be32(&rtx->txbd[i].cbd_bufaddr, (uint)txbuf);
587 setbits_be16(&rtx->txbd[TX_BUF_CNT - 1].cbd_sc, BD_ENET_TX_WRAP);
589 /* Set receive and transmit descriptor base
591 out_be32(&fecp->fec_r_des_start, (__force unsigned int)rtx->rxbd);
592 out_be32(&fecp->fec_x_des_start, (__force unsigned int)rtx->txbd);
596 /* Half duplex mode */
597 out_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT);
598 out_be32(&fecp->fec_x_cntrl, 0);
600 /* Enable big endian and don't care about SDMA FC.
602 out_be32(&fecp->fec_fun_code, 0x78000000);
605 * Setup the pin configuration of the FEC
607 fec_pin_init(efis->ether_index);
613 * Now enable the transmit and receive processing
615 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
617 if (efis->phy_addr == -1) {
618 #ifdef CONFIG_SYS_DISCOVER_PHY
620 * wait for the PHY to wake up after reset
622 efis->actual_phy_addr = mii_discover_phy(dev);
624 if (efis->actual_phy_addr == -1) {
625 printf("Unable to discover phy!\n");
629 efis->actual_phy_addr = -1;
632 efis->actual_phy_addr = efis->phy_addr;
635 #if defined(CONFIG_MII) && defined(CONFIG_RMII)
637 * adapt the RMII speed to the speed of the phy
639 if (miiphy_speed(dev->name, efis->actual_phy_addr) == _100BASET)
645 #if defined(CONFIG_MII)
647 * adapt to the half/full speed settings
649 if (miiphy_duplex(dev->name, efis->actual_phy_addr) == FULL)
650 fec_full_duplex(dev);
652 fec_half_duplex(dev);
655 /* And last, try to fill Rx Buffer Descriptors */
656 /* Descriptor polling active */
657 out_be32(&fecp->fec_r_des_active, 0x01000000);
659 efis->initialized = 1;
665 static void fec_halt(struct eth_device *dev)
667 struct ether_fcc_info_s *efis = dev->priv;
668 fec_t __iomem *fecp =
669 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
672 /* avoid halt if initialized; mii gets stuck otherwise */
673 if (!efis->initialized)
677 * A delay is required between a reset of the FEC block and
678 * initialization of other FEC registers because the reset takes
679 * some time to complete. If you don't delay, subsequent writes
680 * to FEC registers might get killed by the reset routine which is
684 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
685 for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
686 (i < FEC_RESET_DELAY); ++i)
689 if (i == FEC_RESET_DELAY) {
690 printf("FEC_RESET_DELAY timeout\n");
694 efis->initialized = 0;
697 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
699 /* Make MII read/write commands for the FEC.
702 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
705 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
706 (REG & 0x1f) << 18) | \
709 /* Interrupt events/masks.
711 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
712 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
713 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
714 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
715 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
716 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
717 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
718 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
719 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
720 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
722 /* send command to phy using mii, wait for result */
724 mii_send(uint mii_cmd)
729 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
731 ep = &immr->im_cpm.cp_fec;
733 out_be32(&ep->fec_mii_data, mii_cmd); /* command to phy */
735 /* wait for mii complete */
737 while (!(in_be32(&ep->fec_ievent) & FEC_ENET_MII)) {
739 printf("mii_send STUCK!\n");
743 mii_reply = in_be32(&ep->fec_mii_data); /* result from phy */
744 out_be32(&ep->fec_ievent, FEC_ENET_MII); /* clear MII complete */
745 return mii_reply & 0xffff; /* data read from phy */
749 #if defined(CONFIG_SYS_DISCOVER_PHY)
750 static int mii_discover_phy(struct eth_device *dev)
752 #define MAX_PHY_PASSES 11
758 phyaddr = -1; /* didn't find a PHY yet */
759 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
761 /* PHY may need more time to recover from reset.
762 * The LXT970 needs 50ms typical, no maximum is
763 * specified, so wait 10ms before try again.
764 * With 11 passes this gives it 100ms to wake up.
766 udelay(10000); /* wait 10ms */
768 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
769 phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2));
770 if (phytype != 0xffff) {
772 phytype |= mii_send(mk_mii_read(phyno,
778 printf("No PHY device found.\n");
782 #endif /* CONFIG_SYS_DISCOVER_PHY */
784 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
786 /****************************************************************************
787 * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
788 * This function is a subset of eth_init
789 ****************************************************************************
791 static void __mii_init(void)
793 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
794 fec_t __iomem *fecp = &immr->im_cpm.cp_fec;
796 if (fec_reset(fecp) < 0)
797 printf("FEC_RESET_DELAY timeout\n");
799 /* We use strictly polling mode only
801 out_be32(&fecp->fec_imask, 0);
803 /* Clear any pending interrupt
805 out_be32(&fecp->fec_ievent, 0xffc0);
807 /* Now enable the transmit and receive processing
809 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
818 /* Setup the pin configuration of the FEC(s)
820 for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
821 fec_pin_init(ether_fcc_info[i].ether_index);
824 /*****************************************************************************
825 * Read and write a MII PHY register, routines used by MII Utilities
827 * FIXME: These routines are expected to return 0 on success, but mii_send
828 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
829 * no PHY connected...
830 * For now always return 0.
831 * FIXME: These routines only work after calling eth_init() at least once!
832 * Otherwise they hang in mii_send() !!! Sorry!
833 *****************************************************************************/
835 int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
837 unsigned short value = 0;
838 short rdreg; /* register working value */
840 rdreg = mii_send(mk_mii_read(addr, reg));
846 int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
849 (void)mii_send(mk_mii_write(addr, reg, value));