2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
5 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
7 * Based on the Linux version which is:
8 * Copyright (C) 2012 Marvell
10 * Rami Rosen <rosenr@marvell.com>
11 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * SPDX-License-Identifier: GPL-2.0
23 #include <asm/errno.h>
27 #include <asm/arch/cpu.h>
28 #include <asm/arch/soc.h>
29 #include <linux/compat.h>
30 #include <linux/mbus.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #if !defined(CONFIG_PHYLIB)
35 # error Marvell mvneta requires PHYLIB
38 /* Some linux -> U-Boot compatibility stuff */
39 #define netdev_err(dev, fmt, args...) \
41 #define netdev_warn(dev, fmt, args...) \
43 #define netdev_info(dev, fmt, args...) \
46 #define CONFIG_NR_CPUS 1
47 #define ETH_HLEN 14 /* Total octets in header */
49 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
50 #define WRAP (2 + ETH_HLEN + 4 + 32)
52 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
54 #define MVNETA_SMI_TIMEOUT 10000
57 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
58 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
59 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
60 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
61 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
62 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
63 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
64 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
65 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
66 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
67 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
68 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
69 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
70 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
71 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
72 #define MVNETA_PORT_RX_RESET 0x1cc0
73 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
74 #define MVNETA_PHY_ADDR 0x2000
75 #define MVNETA_PHY_ADDR_MASK 0x1f
76 #define MVNETA_SMI 0x2004
77 #define MVNETA_PHY_REG_MASK 0x1f
78 /* SMI register fields */
79 #define MVNETA_SMI_DATA_OFFS 0 /* Data */
80 #define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS)
81 #define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
82 #define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
83 #define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
84 #define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS)
85 #define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */
86 #define MVNETA_SMI_BUSY (1 << 28) /* Busy */
87 #define MVNETA_MBUS_RETRY 0x2010
88 #define MVNETA_UNIT_INTR_CAUSE 0x2080
89 #define MVNETA_UNIT_CONTROL 0x20B0
90 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
91 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
92 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
93 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
94 #define MVNETA_BASE_ADDR_ENABLE 0x2290
95 #define MVNETA_PORT_CONFIG 0x2400
96 #define MVNETA_UNI_PROMISC_MODE BIT(0)
97 #define MVNETA_DEF_RXQ(q) ((q) << 1)
98 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
99 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
100 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
101 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
102 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
103 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
104 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
105 MVNETA_DEF_RXQ_ARP(q) | \
106 MVNETA_DEF_RXQ_TCP(q) | \
107 MVNETA_DEF_RXQ_UDP(q) | \
108 MVNETA_DEF_RXQ_BPDU(q) | \
109 MVNETA_TX_UNSET_ERR_SUM | \
110 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
111 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
112 #define MVNETA_MAC_ADDR_LOW 0x2414
113 #define MVNETA_MAC_ADDR_HIGH 0x2418
114 #define MVNETA_SDMA_CONFIG 0x241c
115 #define MVNETA_SDMA_BRST_SIZE_16 4
116 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
117 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
118 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
119 #define MVNETA_DESC_SWAP BIT(6)
120 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
121 #define MVNETA_PORT_STATUS 0x2444
122 #define MVNETA_TX_IN_PRGRS BIT(1)
123 #define MVNETA_TX_FIFO_EMPTY BIT(8)
124 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
125 #define MVNETA_SERDES_CFG 0x24A0
126 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
127 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
128 #define MVNETA_TYPE_PRIO 0x24bc
129 #define MVNETA_FORCE_UNI BIT(21)
130 #define MVNETA_TXQ_CMD_1 0x24e4
131 #define MVNETA_TXQ_CMD 0x2448
132 #define MVNETA_TXQ_DISABLE_SHIFT 8
133 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
134 #define MVNETA_ACC_MODE 0x2500
135 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
136 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
137 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
138 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
140 /* Exception Interrupt Port/Queue Cause register */
142 #define MVNETA_INTR_NEW_CAUSE 0x25a0
143 #define MVNETA_INTR_NEW_MASK 0x25a4
145 /* bits 0..7 = TXQ SENT, one bit per queue.
146 * bits 8..15 = RXQ OCCUP, one bit per queue.
147 * bits 16..23 = RXQ FREE, one bit per queue.
148 * bit 29 = OLD_REG_SUM, see old reg ?
149 * bit 30 = TX_ERR_SUM, one bit for 4 ports
150 * bit 31 = MISC_SUM, one bit for 4 ports
152 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
153 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
154 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
155 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
157 #define MVNETA_INTR_OLD_CAUSE 0x25a8
158 #define MVNETA_INTR_OLD_MASK 0x25ac
160 /* Data Path Port/Queue Cause Register */
161 #define MVNETA_INTR_MISC_CAUSE 0x25b0
162 #define MVNETA_INTR_MISC_MASK 0x25b4
163 #define MVNETA_INTR_ENABLE 0x25b8
165 #define MVNETA_RXQ_CMD 0x2680
166 #define MVNETA_RXQ_DISABLE_SHIFT 8
167 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
168 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
169 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
170 #define MVNETA_GMAC_CTRL_0 0x2c00
171 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
172 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
173 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
174 #define MVNETA_GMAC_CTRL_2 0x2c08
175 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
176 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
177 #define MVNETA_GMAC2_PORT_RESET BIT(6)
178 #define MVNETA_GMAC_STATUS 0x2c10
179 #define MVNETA_GMAC_LINK_UP BIT(0)
180 #define MVNETA_GMAC_SPEED_1000 BIT(1)
181 #define MVNETA_GMAC_SPEED_100 BIT(2)
182 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
183 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
184 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
185 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
186 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
187 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
188 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
189 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
190 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
191 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
192 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
193 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
194 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
195 #define MVNETA_MIB_COUNTERS_BASE 0x3080
196 #define MVNETA_MIB_LATE_COLLISION 0x7c
197 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
198 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
199 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
200 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
201 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
202 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
203 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
204 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
205 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
206 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
207 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
208 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
209 #define MVNETA_PORT_TX_RESET 0x3cf0
210 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
211 #define MVNETA_TX_MTU 0x3e0c
212 #define MVNETA_TX_TOKEN_SIZE 0x3e14
213 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
214 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
215 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
217 /* Descriptor ring Macros */
218 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
219 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
221 /* Various constants */
224 #define MVNETA_TXDONE_COAL_PKTS 16
225 #define MVNETA_RX_COAL_PKTS 32
226 #define MVNETA_RX_COAL_USEC 100
228 /* The two bytes Marvell header. Either contains a special value used
229 * by Marvell switches when a specific hardware mode is enabled (not
230 * supported by this driver) or is filled automatically by zeroes on
231 * the RX side. Those two bytes being at the front of the Ethernet
232 * header, they allow to have the IP header aligned on a 4 bytes
233 * boundary automatically: the hardware skips those two bytes on its
236 #define MVNETA_MH_SIZE 2
238 #define MVNETA_VLAN_TAG_LEN 4
240 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
241 #define MVNETA_TX_CSUM_MAX_SIZE 9800
242 #define MVNETA_ACC_MODE_EXT 1
244 /* Timeout constants */
245 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
246 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
247 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
249 #define MVNETA_TX_MTU_MAX 0x3ffff
251 /* Max number of Rx descriptors */
252 #define MVNETA_MAX_RXD 16
254 /* Max number of Tx descriptors */
255 #define MVNETA_MAX_TXD 16
257 /* descriptor aligned size */
258 #define MVNETA_DESC_ALIGNED_SIZE 32
262 struct mvneta_rx_queue *rxqs;
263 struct mvneta_tx_queue *txqs;
269 phy_interface_t phy_interface;
276 struct phy_device *phydev;
280 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
281 * layout of the transmit and reception DMA descriptors, and their
282 * layout is therefore defined by the hardware design
285 #define MVNETA_TX_L3_OFF_SHIFT 0
286 #define MVNETA_TX_IP_HLEN_SHIFT 8
287 #define MVNETA_TX_L4_UDP BIT(16)
288 #define MVNETA_TX_L3_IP6 BIT(17)
289 #define MVNETA_TXD_IP_CSUM BIT(18)
290 #define MVNETA_TXD_Z_PAD BIT(19)
291 #define MVNETA_TXD_L_DESC BIT(20)
292 #define MVNETA_TXD_F_DESC BIT(21)
293 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
294 MVNETA_TXD_L_DESC | \
296 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
297 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
299 #define MVNETA_RXD_ERR_CRC 0x0
300 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
301 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
302 #define MVNETA_RXD_ERR_LEN BIT(18)
303 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
304 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
305 #define MVNETA_RXD_L3_IP4 BIT(25)
306 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
307 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
309 struct mvneta_tx_desc {
310 u32 command; /* Options used by HW for packet transmitting.*/
311 u16 reserverd1; /* csum_l4 (for future use) */
312 u16 data_size; /* Data size of transmitted packet in bytes */
313 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
314 u32 reserved2; /* hw_cmd - (for future use, PMT) */
315 u32 reserved3[4]; /* Reserved - (for future use) */
318 struct mvneta_rx_desc {
319 u32 status; /* Info about received packet */
320 u16 reserved1; /* pnc_info - (for future use, PnC) */
321 u16 data_size; /* Size of received packet in bytes */
323 u32 buf_phys_addr; /* Physical address of the buffer */
324 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
326 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
327 u16 reserved3; /* prefetch_cmd, for future use */
328 u16 reserved4; /* csum_l4 - (for future use, PnC) */
330 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
331 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
334 struct mvneta_tx_queue {
335 /* Number of this TX queue, in the range 0-7 */
338 /* Number of TX DMA descriptors in the descriptor ring */
341 /* Index of last TX DMA descriptor that was inserted */
344 /* Index of the TX DMA descriptor to be cleaned up */
347 /* Virtual address of the TX DMA descriptors array */
348 struct mvneta_tx_desc *descs;
350 /* DMA address of the TX DMA descriptors array */
351 dma_addr_t descs_phys;
353 /* Index of the last TX DMA descriptor */
356 /* Index of the next TX DMA descriptor to process */
357 int next_desc_to_proc;
360 struct mvneta_rx_queue {
361 /* rx queue number, in the range 0-7 */
364 /* num of rx descriptors in the rx descriptor ring */
367 /* Virtual address of the RX DMA descriptors array */
368 struct mvneta_rx_desc *descs;
370 /* DMA address of the RX DMA descriptors array */
371 dma_addr_t descs_phys;
373 /* Index of the last RX DMA descriptor */
376 /* Index of the next RX DMA descriptor to process */
377 int next_desc_to_proc;
380 /* U-Boot doesn't use the queues, so set the number to 1 */
381 static int rxq_number = 1;
382 static int txq_number = 1;
385 struct buffer_location {
386 struct mvneta_tx_desc *tx_descs;
387 struct mvneta_rx_desc *rx_descs;
392 * All 4 interfaces use the same global buffer, since only one interface
393 * can be enabled at once
395 static struct buffer_location buffer_loc;
398 * Page table entries are set to 1MB, or multiples of 1MB
399 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
401 #define BD_SPACE (1 << 20)
403 /* Utility/helper methods */
405 /* Write helper method */
406 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
408 writel(data, pp->base + offset);
411 /* Read helper method */
412 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
414 return readl(pp->base + offset);
417 /* Clear all MIB counters */
418 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
422 /* Perform dummy reads from MIB counters */
423 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
424 mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
427 /* Rx descriptors helper methods */
429 /* Checks whether the RX descriptor having this status is both the first
430 * and the last descriptor for the RX packet. Each RX packet is currently
431 * received through a single RX descriptor, so not having each RX
432 * descriptor with its first and last bits set is an error
434 static int mvneta_rxq_desc_is_first_last(u32 status)
436 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
437 MVNETA_RXD_FIRST_LAST_DESC;
440 /* Add number of descriptors ready to receive new packets */
441 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
442 struct mvneta_rx_queue *rxq,
445 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
448 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
449 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
450 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
451 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
452 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
455 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
456 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
459 /* Get number of RX descriptors occupied by received packets */
460 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
461 struct mvneta_rx_queue *rxq)
465 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
466 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
469 /* Update num of rx desc called upon return from rx path or
470 * from mvneta_rxq_drop_pkts().
472 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
473 struct mvneta_rx_queue *rxq,
474 int rx_done, int rx_filled)
478 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
480 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
481 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
485 /* Only 255 descriptors can be added at once */
486 while ((rx_done > 0) || (rx_filled > 0)) {
487 if (rx_done <= 0xff) {
494 if (rx_filled <= 0xff) {
495 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
498 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
501 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
505 /* Get pointer to next RX descriptor to be processed by SW */
506 static struct mvneta_rx_desc *
507 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
509 int rx_desc = rxq->next_desc_to_proc;
511 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
512 return rxq->descs + rx_desc;
515 /* Tx descriptors helper methods */
517 /* Update HW with number of TX descriptors to be sent */
518 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
519 struct mvneta_tx_queue *txq,
524 /* Only 255 descriptors can be added at once ; Assume caller
525 * process TX desriptors in quanta less than 256
528 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
531 /* Get pointer to next TX descriptor to be processed (send) by HW */
532 static struct mvneta_tx_desc *
533 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
535 int tx_desc = txq->next_desc_to_proc;
537 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
538 return txq->descs + tx_desc;
541 /* Set rxq buf size */
542 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
543 struct mvneta_rx_queue *rxq,
548 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
550 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
551 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
553 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
556 /* Start the Ethernet port RX and TX activity */
557 static void mvneta_port_up(struct mvneta_port *pp)
562 /* Enable all initialized TXs. */
563 mvneta_mib_counters_clear(pp);
565 for (queue = 0; queue < txq_number; queue++) {
566 struct mvneta_tx_queue *txq = &pp->txqs[queue];
567 if (txq->descs != NULL)
568 q_map |= (1 << queue);
570 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
572 /* Enable all initialized RXQs. */
574 for (queue = 0; queue < rxq_number; queue++) {
575 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
576 if (rxq->descs != NULL)
577 q_map |= (1 << queue);
579 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
582 /* Stop the Ethernet port activity */
583 static void mvneta_port_down(struct mvneta_port *pp)
588 /* Stop Rx port activity. Check port Rx activity. */
589 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
591 /* Issue stop command for active channels only */
593 mvreg_write(pp, MVNETA_RXQ_CMD,
594 val << MVNETA_RXQ_DISABLE_SHIFT);
596 /* Wait for all Rx activity to terminate. */
599 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
601 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
607 val = mvreg_read(pp, MVNETA_RXQ_CMD);
608 } while (val & 0xff);
610 /* Stop Tx port activity. Check port Tx activity. Issue stop
611 * command for active channels only
613 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
616 mvreg_write(pp, MVNETA_TXQ_CMD,
617 (val << MVNETA_TXQ_DISABLE_SHIFT));
619 /* Wait for all Tx activity to terminate. */
622 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
624 "TIMEOUT for TX stopped status=0x%08x\n",
630 /* Check TX Command reg that all Txqs are stopped */
631 val = mvreg_read(pp, MVNETA_TXQ_CMD);
633 } while (val & 0xff);
635 /* Double check to verify that TX FIFO is empty */
638 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
640 "TX FIFO empty timeout status=0x08%x\n",
646 val = mvreg_read(pp, MVNETA_PORT_STATUS);
647 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
648 (val & MVNETA_TX_IN_PRGRS));
653 /* Enable the port by setting the port enable bit of the MAC control register */
654 static void mvneta_port_enable(struct mvneta_port *pp)
659 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
660 val |= MVNETA_GMAC0_PORT_ENABLE;
661 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
664 /* Disable the port and wait for about 200 usec before retuning */
665 static void mvneta_port_disable(struct mvneta_port *pp)
669 /* Reset the Enable bit in the Serial Control Register */
670 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
671 val &= ~MVNETA_GMAC0_PORT_ENABLE;
672 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
677 /* Multicast tables methods */
679 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
680 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
688 val = 0x1 | (queue << 1);
689 val |= (val << 24) | (val << 16) | (val << 8);
692 for (offset = 0; offset <= 0xc; offset += 4)
693 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
696 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
697 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
705 val = 0x1 | (queue << 1);
706 val |= (val << 24) | (val << 16) | (val << 8);
709 for (offset = 0; offset <= 0xfc; offset += 4)
710 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
713 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
714 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
720 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
723 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
724 val = 0x1 | (queue << 1);
725 val |= (val << 24) | (val << 16) | (val << 8);
728 for (offset = 0; offset <= 0xfc; offset += 4)
729 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
732 /* This method sets defaults to the NETA port:
733 * Clears interrupt Cause and Mask registers.
734 * Clears all MAC tables.
735 * Sets defaults to all registers.
736 * Resets RX and TX descriptor rings.
738 * This method can be called after mvneta_port_down() to return the port
739 * settings to defaults.
741 static void mvneta_defaults_set(struct mvneta_port *pp)
747 /* Clear all Cause registers */
748 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
749 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
750 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
752 /* Mask all interrupts */
753 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
754 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
755 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
756 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
758 /* Enable MBUS Retry bit16 */
759 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
761 /* Set CPU queue access map - all CPUs have access to all RX
762 * queues and to all TX queues
764 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
765 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
766 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
767 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
769 /* Reset RX and TX DMAs */
770 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
771 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
773 /* Disable Legacy WRR, Disable EJP, Release from reset */
774 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
775 for (queue = 0; queue < txq_number; queue++) {
776 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
777 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
780 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
781 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
783 /* Set Port Acceleration Mode */
784 val = MVNETA_ACC_MODE_EXT;
785 mvreg_write(pp, MVNETA_ACC_MODE, val);
787 /* Update val of portCfg register accordingly with all RxQueue types */
788 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
789 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
792 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
793 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
795 /* Build PORT_SDMA_CONFIG_REG */
798 /* Default burst size */
799 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
800 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
801 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
803 /* Assign port SDMA configuration */
804 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
806 /* Enable PHY polling in hardware for U-Boot */
807 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
808 val |= MVNETA_PHY_POLLING_ENABLE;
809 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
811 mvneta_set_ucast_table(pp, -1);
812 mvneta_set_special_mcast_table(pp, -1);
813 mvneta_set_other_mcast_table(pp, -1);
816 /* Set unicast address */
817 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
820 unsigned int unicast_reg;
821 unsigned int tbl_offset;
822 unsigned int reg_offset;
824 /* Locate the Unicast table entry */
825 last_nibble = (0xf & last_nibble);
827 /* offset from unicast tbl base */
828 tbl_offset = (last_nibble / 4) * 4;
830 /* offset within the above reg */
831 reg_offset = last_nibble % 4;
833 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
836 /* Clear accepts frame bit at specified unicast DA tbl entry */
837 unicast_reg &= ~(0xff << (8 * reg_offset));
839 unicast_reg &= ~(0xff << (8 * reg_offset));
840 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
843 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
846 /* Set mac address */
847 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
854 mac_l = (addr[4] << 8) | (addr[5]);
855 mac_h = (addr[0] << 24) | (addr[1] << 16) |
856 (addr[2] << 8) | (addr[3] << 0);
858 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
859 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
862 /* Accept frames of this address */
863 mvneta_set_ucast_addr(pp, addr[5], queue);
866 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
867 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
868 u32 phys_addr, u32 cookie)
870 rx_desc->buf_cookie = cookie;
871 rx_desc->buf_phys_addr = phys_addr;
874 /* Decrement sent descriptors counter */
875 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
876 struct mvneta_tx_queue *txq,
881 /* Only 255 TX descriptors can be updated at once */
882 while (sent_desc > 0xff) {
883 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
884 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
885 sent_desc = sent_desc - 0xff;
888 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
889 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
892 /* Get number of TX descriptors already sent by HW */
893 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
894 struct mvneta_tx_queue *txq)
899 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
900 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
901 MVNETA_TXQ_SENT_DESC_SHIFT;
906 /* Display more error info */
907 static void mvneta_rx_error(struct mvneta_port *pp,
908 struct mvneta_rx_desc *rx_desc)
910 u32 status = rx_desc->status;
912 if (!mvneta_rxq_desc_is_first_last(status)) {
914 "bad rx status %08x (buffer oversize), size=%d\n",
915 status, rx_desc->data_size);
919 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
920 case MVNETA_RXD_ERR_CRC:
921 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
922 status, rx_desc->data_size);
924 case MVNETA_RXD_ERR_OVERRUN:
925 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
926 status, rx_desc->data_size);
928 case MVNETA_RXD_ERR_LEN:
929 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
930 status, rx_desc->data_size);
932 case MVNETA_RXD_ERR_RESOURCE:
933 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
934 status, rx_desc->data_size);
939 static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp,
942 return &pp->rxqs[rxq];
946 /* Drop packets received by the RXQ and free buffers */
947 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
948 struct mvneta_rx_queue *rxq)
952 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
954 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
957 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
958 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
963 for (i = 0; i < num; i++) {
966 /* U-Boot special: Fill in the rx buffer addresses */
967 addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE);
968 mvneta_rx_desc_fill(rxq->descs + i, addr, addr);
971 /* Add this number of RX descriptors as non occupied (ready to
974 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
979 /* Rx/Tx queue initialization/cleanup methods */
981 /* Create a specified RX queue */
982 static int mvneta_rxq_init(struct mvneta_port *pp,
983 struct mvneta_rx_queue *rxq)
986 rxq->size = pp->rx_ring_size;
988 /* Allocate memory for RX descriptors */
989 rxq->descs_phys = (dma_addr_t)rxq->descs;
990 if (rxq->descs == NULL)
993 rxq->last_desc = rxq->size - 1;
995 /* Set Rx descriptors queue starting address */
996 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
997 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
999 /* Fill RXQ with buffers from RX pool */
1000 mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE);
1001 mvneta_rxq_fill(pp, rxq, rxq->size);
1006 /* Cleanup Rx queue */
1007 static void mvneta_rxq_deinit(struct mvneta_port *pp,
1008 struct mvneta_rx_queue *rxq)
1010 mvneta_rxq_drop_pkts(pp, rxq);
1014 rxq->next_desc_to_proc = 0;
1015 rxq->descs_phys = 0;
1018 /* Create and initialize a tx queue */
1019 static int mvneta_txq_init(struct mvneta_port *pp,
1020 struct mvneta_tx_queue *txq)
1022 txq->size = pp->tx_ring_size;
1024 /* Allocate memory for TX descriptors */
1025 txq->descs_phys = (u32)txq->descs;
1026 if (txq->descs == NULL)
1029 txq->last_desc = txq->size - 1;
1031 /* Set maximum bandwidth for enabled TXQs */
1032 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
1033 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
1035 /* Set Tx descriptors queue starting address */
1036 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
1037 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
1042 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
1043 static void mvneta_txq_deinit(struct mvneta_port *pp,
1044 struct mvneta_tx_queue *txq)
1048 txq->next_desc_to_proc = 0;
1049 txq->descs_phys = 0;
1051 /* Set minimum bandwidth for disabled TXQs */
1052 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
1053 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
1055 /* Set Tx descriptors queue starting address and size */
1056 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
1057 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
1060 /* Cleanup all Tx queues */
1061 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
1065 for (queue = 0; queue < txq_number; queue++)
1066 mvneta_txq_deinit(pp, &pp->txqs[queue]);
1069 /* Cleanup all Rx queues */
1070 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
1074 for (queue = 0; queue < rxq_number; queue++)
1075 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
1079 /* Init all Rx queues */
1080 static int mvneta_setup_rxqs(struct mvneta_port *pp)
1084 for (queue = 0; queue < rxq_number; queue++) {
1085 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
1087 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
1089 mvneta_cleanup_rxqs(pp);
1097 /* Init all tx queues */
1098 static int mvneta_setup_txqs(struct mvneta_port *pp)
1102 for (queue = 0; queue < txq_number; queue++) {
1103 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
1105 netdev_err(pp->dev, "%s: can't create txq=%d\n",
1107 mvneta_cleanup_txqs(pp);
1115 static void mvneta_start_dev(struct mvneta_port *pp)
1117 /* start the Rx/Tx activity */
1118 mvneta_port_enable(pp);
1121 static void mvneta_adjust_link(struct udevice *dev)
1123 struct mvneta_port *pp = dev_get_priv(dev);
1124 struct phy_device *phydev = pp->phydev;
1125 int status_change = 0;
1128 if ((pp->speed != phydev->speed) ||
1129 (pp->duplex != phydev->duplex)) {
1132 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1133 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
1134 MVNETA_GMAC_CONFIG_GMII_SPEED |
1135 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
1136 MVNETA_GMAC_AN_SPEED_EN |
1137 MVNETA_GMAC_AN_DUPLEX_EN);
1140 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
1142 if (phydev->speed == SPEED_1000)
1143 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
1145 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
1147 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1149 pp->duplex = phydev->duplex;
1150 pp->speed = phydev->speed;
1154 if (phydev->link != pp->link) {
1155 if (!phydev->link) {
1160 pp->link = phydev->link;
1164 if (status_change) {
1166 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1167 val |= (MVNETA_GMAC_FORCE_LINK_PASS |
1168 MVNETA_GMAC_FORCE_LINK_DOWN);
1169 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1172 mvneta_port_down(pp);
1177 static int mvneta_open(struct udevice *dev)
1179 struct mvneta_port *pp = dev_get_priv(dev);
1182 ret = mvneta_setup_rxqs(pp);
1186 ret = mvneta_setup_txqs(pp);
1190 mvneta_adjust_link(dev);
1192 mvneta_start_dev(pp);
1198 static int mvneta_init2(struct mvneta_port *pp)
1203 mvneta_port_disable(pp);
1205 /* Set port default values */
1206 mvneta_defaults_set(pp);
1208 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
1213 /* U-Boot special: use preallocated area */
1214 pp->txqs[0].descs = buffer_loc.tx_descs;
1216 /* Initialize TX descriptor rings */
1217 for (queue = 0; queue < txq_number; queue++) {
1218 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1220 txq->size = pp->tx_ring_size;
1223 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
1230 /* U-Boot special: use preallocated area */
1231 pp->rxqs[0].descs = buffer_loc.rx_descs;
1233 /* Create Rx descriptor rings */
1234 for (queue = 0; queue < rxq_number; queue++) {
1235 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1237 rxq->size = pp->rx_ring_size;
1243 /* platform glue : initialize decoding windows */
1244 static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
1246 const struct mbus_dram_target_info *dram;
1251 dram = mvebu_mbus_dram_info();
1252 for (i = 0; i < 6; i++) {
1253 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
1254 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
1257 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
1263 for (i = 0; i < dram->num_cs; i++) {
1264 const struct mbus_dram_window *cs = dram->cs + i;
1265 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
1266 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
1268 mvreg_write(pp, MVNETA_WIN_SIZE(i),
1269 (cs->size - 1) & 0xffff0000);
1271 win_enable &= ~(1 << i);
1272 win_protect |= 3 << (2 * i);
1275 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
1278 /* Power up the port */
1279 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
1283 /* MAC Cause register should be cleared */
1284 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
1286 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1288 /* Even though it might look weird, when we're configured in
1289 * SGMII or QSGMII mode, the RGMII bit needs to be set.
1292 case PHY_INTERFACE_MODE_QSGMII:
1293 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
1294 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
1296 case PHY_INTERFACE_MODE_SGMII:
1297 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
1298 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
1300 case PHY_INTERFACE_MODE_RGMII:
1301 case PHY_INTERFACE_MODE_RGMII_ID:
1302 ctrl |= MVNETA_GMAC2_PORT_RGMII;
1308 /* Cancel Port Reset */
1309 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
1310 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
1312 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
1313 MVNETA_GMAC2_PORT_RESET) != 0)
1319 /* Device initialization routine */
1320 static int mvneta_init(struct udevice *dev)
1322 struct eth_pdata *pdata = dev_get_platdata(dev);
1323 struct mvneta_port *pp = dev_get_priv(dev);
1326 pp->tx_ring_size = MVNETA_MAX_TXD;
1327 pp->rx_ring_size = MVNETA_MAX_RXD;
1329 err = mvneta_init2(pp);
1331 dev_err(&pdev->dev, "can't init eth hal\n");
1335 mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def);
1337 err = mvneta_port_power_up(pp, pp->phy_interface);
1339 dev_err(&pdev->dev, "can't power up port\n");
1343 /* Call open() now as it needs to be done before runing send() */
1349 /* U-Boot only functions follow here */
1351 /* SMI / MDIO functions */
1353 static int smi_wait_ready(struct mvneta_port *pp)
1355 u32 timeout = MVNETA_SMI_TIMEOUT;
1358 /* wait till the SMI is not busy */
1360 /* read smi register */
1361 smi_reg = mvreg_read(pp, MVNETA_SMI);
1362 if (timeout-- == 0) {
1363 printf("Error: SMI busy timeout\n");
1366 } while (smi_reg & MVNETA_SMI_BUSY);
1372 * mvneta_mdio_read - miiphy_read callback function.
1374 * Returns 16bit phy register value, or 0xffff on error
1376 static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
1378 struct mvneta_port *pp = bus->priv;
1382 /* check parameters */
1383 if (addr > MVNETA_PHY_ADDR_MASK) {
1384 printf("Error: Invalid PHY address %d\n", addr);
1388 if (reg > MVNETA_PHY_REG_MASK) {
1389 printf("Err: Invalid register offset %d\n", reg);
1393 /* wait till the SMI is not busy */
1394 if (smi_wait_ready(pp) < 0)
1397 /* fill the phy address and regiser offset and read opcode */
1398 smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS)
1399 | (reg << MVNETA_SMI_REG_ADDR_OFFS)
1400 | MVNETA_SMI_OPCODE_READ;
1402 /* write the smi register */
1403 mvreg_write(pp, MVNETA_SMI, smi_reg);
1405 /* wait till read value is ready */
1406 timeout = MVNETA_SMI_TIMEOUT;
1409 /* read smi register */
1410 smi_reg = mvreg_read(pp, MVNETA_SMI);
1411 if (timeout-- == 0) {
1412 printf("Err: SMI read ready timeout\n");
1415 } while (!(smi_reg & MVNETA_SMI_READ_VALID));
1417 /* Wait for the data to update in the SMI register */
1418 for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++)
1421 return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK;
1425 * mvneta_mdio_write - miiphy_write callback function.
1427 * Returns 0 if write succeed, -EINVAL on bad parameters
1430 static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
1433 struct mvneta_port *pp = bus->priv;
1436 /* check parameters */
1437 if (addr > MVNETA_PHY_ADDR_MASK) {
1438 printf("Error: Invalid PHY address %d\n", addr);
1442 if (reg > MVNETA_PHY_REG_MASK) {
1443 printf("Err: Invalid register offset %d\n", reg);
1447 /* wait till the SMI is not busy */
1448 if (smi_wait_ready(pp) < 0)
1451 /* fill the phy addr and reg offset and write opcode and data */
1452 smi_reg = value << MVNETA_SMI_DATA_OFFS;
1453 smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS)
1454 | (reg << MVNETA_SMI_REG_ADDR_OFFS);
1455 smi_reg &= ~MVNETA_SMI_OPCODE_READ;
1457 /* write the smi register */
1458 mvreg_write(pp, MVNETA_SMI, smi_reg);
1463 static int mvneta_start(struct udevice *dev)
1465 struct mvneta_port *pp = dev_get_priv(dev);
1466 struct phy_device *phydev;
1468 mvneta_port_power_up(pp, pp->phy_interface);
1470 if (!pp->init || pp->link == 0) {
1471 /* Set phy address of the port */
1472 mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr);
1473 phydev = phy_connect(pp->bus, pp->phyaddr, dev,
1476 pp->phydev = phydev;
1478 phy_startup(phydev);
1479 if (!phydev->link) {
1480 printf("%s: No link.\n", phydev->dev->name);
1484 /* Full init on first call */
1488 /* Upon all following calls, this is enough */
1490 mvneta_port_enable(pp);
1496 static int mvneta_send(struct udevice *dev, void *packet, int length)
1498 struct mvneta_port *pp = dev_get_priv(dev);
1499 struct mvneta_tx_queue *txq = &pp->txqs[0];
1500 struct mvneta_tx_desc *tx_desc;
1504 /* Get a descriptor for the first part of the packet */
1505 tx_desc = mvneta_txq_next_desc_get(txq);
1507 tx_desc->buf_phys_addr = (u32)packet;
1508 tx_desc->data_size = length;
1509 flush_dcache_range((u32)packet, (u32)packet + length);
1511 /* First and Last descriptor */
1512 tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
1513 mvneta_txq_pend_desc_add(pp, txq, 1);
1515 /* Wait for packet to be sent (queue might help with speed here) */
1516 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1517 while (!sent_desc) {
1518 if (timeout++ > 10000) {
1519 printf("timeout: packet not sent\n");
1522 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1525 /* txDone has increased - hw sent packet */
1526 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1531 static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
1533 struct mvneta_port *pp = dev_get_priv(dev);
1535 struct mvneta_rx_queue *rxq;
1539 rxq = mvneta_rxq_handle_get(pp, rxq_def);
1540 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1543 struct mvneta_rx_desc *rx_desc;
1544 unsigned char *data;
1548 * No cache invalidation needed here, since the desc's are
1549 * located in a uncached memory region
1551 rx_desc = mvneta_rxq_next_desc_get(rxq);
1553 rx_status = rx_desc->status;
1554 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1555 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1556 mvneta_rx_error(pp, rx_desc);
1557 /* leave the descriptor untouched */
1561 /* 2 bytes for marvell header. 4 bytes for crc */
1562 rx_bytes = rx_desc->data_size - 6;
1564 /* give packet to stack - skip on first 2 bytes */
1565 data = (u8 *)rx_desc->buf_cookie + 2;
1567 * No cache invalidation needed here, since the rx_buffer's are
1568 * located in a uncached memory region
1572 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1578 static int mvneta_probe(struct udevice *dev)
1580 struct eth_pdata *pdata = dev_get_platdata(dev);
1581 struct mvneta_port *pp = dev_get_priv(dev);
1582 void *blob = (void *)gd->fdt_blob;
1583 int node = dev->of_offset;
1584 struct mii_dev *bus;
1589 * Allocate buffer area for descs and rx_buffers. This is only
1590 * done once for all interfaces. As only one interface can
1591 * be active. Make this area DMA save by disabling the D-cache
1593 if (!buffer_loc.tx_descs) {
1594 /* Align buffer area for descs and rx_buffers to 1MiB */
1595 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
1596 mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE,
1598 buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
1599 buffer_loc.rx_descs = (struct mvneta_rx_desc *)
1601 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc));
1602 buffer_loc.rx_buffers = (u32)
1604 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) +
1605 MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc));
1608 pp->base = (void __iomem *)pdata->iobase;
1610 /* Configure MBUS address windows */
1611 mvneta_conf_mbus_windows(pp);
1613 /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
1614 pp->phy_interface = pdata->phy_interface;
1616 /* Now read phyaddr from DT */
1617 addr = fdtdec_get_int(blob, node, "phy", 0);
1618 addr = fdt_node_offset_by_phandle(blob, addr);
1619 pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
1623 printf("Failed to allocate MDIO bus\n");
1627 bus->read = mvneta_mdio_read;
1628 bus->write = mvneta_mdio_write;
1629 snprintf(bus->name, sizeof(bus->name), dev->name);
1630 bus->priv = (void *)pp;
1633 return mdio_register(bus);
1636 static void mvneta_stop(struct udevice *dev)
1638 struct mvneta_port *pp = dev_get_priv(dev);
1640 mvneta_port_down(pp);
1641 mvneta_port_disable(pp);
1644 static const struct eth_ops mvneta_ops = {
1645 .start = mvneta_start,
1646 .send = mvneta_send,
1647 .recv = mvneta_recv,
1648 .stop = mvneta_stop,
1651 static int mvneta_ofdata_to_platdata(struct udevice *dev)
1653 struct eth_pdata *pdata = dev_get_platdata(dev);
1654 const char *phy_mode;
1656 pdata->iobase = dev_get_addr(dev);
1658 /* Get phy-mode / phy_interface from DT */
1659 pdata->phy_interface = -1;
1660 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
1662 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1663 if (pdata->phy_interface == -1) {
1664 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1671 static const struct udevice_id mvneta_ids[] = {
1672 { .compatible = "marvell,armada-370-neta" },
1673 { .compatible = "marvell,armada-xp-neta" },
1677 U_BOOT_DRIVER(mvneta) = {
1680 .of_match = mvneta_ids,
1681 .ofdata_to_platdata = mvneta_ofdata_to_platdata,
1682 .probe = mvneta_probe,
1684 .priv_auto_alloc_size = sizeof(struct mvneta_port),
1685 .platdata_auto_alloc_size = sizeof(struct eth_pdata),