2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
18 #include <dm/device-internal.h>
25 #include <linux/errno.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/soc.h>
31 #include <linux/compat.h>
32 #include <linux/mbus.h>
33 #include <asm-generic/gpio.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 /* Some linux -> U-Boot compatibility stuff */
38 #define netdev_err(dev, fmt, args...) \
40 #define netdev_warn(dev, fmt, args...) \
42 #define netdev_info(dev, fmt, args...) \
44 #define netdev_dbg(dev, fmt, args...) \
47 #define ETH_ALEN 6 /* Octets in one ethernet addr */
49 #define __verify_pcpu_ptr(ptr) \
51 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
55 #define VERIFY_PERCPU_PTR(__p) \
57 __verify_pcpu_ptr(__p); \
58 (typeof(*(__p)) __kernel __force *)(__p); \
61 #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
62 #define smp_processor_id() 0
63 #define num_present_cpus() 1
64 #define for_each_present_cpu(cpu) \
65 for ((cpu) = 0; (cpu) < 1; (cpu)++)
67 #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
69 #define CONFIG_NR_CPUS 1
70 #define ETH_HLEN ETHER_HDR_SIZE /* Total octets in header */
72 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
73 #define WRAP (2 + ETH_HLEN + 4 + 32)
75 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
77 #define MVPP2_SMI_TIMEOUT 10000
79 /* RX Fifo Registers */
80 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
81 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
82 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
83 #define MVPP2_RX_FIFO_INIT_REG 0x64
85 /* RX DMA Top Registers */
86 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
87 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
88 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
89 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
90 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
91 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
92 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
93 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
94 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
95 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
96 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
97 #define MVPP2_RXQ_POOL_LONG_OFFS 24
98 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
99 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
100 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
101 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
102 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
104 /* Parser Registers */
105 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
106 #define MVPP2_PRS_PORT_LU_MAX 0xf
107 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
108 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
109 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
110 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
111 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
112 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
113 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
114 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
115 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
116 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
117 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
118 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
119 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
120 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
121 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
123 /* Classifier Registers */
124 #define MVPP2_CLS_MODE_REG 0x1800
125 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
126 #define MVPP2_CLS_PORT_WAY_REG 0x1810
127 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
128 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
129 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
130 #define MVPP2_CLS_LKP_TBL_REG 0x1818
131 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
132 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
133 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
134 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
135 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
136 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
137 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
138 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
139 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
140 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
141 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
142 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
144 /* Descriptor Manager Top Registers */
145 #define MVPP2_RXQ_NUM_REG 0x2040
146 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
147 #define MVPP22_DESC_ADDR_OFFS 8
148 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
149 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
150 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
151 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
152 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
153 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
154 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
155 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
156 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
157 #define MVPP2_RXQ_THRESH_REG 0x204c
158 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
159 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
160 #define MVPP2_RXQ_INDEX_REG 0x2050
161 #define MVPP2_TXQ_NUM_REG 0x2080
162 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
163 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
164 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
165 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
166 #define MVPP2_TXQ_THRESH_REG 0x2094
167 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
168 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
169 #define MVPP2_TXQ_INDEX_REG 0x2098
170 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
171 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
172 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
173 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
174 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
175 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
176 #define MVPP2_TXQ_PENDING_REG 0x20a0
177 #define MVPP2_TXQ_PENDING_MASK 0x3fff
178 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
179 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
180 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
181 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
182 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
183 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
184 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
185 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
186 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
187 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
188 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
189 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
190 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
191 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
192 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
193 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
194 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
196 /* MBUS bridge registers */
197 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
198 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
199 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
200 #define MVPP2_BASE_ADDR_ENABLE 0x4060
202 /* AXI Bridge Registers */
203 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
204 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
205 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
206 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
207 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
208 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
209 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
210 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
211 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
212 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
213 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
214 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
216 /* Values for AXI Bridge registers */
217 #define MVPP22_AXI_ATTR_CACHE_OFFS 0
218 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
220 #define MVPP22_AXI_CODE_CACHE_OFFS 0
221 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4
223 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
224 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
225 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
227 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
228 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
230 /* Interrupt Cause and Mask registers */
231 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
232 #define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
234 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
235 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
236 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
237 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
239 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
240 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
242 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
243 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
244 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
245 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
247 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
248 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
249 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
250 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
251 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
252 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
253 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
254 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
255 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
256 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
257 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
258 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
259 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
260 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
261 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
262 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
263 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
264 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
266 /* Buffer Manager registers */
267 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
268 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
269 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
270 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
271 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
272 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
273 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
274 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
275 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
276 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
277 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
278 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
279 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
280 #define MVPP2_BM_START_MASK BIT(0)
281 #define MVPP2_BM_STOP_MASK BIT(1)
282 #define MVPP2_BM_STATE_MASK BIT(4)
283 #define MVPP2_BM_LOW_THRESH_OFFS 8
284 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
285 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
286 MVPP2_BM_LOW_THRESH_OFFS)
287 #define MVPP2_BM_HIGH_THRESH_OFFS 16
288 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
289 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
290 MVPP2_BM_HIGH_THRESH_OFFS)
291 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
292 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
293 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
294 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
295 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
296 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
297 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
298 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
299 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
300 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
301 #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
302 #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
303 #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
304 #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
305 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
306 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
307 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
308 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
309 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
310 #define MVPP21_BM_MC_RLS_REG 0x64c4
311 #define MVPP2_BM_MC_ID_MASK 0xfff
312 #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
313 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
314 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
315 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
316 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
317 #define MVPP22_BM_MC_RLS_REG 0x64d4
319 /* TX Scheduler registers */
320 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
321 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
322 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
323 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
324 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
325 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
326 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
327 #define MVPP2_TXP_MTU_MAX 0x7FFFF
328 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
329 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
330 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
331 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
332 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
333 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
334 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
335 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
336 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
337 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
338 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
339 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
340 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
341 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
343 /* TX general registers */
344 #define MVPP2_TX_SNOOP_REG 0x8800
345 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
346 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
349 #define MVPP2_SRC_ADDR_MIDDLE 0x24
350 #define MVPP2_SRC_ADDR_HIGH 0x28
351 #define MVPP2_PHY_AN_CFG0_REG 0x34
352 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
353 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
354 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
356 /* Per-port registers */
357 #define MVPP2_GMAC_CTRL_0_REG 0x0
358 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
359 #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
360 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
361 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
362 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
363 #define MVPP2_GMAC_CTRL_1_REG 0x4
364 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
365 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
366 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
367 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
368 #define MVPP2_GMAC_SA_LOW_OFFS 7
369 #define MVPP2_GMAC_CTRL_2_REG 0x8
370 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
371 #define MVPP2_GMAC_SGMII_MODE_MASK BIT(0)
372 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
373 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
374 #define MVPP2_GMAC_PORT_DIS_PADING_MASK BIT(5)
375 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
376 #define MVPP2_GMAC_CLK_125_BYPS_EN_MASK BIT(9)
377 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
378 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
379 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
380 #define MVPP2_GMAC_EN_PCS_AN BIT(2)
381 #define MVPP2_GMAC_AN_BYPASS_EN BIT(3)
382 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
383 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
384 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
385 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
386 #define MVPP2_GMAC_EN_FC_AN BIT(11)
387 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
388 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
389 #define MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG BIT(15)
390 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
391 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
392 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
393 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
394 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
395 #define MVPP2_GMAC_CTRL_4_REG 0x90
396 #define MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK BIT(0)
397 #define MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK BIT(5)
398 #define MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK BIT(6)
399 #define MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK BIT(7)
402 * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
403 * relative to port->base.
406 /* Port Mac Control0 */
407 #define MVPP22_XLG_CTRL0_REG 0x100
408 #define MVPP22_XLG_PORT_EN BIT(0)
409 #define MVPP22_XLG_MAC_RESETN BIT(1)
410 #define MVPP22_XLG_RX_FC_EN BIT(7)
411 #define MVPP22_XLG_MIBCNT_DIS BIT(13)
412 /* Port Mac Control1 */
413 #define MVPP22_XLG_CTRL1_REG 0x104
414 #define MVPP22_XLG_MAX_RX_SIZE_OFFS 0
415 #define MVPP22_XLG_MAX_RX_SIZE_MASK 0x1fff
416 /* Port Interrupt Mask */
417 #define MVPP22_XLG_INTERRUPT_MASK_REG 0x118
418 #define MVPP22_XLG_INTERRUPT_LINK_CHANGE BIT(1)
419 /* Port Mac Control3 */
420 #define MVPP22_XLG_CTRL3_REG 0x11c
421 #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
422 #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
423 #define MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC (1 << 13)
424 /* Port Mac Control4 */
425 #define MVPP22_XLG_CTRL4_REG 0x184
426 #define MVPP22_XLG_FORWARD_802_3X_FC_EN BIT(5)
427 #define MVPP22_XLG_FORWARD_PFC_EN BIT(6)
428 #define MVPP22_XLG_MODE_DMA_1G BIT(12)
429 #define MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK BIT(14)
433 /* Global Configuration 0 */
434 #define MVPP22_XPCS_GLOBAL_CFG_0_REG 0x0
435 #define MVPP22_XPCS_PCSRESET BIT(0)
436 #define MVPP22_XPCS_PCSMODE_OFFS 3
437 #define MVPP22_XPCS_PCSMODE_MASK (0x3 << \
438 MVPP22_XPCS_PCSMODE_OFFS)
439 #define MVPP22_XPCS_LANEACTIVE_OFFS 5
440 #define MVPP22_XPCS_LANEACTIVE_MASK (0x3 << \
441 MVPP22_XPCS_LANEACTIVE_OFFS)
445 #define PCS40G_COMMON_CONTROL 0x14
446 #define FORWARD_ERROR_CORRECTION_MASK BIT(10)
448 #define PCS_CLOCK_RESET 0x14c
449 #define TX_SD_CLK_RESET_MASK BIT(0)
450 #define RX_SD_CLK_RESET_MASK BIT(1)
451 #define MAC_CLK_RESET_MASK BIT(2)
452 #define CLK_DIVISION_RATIO_OFFS 4
453 #define CLK_DIVISION_RATIO_MASK (0x7 << CLK_DIVISION_RATIO_OFFS)
454 #define CLK_DIV_PHASE_SET_MASK BIT(11)
456 /* System Soft Reset 1 */
457 #define GOP_SOFT_RESET_1_REG 0x108
458 #define NETC_GOP_SOFT_RESET_OFFS 6
459 #define NETC_GOP_SOFT_RESET_MASK (0x1 << \
460 NETC_GOP_SOFT_RESET_OFFS)
462 /* Ports Control 0 */
463 #define NETCOMP_PORTS_CONTROL_0_REG 0x110
464 #define NETC_BUS_WIDTH_SELECT_OFFS 1
465 #define NETC_BUS_WIDTH_SELECT_MASK (0x1 << \
466 NETC_BUS_WIDTH_SELECT_OFFS)
467 #define NETC_GIG_RX_DATA_SAMPLE_OFFS 29
468 #define NETC_GIG_RX_DATA_SAMPLE_MASK (0x1 << \
469 NETC_GIG_RX_DATA_SAMPLE_OFFS)
470 #define NETC_CLK_DIV_PHASE_OFFS 31
471 #define NETC_CLK_DIV_PHASE_MASK (0x1 << NETC_CLK_DIV_PHASE_OFFS)
472 /* Ports Control 1 */
473 #define NETCOMP_PORTS_CONTROL_1_REG 0x114
474 #define NETC_PORTS_ACTIVE_OFFSET(p) (0 + p)
475 #define NETC_PORTS_ACTIVE_MASK(p) (0x1 << \
476 NETC_PORTS_ACTIVE_OFFSET(p))
477 #define NETC_PORT_GIG_RF_RESET_OFFS(p) (28 + p)
478 #define NETC_PORT_GIG_RF_RESET_MASK(p) (0x1 << \
479 NETC_PORT_GIG_RF_RESET_OFFS(p))
480 #define NETCOMP_CONTROL_0_REG 0x120
481 #define NETC_GBE_PORT0_SGMII_MODE_OFFS 0
482 #define NETC_GBE_PORT0_SGMII_MODE_MASK (0x1 << \
483 NETC_GBE_PORT0_SGMII_MODE_OFFS)
484 #define NETC_GBE_PORT1_SGMII_MODE_OFFS 1
485 #define NETC_GBE_PORT1_SGMII_MODE_MASK (0x1 << \
486 NETC_GBE_PORT1_SGMII_MODE_OFFS)
487 #define NETC_GBE_PORT1_MII_MODE_OFFS 2
488 #define NETC_GBE_PORT1_MII_MODE_MASK (0x1 << \
489 NETC_GBE_PORT1_MII_MODE_OFFS)
491 #define MVPP22_SMI_MISC_CFG_REG (MVPP22_SMI + 0x04)
492 #define MVPP22_SMI_POLLING_EN BIT(10)
494 #define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \
497 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
499 /* Descriptor ring Macros */
500 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
501 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
503 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
504 #define MVPP21_SMI 0x0054
505 /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
506 #define MVPP22_SMI 0x1200
507 #define MVPP2_PHY_REG_MASK 0x1f
508 /* SMI register fields */
509 #define MVPP2_SMI_DATA_OFFS 0 /* Data */
510 #define MVPP2_SMI_DATA_MASK (0xffff << MVPP2_SMI_DATA_OFFS)
511 #define MVPP2_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
512 #define MVPP2_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
513 #define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
514 #define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS)
515 #define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid */
516 #define MVPP2_SMI_BUSY (1 << 28) /* Busy */
518 #define MVPP2_PHY_ADDR_MASK 0x1f
519 #define MVPP2_PHY_REG_MASK 0x1f
521 /* Additional PPv2.2 offsets */
522 #define MVPP22_MPCS 0x007000
523 #define MVPP22_XPCS 0x007400
524 #define MVPP22_PORT_BASE 0x007e00
525 #define MVPP22_PORT_OFFSET 0x001000
526 #define MVPP22_RFU1 0x318000
528 /* Maximum number of ports */
529 #define MVPP22_GOP_MAC_NUM 4
531 /* Sets the field located at the specified in data */
532 #define MVPP2_RGMII_TX_FIFO_MIN_TH 0x41
533 #define MVPP2_SGMII_TX_FIFO_MIN_TH 0x5
534 #define MVPP2_SGMII2_5_TX_FIFO_MIN_TH 0xb
537 enum mv_netc_topology {
538 MV_NETC_GE_MAC2_SGMII = BIT(0),
539 MV_NETC_GE_MAC3_SGMII = BIT(1),
540 MV_NETC_GE_MAC3_RGMII = BIT(2),
545 MV_NETC_SECOND_PHASE,
548 enum mv_netc_sgmii_xmi_mode {
553 enum mv_netc_mii_mode {
563 /* Various constants */
566 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
567 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
568 #define MVPP2_RX_COAL_PKTS 32
569 #define MVPP2_RX_COAL_USEC 100
571 /* The two bytes Marvell header. Either contains a special value used
572 * by Marvell switches when a specific hardware mode is enabled (not
573 * supported by this driver) or is filled automatically by zeroes on
574 * the RX side. Those two bytes being at the front of the Ethernet
575 * header, they allow to have the IP header aligned on a 4 bytes
576 * boundary automatically: the hardware skips those two bytes on its
579 #define MVPP2_MH_SIZE 2
580 #define MVPP2_ETH_TYPE_LEN 2
581 #define MVPP2_PPPOE_HDR_SIZE 8
582 #define MVPP2_VLAN_TAG_LEN 4
584 /* Lbtd 802.3 type */
585 #define MVPP2_IP_LBDT_TYPE 0xfffa
587 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
588 #define MVPP2_TX_CSUM_MAX_SIZE 9800
590 /* Timeout constants */
591 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
592 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
594 #define MVPP2_TX_MTU_MAX 0x7ffff
596 /* Maximum number of T-CONTs of PON port */
597 #define MVPP2_MAX_TCONT 16
599 /* Maximum number of supported ports */
600 #define MVPP2_MAX_PORTS 4
602 /* Maximum number of TXQs used by single port */
603 #define MVPP2_MAX_TXQ 8
605 /* Default number of TXQs in use */
606 #define MVPP2_DEFAULT_TXQ 1
608 /* Dfault number of RXQs in use */
609 #define MVPP2_DEFAULT_RXQ 1
610 #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
612 /* Max number of Rx descriptors */
613 #define MVPP2_MAX_RXD 16
615 /* Max number of Tx descriptors */
616 #define MVPP2_MAX_TXD 16
618 /* Amount of Tx descriptors that can be reserved at once by CPU */
619 #define MVPP2_CPU_DESC_CHUNK 64
621 /* Max number of Tx descriptors in each aggregated queue */
622 #define MVPP2_AGGR_TXQ_SIZE 256
624 /* Descriptor aligned size */
625 #define MVPP2_DESC_ALIGNED_SIZE 32
627 /* Descriptor alignment mask */
628 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
630 /* RX FIFO constants */
631 #define MVPP21_RX_FIFO_PORT_DATA_SIZE 0x2000
632 #define MVPP21_RX_FIFO_PORT_ATTR_SIZE 0x80
633 #define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE 0x8000
634 #define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE 0x2000
635 #define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE 0x1000
636 #define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE 0x200
637 #define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE 0x80
638 #define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE 0x40
639 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
641 /* TX general registers */
642 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2))
643 #define MVPP22_TX_FIFO_SIZE_MASK 0xf
645 /* TX FIFO constants */
646 #define MVPP2_TX_FIFO_DATA_SIZE_10KB 0xa
647 #define MVPP2_TX_FIFO_DATA_SIZE_3KB 0x3
649 /* RX buffer constants */
650 #define MVPP2_SKB_SHINFO_SIZE \
653 #define MVPP2_RX_PKT_SIZE(mtu) \
654 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
655 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
657 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
658 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
659 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
660 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
662 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
664 /* IPv6 max L3 address size */
665 #define MVPP2_MAX_L3_ADDR_SIZE 16
668 #define MVPP2_F_LOOPBACK BIT(0)
670 /* Marvell tag types */
671 enum mvpp2_tag_type {
672 MVPP2_TAG_TYPE_NONE = 0,
673 MVPP2_TAG_TYPE_MH = 1,
674 MVPP2_TAG_TYPE_DSA = 2,
675 MVPP2_TAG_TYPE_EDSA = 3,
676 MVPP2_TAG_TYPE_VLAN = 4,
677 MVPP2_TAG_TYPE_LAST = 5
680 /* Parser constants */
681 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
682 #define MVPP2_PRS_TCAM_WORDS 6
683 #define MVPP2_PRS_SRAM_WORDS 4
684 #define MVPP2_PRS_FLOW_ID_SIZE 64
685 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
686 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
687 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
688 #define MVPP2_PRS_IPV4_HEAD 0x40
689 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
690 #define MVPP2_PRS_IPV4_MC 0xe0
691 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
692 #define MVPP2_PRS_IPV4_BC_MASK 0xff
693 #define MVPP2_PRS_IPV4_IHL 0x5
694 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
695 #define MVPP2_PRS_IPV6_MC 0xff
696 #define MVPP2_PRS_IPV6_MC_MASK 0xff
697 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
698 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
699 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
700 #define MVPP2_PRS_DBL_VLANS_MAX 100
703 * - lookup ID - 4 bits
705 * - additional information - 1 byte
706 * - header data - 8 bytes
707 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
709 #define MVPP2_PRS_AI_BITS 8
710 #define MVPP2_PRS_PORT_MASK 0xff
711 #define MVPP2_PRS_LU_MASK 0xf
712 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
713 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
714 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
715 (((offs) * 2) - ((offs) % 2) + 2)
716 #define MVPP2_PRS_TCAM_AI_BYTE 16
717 #define MVPP2_PRS_TCAM_PORT_BYTE 17
718 #define MVPP2_PRS_TCAM_LU_BYTE 20
719 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
720 #define MVPP2_PRS_TCAM_INV_WORD 5
721 /* Tcam entries ID */
722 #define MVPP2_PE_DROP_ALL 0
723 #define MVPP2_PE_FIRST_FREE_TID 1
724 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
725 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
726 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
727 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
728 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
729 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
730 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
731 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
732 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
733 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
734 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
735 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
736 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
737 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
738 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
739 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
740 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
741 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
742 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
743 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
744 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
745 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
746 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
747 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
748 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
751 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
753 #define MVPP2_PRS_SRAM_RI_OFFS 0
754 #define MVPP2_PRS_SRAM_RI_WORD 0
755 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
756 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
757 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
758 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
759 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
760 #define MVPP2_PRS_SRAM_UDF_OFFS 73
761 #define MVPP2_PRS_SRAM_UDF_BITS 8
762 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
763 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
764 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
765 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
766 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
767 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
768 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
769 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
770 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
771 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
772 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
773 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
774 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
775 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
776 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
777 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
778 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
779 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
780 #define MVPP2_PRS_SRAM_AI_OFFS 90
781 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
782 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
783 #define MVPP2_PRS_SRAM_AI_MASK 0xff
784 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
785 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
786 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
787 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
789 /* Sram result info bits assignment */
790 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
791 #define MVPP2_PRS_RI_DSA_MASK 0x2
792 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
793 #define MVPP2_PRS_RI_VLAN_NONE 0x0
794 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
795 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
796 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
797 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
798 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
799 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
800 #define MVPP2_PRS_RI_L2_UCAST 0x0
801 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
802 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
803 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
804 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
805 #define MVPP2_PRS_RI_L3_UN 0x0
806 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
807 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
808 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
809 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
810 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
811 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
812 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
813 #define MVPP2_PRS_RI_L3_UCAST 0x0
814 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
815 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
816 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
817 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
818 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
819 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
820 #define MVPP2_PRS_RI_L4_TCP BIT(22)
821 #define MVPP2_PRS_RI_L4_UDP BIT(23)
822 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
823 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
824 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
825 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
827 /* Sram additional info bits assignment */
828 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
829 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
830 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
831 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
832 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
833 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
834 #define MVPP2_PRS_SINGLE_VLAN_AI 0
835 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
838 #define MVPP2_PRS_TAGGED true
839 #define MVPP2_PRS_UNTAGGED false
840 #define MVPP2_PRS_EDSA true
841 #define MVPP2_PRS_DSA false
843 /* MAC entries, shadow udf */
845 MVPP2_PRS_UDF_MAC_DEF,
846 MVPP2_PRS_UDF_MAC_RANGE,
847 MVPP2_PRS_UDF_L2_DEF,
848 MVPP2_PRS_UDF_L2_DEF_COPY,
849 MVPP2_PRS_UDF_L2_USER,
853 enum mvpp2_prs_lookup {
867 enum mvpp2_prs_l3_cast {
868 MVPP2_PRS_L3_UNI_CAST,
869 MVPP2_PRS_L3_MULTI_CAST,
870 MVPP2_PRS_L3_BROAD_CAST
873 /* Classifier constants */
874 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
875 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
876 #define MVPP2_CLS_LKP_TBL_SIZE 64
879 #define MVPP2_BM_POOLS_NUM 1
880 #define MVPP2_BM_LONG_BUF_NUM 16
881 #define MVPP2_BM_SHORT_BUF_NUM 16
882 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
883 #define MVPP2_BM_POOL_PTR_ALIGN 128
884 #define MVPP2_BM_SWF_LONG_POOL(port) 0
886 /* BM cookie (32 bits) definition */
887 #define MVPP2_BM_COOKIE_POOL_OFFS 8
888 #define MVPP2_BM_COOKIE_CPU_OFFS 24
890 /* BM short pool packet size
891 * These value assure that for SWF the total number
892 * of bytes allocated for each buffer will be 512
894 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
904 /* Shared Packet Processor resources */
906 /* Shared registers' base addresses */
908 void __iomem *lms_base;
909 void __iomem *iface_base;
910 void __iomem *mdio_base;
912 void __iomem *mpcs_base;
913 void __iomem *xpcs_base;
914 void __iomem *rfu1_base;
918 /* List of pointers to port structures */
919 struct mvpp2_port **port_list;
921 /* Aggregated TXQs */
922 struct mvpp2_tx_queue *aggr_txqs;
925 struct mvpp2_bm_pool *bm_pools;
927 /* PRS shadow table */
928 struct mvpp2_prs_shadow *prs_shadow;
929 /* PRS auxiliary table for double vlan entries control */
930 bool *prs_double_vlans;
936 enum { MVPP21, MVPP22 } hw_version;
938 /* Maximum number of RXQs per port */
939 unsigned int max_port_rxqs;
946 struct mvpp2_pcpu_stats {
956 /* Index of the port from the "group of ports" complex point
965 /* Per-port registers' base address */
968 struct mvpp2_rx_queue **rxqs;
969 struct mvpp2_tx_queue **txqs;
973 u32 pending_cause_rx;
975 /* Per-CPU port control */
976 struct mvpp2_port_pcpu __percpu *pcpu;
983 struct mvpp2_pcpu_stats __percpu *stats;
985 struct phy_device *phy_dev;
986 phy_interface_t phy_interface;
989 #ifdef CONFIG_DM_GPIO
990 struct gpio_desc phy_reset_gpio;
991 struct gpio_desc phy_tx_disable_gpio;
998 unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */
1000 struct mvpp2_bm_pool *pool_long;
1001 struct mvpp2_bm_pool *pool_short;
1003 /* Index of first port's physical RXQ */
1006 u8 dev_addr[ETH_ALEN];
1009 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
1010 * layout of the transmit and reception DMA descriptors, and their
1011 * layout is therefore defined by the hardware design
1014 #define MVPP2_TXD_L3_OFF_SHIFT 0
1015 #define MVPP2_TXD_IP_HLEN_SHIFT 8
1016 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
1017 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
1018 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
1019 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
1020 #define MVPP2_TXD_L4_UDP BIT(24)
1021 #define MVPP2_TXD_L3_IP6 BIT(26)
1022 #define MVPP2_TXD_L_DESC BIT(28)
1023 #define MVPP2_TXD_F_DESC BIT(29)
1025 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
1026 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
1027 #define MVPP2_RXD_ERR_CRC 0x0
1028 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
1029 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
1030 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
1031 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
1032 #define MVPP2_RXD_HWF_SYNC BIT(21)
1033 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
1034 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
1035 #define MVPP2_RXD_L4_TCP BIT(25)
1036 #define MVPP2_RXD_L4_UDP BIT(26)
1037 #define MVPP2_RXD_L3_IP4 BIT(28)
1038 #define MVPP2_RXD_L3_IP6 BIT(30)
1039 #define MVPP2_RXD_BUF_HDR BIT(31)
1041 /* HW TX descriptor for PPv2.1 */
1042 struct mvpp21_tx_desc {
1043 u32 command; /* Options used by HW for packet transmitting.*/
1044 u8 packet_offset; /* the offset from the buffer beginning */
1045 u8 phys_txq; /* destination queue ID */
1046 u16 data_size; /* data size of transmitted packet in bytes */
1047 u32 buf_dma_addr; /* physical addr of transmitted buffer */
1048 u32 buf_cookie; /* cookie for access to TX buffer in tx path */
1049 u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
1050 u32 reserved2; /* reserved (for future use) */
1053 /* HW RX descriptor for PPv2.1 */
1054 struct mvpp21_rx_desc {
1055 u32 status; /* info about received packet */
1056 u16 reserved1; /* parser_info (for future use, PnC) */
1057 u16 data_size; /* size of received packet in bytes */
1058 u32 buf_dma_addr; /* physical address of the buffer */
1059 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
1060 u16 reserved2; /* gem_port_id (for future use, PON) */
1061 u16 reserved3; /* csum_l4 (for future use, PnC) */
1062 u8 reserved4; /* bm_qset (for future use, BM) */
1064 u16 reserved6; /* classify_info (for future use, PnC) */
1065 u32 reserved7; /* flow_id (for future use, PnC) */
1069 /* HW TX descriptor for PPv2.2 */
1070 struct mvpp22_tx_desc {
1076 u64 buf_dma_addr_ptp;
1077 u64 buf_cookie_misc;
1080 /* HW RX descriptor for PPv2.2 */
1081 struct mvpp22_rx_desc {
1087 u64 buf_dma_addr_key_hash;
1088 u64 buf_cookie_misc;
1091 /* Opaque type used by the driver to manipulate the HW TX and RX
1094 struct mvpp2_tx_desc {
1096 struct mvpp21_tx_desc pp21;
1097 struct mvpp22_tx_desc pp22;
1101 struct mvpp2_rx_desc {
1103 struct mvpp21_rx_desc pp21;
1104 struct mvpp22_rx_desc pp22;
1108 /* Per-CPU Tx queue control */
1109 struct mvpp2_txq_pcpu {
1112 /* Number of Tx DMA descriptors in the descriptor ring */
1115 /* Number of currently used Tx DMA descriptor in the
1120 /* Number of Tx DMA descriptors reserved for each CPU */
1123 /* Index of last TX DMA descriptor that was inserted */
1126 /* Index of the TX DMA descriptor to be cleaned up */
1130 struct mvpp2_tx_queue {
1131 /* Physical number of this Tx queue */
1134 /* Logical number of this Tx queue */
1137 /* Number of Tx DMA descriptors in the descriptor ring */
1140 /* Number of currently used Tx DMA descriptor in the descriptor ring */
1143 /* Per-CPU control of physical Tx queues */
1144 struct mvpp2_txq_pcpu __percpu *pcpu;
1148 /* Virtual address of thex Tx DMA descriptors array */
1149 struct mvpp2_tx_desc *descs;
1151 /* DMA address of the Tx DMA descriptors array */
1152 dma_addr_t descs_dma;
1154 /* Index of the last Tx DMA descriptor */
1157 /* Index of the next Tx DMA descriptor to process */
1158 int next_desc_to_proc;
1161 struct mvpp2_rx_queue {
1162 /* RX queue number, in the range 0-31 for physical RXQs */
1165 /* Num of rx descriptors in the rx descriptor ring */
1171 /* Virtual address of the RX DMA descriptors array */
1172 struct mvpp2_rx_desc *descs;
1174 /* DMA address of the RX DMA descriptors array */
1175 dma_addr_t descs_dma;
1177 /* Index of the last RX DMA descriptor */
1180 /* Index of the next RX DMA descriptor to process */
1181 int next_desc_to_proc;
1183 /* ID of port to which physical RXQ is mapped */
1186 /* Port's logic RXQ number to which physical RXQ is mapped */
1190 union mvpp2_prs_tcam_entry {
1191 u32 word[MVPP2_PRS_TCAM_WORDS];
1192 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
1195 union mvpp2_prs_sram_entry {
1196 u32 word[MVPP2_PRS_SRAM_WORDS];
1197 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
1200 struct mvpp2_prs_entry {
1202 union mvpp2_prs_tcam_entry tcam;
1203 union mvpp2_prs_sram_entry sram;
1206 struct mvpp2_prs_shadow {
1213 /* User defined offset */
1221 struct mvpp2_cls_flow_entry {
1223 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
1226 struct mvpp2_cls_lookup_entry {
1232 struct mvpp2_bm_pool {
1233 /* Pool number in the range 0-7 */
1235 enum mvpp2_bm_type type;
1237 /* Buffer Pointers Pool External (BPPE) size */
1239 /* Number of buffers for this pool */
1241 /* Pool buffer size */
1246 /* BPPE virtual base address */
1247 unsigned long *virt_addr;
1248 /* BPPE DMA base address */
1249 dma_addr_t dma_addr;
1251 /* Ports using BM pool */
1255 /* Static declaractions */
1257 /* Number of RXQs used by single port */
1258 static int rxq_number = MVPP2_DEFAULT_RXQ;
1259 /* Number of TXQs used by single port */
1260 static int txq_number = MVPP2_DEFAULT_TXQ;
1264 #define MVPP2_DRIVER_NAME "mvpp2"
1265 #define MVPP2_DRIVER_VERSION "1.0"
1268 * U-Boot internal data, mostly uncached buffers for descriptors and data
1270 struct buffer_location {
1271 struct mvpp2_tx_desc *aggr_tx_descs;
1272 struct mvpp2_tx_desc *tx_descs;
1273 struct mvpp2_rx_desc *rx_descs;
1274 unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
1275 unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
1280 * All 4 interfaces use the same global buffer, since only one interface
1281 * can be enabled at once
1283 static struct buffer_location buffer_loc;
1286 * Page table entries are set to 1MB, or multiples of 1MB
1287 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
1289 #define BD_SPACE (1 << 20)
1291 /* Utility/helper methods */
1293 static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
1295 writel(data, priv->base + offset);
1298 static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
1300 return readl(priv->base + offset);
1303 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
1304 struct mvpp2_tx_desc *tx_desc,
1305 dma_addr_t dma_addr)
1307 if (port->priv->hw_version == MVPP21) {
1308 tx_desc->pp21.buf_dma_addr = dma_addr;
1310 u64 val = (u64)dma_addr;
1312 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
1313 tx_desc->pp22.buf_dma_addr_ptp |= val;
1317 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
1318 struct mvpp2_tx_desc *tx_desc,
1321 if (port->priv->hw_version == MVPP21)
1322 tx_desc->pp21.data_size = size;
1324 tx_desc->pp22.data_size = size;
1327 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
1328 struct mvpp2_tx_desc *tx_desc,
1331 if (port->priv->hw_version == MVPP21)
1332 tx_desc->pp21.phys_txq = txq;
1334 tx_desc->pp22.phys_txq = txq;
1337 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
1338 struct mvpp2_tx_desc *tx_desc,
1339 unsigned int command)
1341 if (port->priv->hw_version == MVPP21)
1342 tx_desc->pp21.command = command;
1344 tx_desc->pp22.command = command;
1347 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
1348 struct mvpp2_tx_desc *tx_desc,
1349 unsigned int offset)
1351 if (port->priv->hw_version == MVPP21)
1352 tx_desc->pp21.packet_offset = offset;
1354 tx_desc->pp22.packet_offset = offset;
1357 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
1358 struct mvpp2_rx_desc *rx_desc)
1360 if (port->priv->hw_version == MVPP21)
1361 return rx_desc->pp21.buf_dma_addr;
1363 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
1366 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
1367 struct mvpp2_rx_desc *rx_desc)
1369 if (port->priv->hw_version == MVPP21)
1370 return rx_desc->pp21.buf_cookie;
1372 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
1375 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
1376 struct mvpp2_rx_desc *rx_desc)
1378 if (port->priv->hw_version == MVPP21)
1379 return rx_desc->pp21.data_size;
1381 return rx_desc->pp22.data_size;
1384 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
1385 struct mvpp2_rx_desc *rx_desc)
1387 if (port->priv->hw_version == MVPP21)
1388 return rx_desc->pp21.status;
1390 return rx_desc->pp22.status;
1393 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
1395 txq_pcpu->txq_get_index++;
1396 if (txq_pcpu->txq_get_index == txq_pcpu->size)
1397 txq_pcpu->txq_get_index = 0;
1400 /* Get number of physical egress port */
1401 static inline int mvpp2_egress_port(struct mvpp2_port *port)
1403 return MVPP2_MAX_TCONT + port->id;
1406 /* Get number of physical TXQ */
1407 static inline int mvpp2_txq_phys(int port, int txq)
1409 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
1412 /* Parser configuration routines */
1414 /* Update parser tcam and sram hw entries */
1415 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1419 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1422 /* Clear entry invalidation bit */
1423 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1425 /* Write tcam index - indirect access */
1426 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1427 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1428 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1430 /* Write sram index - indirect access */
1431 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1432 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1433 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1438 /* Read tcam entry from hw */
1439 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1443 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1446 /* Write tcam index - indirect access */
1447 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1449 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1450 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1451 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1452 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1454 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1455 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1457 /* Write sram index - indirect access */
1458 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1459 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1460 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1465 /* Invalidate tcam hw entry */
1466 static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1468 /* Write index - indirect access */
1469 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1470 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1471 MVPP2_PRS_TCAM_INV_MASK);
1474 /* Enable shadow table entry and set its lookup ID */
1475 static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1477 priv->prs_shadow[index].valid = true;
1478 priv->prs_shadow[index].lu = lu;
1481 /* Update ri fields in shadow table entry */
1482 static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1483 unsigned int ri, unsigned int ri_mask)
1485 priv->prs_shadow[index].ri_mask = ri_mask;
1486 priv->prs_shadow[index].ri = ri;
1489 /* Update lookup field in tcam sw entry */
1490 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1492 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1494 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1495 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1498 /* Update mask for single port in tcam sw entry */
1499 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1500 unsigned int port, bool add)
1502 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1505 pe->tcam.byte[enable_off] &= ~(1 << port);
1507 pe->tcam.byte[enable_off] |= 1 << port;
1510 /* Update port map in tcam sw entry */
1511 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1514 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1515 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1517 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1518 pe->tcam.byte[enable_off] &= ~port_mask;
1519 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1522 /* Obtain port map from tcam sw entry */
1523 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1525 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1527 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1530 /* Set byte of data and its enable bits in tcam sw entry */
1531 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1532 unsigned int offs, unsigned char byte,
1533 unsigned char enable)
1535 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1536 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1539 /* Get byte of data and its enable bits from tcam sw entry */
1540 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1541 unsigned int offs, unsigned char *byte,
1542 unsigned char *enable)
1544 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1545 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1548 /* Set ethertype in tcam sw entry */
1549 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1550 unsigned short ethertype)
1552 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1553 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1556 /* Set bits in sram sw entry */
1557 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1560 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1563 /* Clear bits in sram sw entry */
1564 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1567 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1570 /* Update ri bits in sram sw entry */
1571 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1572 unsigned int bits, unsigned int mask)
1576 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1577 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1579 if (!(mask & BIT(i)))
1583 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1585 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1587 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1591 /* Update ai bits in sram sw entry */
1592 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1593 unsigned int bits, unsigned int mask)
1596 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1598 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1600 if (!(mask & BIT(i)))
1604 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1606 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1608 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1612 /* Read ai bits from sram sw entry */
1613 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1616 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1617 int ai_en_off = ai_off + 1;
1618 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1620 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1621 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1626 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1629 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1632 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1634 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1635 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1636 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1639 /* In the sram sw entry set sign and value of the next lookup offset
1640 * and the offset value generated to the classifier
1642 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1647 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1650 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1654 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1655 (unsigned char)shift;
1657 /* Reset and set operation */
1658 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1659 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1660 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1662 /* Set base offset as current */
1663 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1666 /* In the sram sw entry set sign and value of the user defined offset
1667 * generated to the classifier
1669 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1670 unsigned int type, int offset,
1675 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1676 offset = 0 - offset;
1678 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1682 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1683 MVPP2_PRS_SRAM_UDF_MASK);
1684 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1685 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1686 MVPP2_PRS_SRAM_UDF_BITS)] &=
1687 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1688 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1689 MVPP2_PRS_SRAM_UDF_BITS)] |=
1690 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1692 /* Set offset type */
1693 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1694 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1695 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1697 /* Set offset operation */
1698 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1699 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1700 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1702 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1703 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1704 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1705 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1707 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1708 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1709 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1711 /* Set base offset as current */
1712 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1715 /* Find parser flow entry */
1716 static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1718 struct mvpp2_prs_entry *pe;
1721 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1724 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1726 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1727 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1730 if (!priv->prs_shadow[tid].valid ||
1731 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1735 mvpp2_prs_hw_read(priv, pe);
1736 bits = mvpp2_prs_sram_ai_get(pe);
1738 /* Sram store classification lookup ID in AI bits [5:0] */
1739 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1747 /* Return first free tcam index, seeking from start to end */
1748 static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1756 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1757 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1759 for (tid = start; tid <= end; tid++) {
1760 if (!priv->prs_shadow[tid].valid)
1767 /* Enable/disable dropping all mac da's */
1768 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1770 struct mvpp2_prs_entry pe;
1772 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1773 /* Entry exist - update port only */
1774 pe.index = MVPP2_PE_DROP_ALL;
1775 mvpp2_prs_hw_read(priv, &pe);
1777 /* Entry doesn't exist - create new */
1778 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1779 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1780 pe.index = MVPP2_PE_DROP_ALL;
1782 /* Non-promiscuous mode for all ports - DROP unknown packets */
1783 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1784 MVPP2_PRS_RI_DROP_MASK);
1786 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1787 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1789 /* Update shadow table */
1790 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1792 /* Mask all ports */
1793 mvpp2_prs_tcam_port_map_set(&pe, 0);
1796 /* Update port mask */
1797 mvpp2_prs_tcam_port_set(&pe, port, add);
1799 mvpp2_prs_hw_write(priv, &pe);
1802 /* Set port to promiscuous mode */
1803 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1805 struct mvpp2_prs_entry pe;
1807 /* Promiscuous mode - Accept unknown packets */
1809 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1810 /* Entry exist - update port only */
1811 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1812 mvpp2_prs_hw_read(priv, &pe);
1814 /* Entry doesn't exist - create new */
1815 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1816 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1817 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1819 /* Continue - set next lookup */
1820 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1822 /* Set result info bits */
1823 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1824 MVPP2_PRS_RI_L2_CAST_MASK);
1826 /* Shift to ethertype */
1827 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1828 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1830 /* Mask all ports */
1831 mvpp2_prs_tcam_port_map_set(&pe, 0);
1833 /* Update shadow table */
1834 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1837 /* Update port mask */
1838 mvpp2_prs_tcam_port_set(&pe, port, add);
1840 mvpp2_prs_hw_write(priv, &pe);
1843 /* Accept multicast */
1844 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1847 struct mvpp2_prs_entry pe;
1848 unsigned char da_mc;
1850 /* Ethernet multicast address first byte is
1851 * 0x01 for IPv4 and 0x33 for IPv6
1853 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1855 if (priv->prs_shadow[index].valid) {
1856 /* Entry exist - update port only */
1858 mvpp2_prs_hw_read(priv, &pe);
1860 /* Entry doesn't exist - create new */
1861 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1862 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1865 /* Continue - set next lookup */
1866 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1868 /* Set result info bits */
1869 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1870 MVPP2_PRS_RI_L2_CAST_MASK);
1872 /* Update tcam entry data first byte */
1873 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1875 /* Shift to ethertype */
1876 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1877 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1879 /* Mask all ports */
1880 mvpp2_prs_tcam_port_map_set(&pe, 0);
1882 /* Update shadow table */
1883 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1886 /* Update port mask */
1887 mvpp2_prs_tcam_port_set(&pe, port, add);
1889 mvpp2_prs_hw_write(priv, &pe);
1892 /* Parser per-port initialization */
1893 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
1894 int lu_max, int offset)
1899 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
1900 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
1901 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
1902 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
1904 /* Set maximum number of loops for packet received from port */
1905 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
1906 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
1907 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
1908 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
1910 /* Set initial offset for packet header extraction for the first
1913 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
1914 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
1915 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
1916 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
1919 /* Default flow entries initialization for all ports */
1920 static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
1922 struct mvpp2_prs_entry pe;
1925 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
1926 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1927 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1928 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
1930 /* Mask all ports */
1931 mvpp2_prs_tcam_port_map_set(&pe, 0);
1934 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
1935 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
1937 /* Update shadow table and hw entry */
1938 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
1939 mvpp2_prs_hw_write(priv, &pe);
1943 /* Set default entry for Marvell Header field */
1944 static void mvpp2_prs_mh_init(struct mvpp2 *priv)
1946 struct mvpp2_prs_entry pe;
1948 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1950 pe.index = MVPP2_PE_MH_DEFAULT;
1951 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1952 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1953 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1954 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
1956 /* Unmask all ports */
1957 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1959 /* Update shadow table and hw entry */
1960 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1961 mvpp2_prs_hw_write(priv, &pe);
1964 /* Set default entires (place holder) for promiscuous, non-promiscuous and
1965 * multicast MAC addresses
1967 static void mvpp2_prs_mac_init(struct mvpp2 *priv)
1969 struct mvpp2_prs_entry pe;
1971 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1973 /* Non-promiscuous mode for all ports - DROP unknown packets */
1974 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
1975 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1977 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1978 MVPP2_PRS_RI_DROP_MASK);
1979 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1980 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1982 /* Unmask all ports */
1983 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1985 /* Update shadow table and hw entry */
1986 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1987 mvpp2_prs_hw_write(priv, &pe);
1989 /* place holders only - no ports */
1990 mvpp2_prs_mac_drop_all_set(priv, 0, false);
1991 mvpp2_prs_mac_promisc_set(priv, 0, false);
1992 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
1993 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
1996 /* Match basic ethertypes */
1997 static int mvpp2_prs_etype_init(struct mvpp2 *priv)
1999 struct mvpp2_prs_entry pe;
2002 /* Ethertype: PPPoE */
2003 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2004 MVPP2_PE_LAST_FREE_TID);
2008 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2009 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2012 mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
2014 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
2015 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2016 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
2017 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
2018 MVPP2_PRS_RI_PPPOE_MASK);
2020 /* Update shadow table and hw entry */
2021 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2022 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2023 priv->prs_shadow[pe.index].finish = false;
2024 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
2025 MVPP2_PRS_RI_PPPOE_MASK);
2026 mvpp2_prs_hw_write(priv, &pe);
2028 /* Ethertype: ARP */
2029 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2030 MVPP2_PE_LAST_FREE_TID);
2034 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2035 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2038 mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
2040 /* Generate flow in the next iteration*/
2041 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2042 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2043 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
2044 MVPP2_PRS_RI_L3_PROTO_MASK);
2046 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2048 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2050 /* Update shadow table and hw entry */
2051 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2052 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2053 priv->prs_shadow[pe.index].finish = true;
2054 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
2055 MVPP2_PRS_RI_L3_PROTO_MASK);
2056 mvpp2_prs_hw_write(priv, &pe);
2058 /* Ethertype: LBTD */
2059 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2060 MVPP2_PE_LAST_FREE_TID);
2064 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2065 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2068 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
2070 /* Generate flow in the next iteration*/
2071 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2072 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2073 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2074 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2075 MVPP2_PRS_RI_CPU_CODE_MASK |
2076 MVPP2_PRS_RI_UDF3_MASK);
2078 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2080 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2082 /* Update shadow table and hw entry */
2083 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2084 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2085 priv->prs_shadow[pe.index].finish = true;
2086 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2087 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2088 MVPP2_PRS_RI_CPU_CODE_MASK |
2089 MVPP2_PRS_RI_UDF3_MASK);
2090 mvpp2_prs_hw_write(priv, &pe);
2092 /* Ethertype: IPv4 without options */
2093 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2094 MVPP2_PE_LAST_FREE_TID);
2098 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2099 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2102 mvpp2_prs_match_etype(&pe, 0, PROT_IP);
2103 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2104 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
2105 MVPP2_PRS_IPV4_HEAD_MASK |
2106 MVPP2_PRS_IPV4_IHL_MASK);
2108 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2109 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
2110 MVPP2_PRS_RI_L3_PROTO_MASK);
2111 /* Skip eth_type + 4 bytes of IP header */
2112 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
2113 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2115 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2117 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2119 /* Update shadow table and hw entry */
2120 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2121 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2122 priv->prs_shadow[pe.index].finish = false;
2123 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
2124 MVPP2_PRS_RI_L3_PROTO_MASK);
2125 mvpp2_prs_hw_write(priv, &pe);
2127 /* Ethertype: IPv4 with options */
2128 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2129 MVPP2_PE_LAST_FREE_TID);
2135 /* Clear tcam data before updating */
2136 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
2137 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
2139 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2140 MVPP2_PRS_IPV4_HEAD,
2141 MVPP2_PRS_IPV4_HEAD_MASK);
2143 /* Clear ri before updating */
2144 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
2145 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
2146 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
2147 MVPP2_PRS_RI_L3_PROTO_MASK);
2149 /* Update shadow table and hw entry */
2150 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2151 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2152 priv->prs_shadow[pe.index].finish = false;
2153 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
2154 MVPP2_PRS_RI_L3_PROTO_MASK);
2155 mvpp2_prs_hw_write(priv, &pe);
2157 /* Ethertype: IPv6 without options */
2158 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2159 MVPP2_PE_LAST_FREE_TID);
2163 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2164 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2167 mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
2169 /* Skip DIP of IPV6 header */
2170 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
2171 MVPP2_MAX_L3_ADDR_SIZE,
2172 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2173 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2174 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
2175 MVPP2_PRS_RI_L3_PROTO_MASK);
2177 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2179 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2181 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2182 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2183 priv->prs_shadow[pe.index].finish = false;
2184 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
2185 MVPP2_PRS_RI_L3_PROTO_MASK);
2186 mvpp2_prs_hw_write(priv, &pe);
2188 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
2189 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2190 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2191 pe.index = MVPP2_PE_ETH_TYPE_UN;
2193 /* Unmask all ports */
2194 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2196 /* Generate flow in the next iteration*/
2197 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2198 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2199 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2200 MVPP2_PRS_RI_L3_PROTO_MASK);
2201 /* Set L3 offset even it's unknown L3 */
2202 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2204 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2206 /* Update shadow table and hw entry */
2207 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2208 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2209 priv->prs_shadow[pe.index].finish = true;
2210 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
2211 MVPP2_PRS_RI_L3_PROTO_MASK);
2212 mvpp2_prs_hw_write(priv, &pe);
2217 /* Parser default initialization */
2218 static int mvpp2_prs_default_init(struct udevice *dev,
2223 /* Enable tcam table */
2224 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
2226 /* Clear all tcam and sram entries */
2227 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
2228 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
2229 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
2230 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
2232 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
2233 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
2234 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
2237 /* Invalidate all tcam entries */
2238 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
2239 mvpp2_prs_hw_inv(priv, index);
2241 priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
2242 sizeof(struct mvpp2_prs_shadow),
2244 if (!priv->prs_shadow)
2247 /* Always start from lookup = 0 */
2248 for (index = 0; index < MVPP2_MAX_PORTS; index++)
2249 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
2250 MVPP2_PRS_PORT_LU_MAX, 0);
2252 mvpp2_prs_def_flow_init(priv);
2254 mvpp2_prs_mh_init(priv);
2256 mvpp2_prs_mac_init(priv);
2258 err = mvpp2_prs_etype_init(priv);
2265 /* Compare MAC DA with tcam entry data */
2266 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2267 const u8 *da, unsigned char *mask)
2269 unsigned char tcam_byte, tcam_mask;
2272 for (index = 0; index < ETH_ALEN; index++) {
2273 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2274 if (tcam_mask != mask[index])
2277 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
2284 /* Find tcam entry with matched pair <MAC DA, port> */
2285 static struct mvpp2_prs_entry *
2286 mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
2287 unsigned char *mask, int udf_type)
2289 struct mvpp2_prs_entry *pe;
2292 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2295 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2297 /* Go through the all entires with MVPP2_PRS_LU_MAC */
2298 for (tid = MVPP2_PE_FIRST_FREE_TID;
2299 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
2300 unsigned int entry_pmap;
2302 if (!priv->prs_shadow[tid].valid ||
2303 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
2304 (priv->prs_shadow[tid].udf != udf_type))
2308 mvpp2_prs_hw_read(priv, pe);
2309 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
2311 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
2320 /* Update parser's mac da entry */
2321 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
2322 const u8 *da, bool add)
2324 struct mvpp2_prs_entry *pe;
2325 unsigned int pmap, len, ri;
2326 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2329 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
2330 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
2331 MVPP2_PRS_UDF_MAC_DEF);
2338 /* Create new TCAM entry */
2339 /* Find first range mac entry*/
2340 for (tid = MVPP2_PE_FIRST_FREE_TID;
2341 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
2342 if (priv->prs_shadow[tid].valid &&
2343 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
2344 (priv->prs_shadow[tid].udf ==
2345 MVPP2_PRS_UDF_MAC_RANGE))
2348 /* Go through the all entries from first to last */
2349 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2354 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2357 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2360 /* Mask all ports */
2361 mvpp2_prs_tcam_port_map_set(pe, 0);
2364 /* Update port mask */
2365 mvpp2_prs_tcam_port_set(pe, port, add);
2367 /* Invalidate the entry if no ports are left enabled */
2368 pmap = mvpp2_prs_tcam_port_map_get(pe);
2374 mvpp2_prs_hw_inv(priv, pe->index);
2375 priv->prs_shadow[pe->index].valid = false;
2380 /* Continue - set next lookup */
2381 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
2383 /* Set match on DA */
2386 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
2388 /* Set result info bits */
2389 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
2391 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2392 MVPP2_PRS_RI_MAC_ME_MASK);
2393 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2394 MVPP2_PRS_RI_MAC_ME_MASK);
2396 /* Shift to ethertype */
2397 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
2398 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2400 /* Update shadow table and hw entry */
2401 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
2402 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
2403 mvpp2_prs_hw_write(priv, pe);
2410 static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
2414 /* Remove old parser entry */
2415 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
2420 /* Add new parser entry */
2421 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
2425 /* Set addr in the device */
2426 memcpy(port->dev_addr, da, ETH_ALEN);
2431 /* Set prs flow for the port */
2432 static int mvpp2_prs_def_flow(struct mvpp2_port *port)
2434 struct mvpp2_prs_entry *pe;
2437 pe = mvpp2_prs_flow_find(port->priv, port->id);
2439 /* Such entry not exist */
2441 /* Go through the all entires from last to first */
2442 tid = mvpp2_prs_tcam_first_free(port->priv,
2443 MVPP2_PE_LAST_FREE_TID,
2444 MVPP2_PE_FIRST_FREE_TID);
2448 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2452 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
2456 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
2457 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2459 /* Update shadow table */
2460 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
2463 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
2464 mvpp2_prs_hw_write(port->priv, pe);
2470 /* Classifier configuration routines */
2472 /* Update classification flow table registers */
2473 static void mvpp2_cls_flow_write(struct mvpp2 *priv,
2474 struct mvpp2_cls_flow_entry *fe)
2476 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
2477 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
2478 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
2479 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
2482 /* Update classification lookup table register */
2483 static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
2484 struct mvpp2_cls_lookup_entry *le)
2488 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
2489 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
2490 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
2493 /* Classifier default initialization */
2494 static void mvpp2_cls_init(struct mvpp2 *priv)
2496 struct mvpp2_cls_lookup_entry le;
2497 struct mvpp2_cls_flow_entry fe;
2500 /* Enable classifier */
2501 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
2503 /* Clear classifier flow table */
2504 memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
2505 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
2507 mvpp2_cls_flow_write(priv, &fe);
2510 /* Clear classifier lookup table */
2512 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
2515 mvpp2_cls_lookup_write(priv, &le);
2518 mvpp2_cls_lookup_write(priv, &le);
2522 static void mvpp2_cls_port_config(struct mvpp2_port *port)
2524 struct mvpp2_cls_lookup_entry le;
2527 /* Set way for the port */
2528 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
2529 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
2530 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
2532 /* Pick the entry to be accessed in lookup ID decoding table
2533 * according to the way and lkpid.
2535 le.lkpid = port->id;
2539 /* Set initial CPU queue for receiving packets */
2540 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
2541 le.data |= port->first_rxq;
2543 /* Disable classification engines */
2544 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
2546 /* Update lookup ID table entry */
2547 mvpp2_cls_lookup_write(port->priv, &le);
2550 /* Set CPU queue number for oversize packets */
2551 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
2555 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
2556 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
2558 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
2559 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
2561 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
2562 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
2563 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
2566 /* Buffer Manager configuration routines */
2569 static int mvpp2_bm_pool_create(struct udevice *dev,
2571 struct mvpp2_bm_pool *bm_pool, int size)
2575 /* Number of buffer pointers must be a multiple of 16, as per
2576 * hardware constraints
2578 if (!IS_ALIGNED(size, 16))
2581 bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
2582 bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
2583 if (!bm_pool->virt_addr)
2586 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
2587 MVPP2_BM_POOL_PTR_ALIGN)) {
2588 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
2589 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
2593 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
2594 lower_32_bits(bm_pool->dma_addr));
2595 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
2597 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2598 val |= MVPP2_BM_START_MASK;
2599 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2601 bm_pool->type = MVPP2_BM_FREE;
2602 bm_pool->size = size;
2603 bm_pool->pkt_size = 0;
2604 bm_pool->buf_num = 0;
2609 /* Set pool buffer size */
2610 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
2611 struct mvpp2_bm_pool *bm_pool,
2616 bm_pool->buf_size = buf_size;
2618 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
2619 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
2622 /* Free all buffers from the pool */
2623 static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
2624 struct mvpp2_bm_pool *bm_pool)
2628 for (i = 0; i < bm_pool->buf_num; i++) {
2629 /* Allocate buffer back from the buffer manager */
2630 mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
2633 bm_pool->buf_num = 0;
2637 static int mvpp2_bm_pool_destroy(struct udevice *dev,
2639 struct mvpp2_bm_pool *bm_pool)
2643 mvpp2_bm_bufs_free(dev, priv, bm_pool);
2644 if (bm_pool->buf_num) {
2645 dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
2649 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2650 val |= MVPP2_BM_STOP_MASK;
2651 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2656 static int mvpp2_bm_pools_init(struct udevice *dev,
2660 struct mvpp2_bm_pool *bm_pool;
2662 /* Create all pools with maximum size */
2663 size = MVPP2_BM_POOL_SIZE_MAX;
2664 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2665 bm_pool = &priv->bm_pools[i];
2667 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
2669 goto err_unroll_pools;
2670 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
2675 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
2676 for (i = i - 1; i >= 0; i--)
2677 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
2681 static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
2685 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2686 /* Mask BM all interrupts */
2687 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
2688 /* Clear BM cause register */
2689 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
2692 /* Allocate and initialize BM pools */
2693 priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
2694 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
2695 if (!priv->bm_pools)
2698 err = mvpp2_bm_pools_init(dev, priv);
2704 /* Attach long pool to rxq */
2705 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
2706 int lrxq, int long_pool)
2711 /* Get queue physical ID */
2712 prxq = port->rxqs[lrxq]->id;
2714 if (port->priv->hw_version == MVPP21)
2715 mask = MVPP21_RXQ_POOL_LONG_MASK;
2717 mask = MVPP22_RXQ_POOL_LONG_MASK;
2719 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2721 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
2722 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2725 /* Set pool number in a BM cookie */
2726 static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
2730 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
2731 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
2736 /* Get pool number from a BM cookie */
2737 static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
2739 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
2742 /* Release buffer to BM */
2743 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
2744 dma_addr_t buf_dma_addr,
2745 unsigned long buf_phys_addr)
2747 if (port->priv->hw_version == MVPP22) {
2750 if (sizeof(dma_addr_t) == 8)
2751 val |= upper_32_bits(buf_dma_addr) &
2752 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
2754 if (sizeof(phys_addr_t) == 8)
2755 val |= (upper_32_bits(buf_phys_addr)
2756 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
2757 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
2759 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
2762 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
2763 * returned in the "cookie" field of the RX
2764 * descriptor. Instead of storing the virtual address, we
2765 * store the physical address
2767 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
2768 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
2771 /* Refill BM pool */
2772 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
2773 dma_addr_t dma_addr,
2774 phys_addr_t phys_addr)
2776 int pool = mvpp2_bm_cookie_pool_get(bm);
2778 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2781 /* Allocate buffers for the pool */
2782 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
2783 struct mvpp2_bm_pool *bm_pool, int buf_num)
2788 (buf_num + bm_pool->buf_num > bm_pool->size)) {
2789 netdev_err(port->dev,
2790 "cannot allocate %d buffers for pool %d\n",
2791 buf_num, bm_pool->id);
2795 for (i = 0; i < buf_num; i++) {
2796 mvpp2_bm_pool_put(port, bm_pool->id,
2797 (dma_addr_t)buffer_loc.rx_buffer[i],
2798 (unsigned long)buffer_loc.rx_buffer[i]);
2802 /* Update BM driver with number of buffers added to pool */
2803 bm_pool->buf_num += i;
2808 /* Notify the driver that BM pool is being used as specific type and return the
2809 * pool pointer on success
2811 static struct mvpp2_bm_pool *
2812 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
2815 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
2818 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
2819 netdev_err(port->dev, "mixing pool types is forbidden\n");
2823 if (new_pool->type == MVPP2_BM_FREE)
2824 new_pool->type = type;
2826 /* Allocate buffers in case BM pool is used as long pool, but packet
2827 * size doesn't match MTU or BM pool hasn't being used yet
2829 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
2830 (new_pool->pkt_size == 0)) {
2833 /* Set default buffer number or free all the buffers in case
2834 * the pool is not empty
2836 pkts_num = new_pool->buf_num;
2838 pkts_num = type == MVPP2_BM_SWF_LONG ?
2839 MVPP2_BM_LONG_BUF_NUM :
2840 MVPP2_BM_SHORT_BUF_NUM;
2842 mvpp2_bm_bufs_free(NULL,
2843 port->priv, new_pool);
2845 new_pool->pkt_size = pkt_size;
2847 /* Allocate buffers for this pool */
2848 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
2849 if (num != pkts_num) {
2850 dev_err(dev, "pool %d: %d of %d allocated\n",
2851 new_pool->id, num, pkts_num);
2856 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
2857 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
2862 /* Initialize pools for swf */
2863 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
2867 if (!port->pool_long) {
2869 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
2872 if (!port->pool_long)
2875 port->pool_long->port_map |= (1 << port->id);
2877 for (rxq = 0; rxq < rxq_number; rxq++)
2878 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
2884 /* Port configuration routines */
2886 static void mvpp2_port_mii_set(struct mvpp2_port *port)
2890 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2892 switch (port->phy_interface) {
2893 case PHY_INTERFACE_MODE_SGMII:
2894 val |= MVPP2_GMAC_INBAND_AN_MASK;
2896 case PHY_INTERFACE_MODE_RGMII:
2897 case PHY_INTERFACE_MODE_RGMII_ID:
2898 val |= MVPP2_GMAC_PORT_RGMII_MASK;
2900 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
2903 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2906 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
2910 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2911 val |= MVPP2_GMAC_FC_ADV_EN;
2912 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2915 static void mvpp2_port_enable(struct mvpp2_port *port)
2919 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2920 val |= MVPP2_GMAC_PORT_EN_MASK;
2921 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
2922 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2925 static void mvpp2_port_disable(struct mvpp2_port *port)
2929 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2930 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
2931 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2934 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
2935 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
2939 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
2940 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
2941 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2944 /* Configure loopback port */
2945 static void mvpp2_port_loopback_set(struct mvpp2_port *port)
2949 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
2951 if (port->speed == 1000)
2952 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
2954 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
2956 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
2957 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
2959 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
2961 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2964 static void mvpp2_port_reset(struct mvpp2_port *port)
2968 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2969 ~MVPP2_GMAC_PORT_RESET_MASK;
2970 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2972 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2973 MVPP2_GMAC_PORT_RESET_MASK)
2977 /* Change maximum receive size of the port */
2978 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2982 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2983 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2984 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2985 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2986 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2989 /* PPv2.2 GoP/GMAC config */
2991 /* Set the MAC to reset or exit from reset */
2992 static int gop_gmac_reset(struct mvpp2_port *port, int reset)
2996 /* read - modify - write */
2997 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2999 val |= MVPP2_GMAC_PORT_RESET_MASK;
3001 val &= ~MVPP2_GMAC_PORT_RESET_MASK;
3002 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3010 * Configure port to working with Gig PCS or don't.
3012 static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en)
3016 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3018 val |= MVPP2_GMAC_PCS_ENABLE_MASK;
3020 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
3021 /* enable / disable PCS on this port */
3022 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3027 static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en)
3031 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3033 val |= MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
3035 val &= ~MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
3036 /* enable / disable PCS on this port */
3037 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3042 static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
3047 * Configure minimal level of the Tx FIFO before the lower part
3048 * starts to read a packet
3050 thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
3051 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3052 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3053 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3054 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3056 /* Disable bypass of sync module */
3057 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3058 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3059 /* configure DP clock select according to mode */
3060 val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3061 /* configure QSGMII bypass according to mode */
3062 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3063 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3065 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3066 val |= MVPP2_GMAC_PORT_DIS_PADING_MASK;
3067 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3069 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3071 * Configure GIG MAC to 1000Base-X mode connected to a fiber
3074 val |= MVPP2_GMAC_PORT_TYPE_MASK;
3075 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3077 /* configure AN 0x9268 */
3078 val = MVPP2_GMAC_EN_PCS_AN |
3079 MVPP2_GMAC_AN_BYPASS_EN |
3080 MVPP2_GMAC_CONFIG_MII_SPEED |
3081 MVPP2_GMAC_CONFIG_GMII_SPEED |
3082 MVPP2_GMAC_FC_ADV_EN |
3083 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
3084 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3085 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3088 static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
3093 * Configure minimal level of the Tx FIFO before the lower part
3094 * starts to read a packet
3096 thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
3097 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3098 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3099 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3100 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3102 /* Disable bypass of sync module */
3103 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3104 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3105 /* configure DP clock select according to mode */
3106 val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3107 /* configure QSGMII bypass according to mode */
3108 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3109 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3111 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3112 val |= MVPP2_GMAC_PORT_DIS_PADING_MASK;
3113 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3115 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3116 /* configure GIG MAC to SGMII mode */
3117 val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
3118 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3121 val = MVPP2_GMAC_EN_PCS_AN |
3122 MVPP2_GMAC_AN_BYPASS_EN |
3123 MVPP2_GMAC_AN_SPEED_EN |
3124 MVPP2_GMAC_EN_FC_AN |
3125 MVPP2_GMAC_AN_DUPLEX_EN |
3126 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3127 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3130 static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
3135 * Configure minimal level of the Tx FIFO before the lower part
3136 * starts to read a packet
3138 thresh = MVPP2_RGMII_TX_FIFO_MIN_TH;
3139 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3140 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3141 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3142 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3144 /* Disable bypass of sync module */
3145 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3146 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3147 /* configure DP clock select according to mode */
3148 val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3149 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3150 val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK;
3151 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3153 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3154 val &= ~MVPP2_GMAC_PORT_DIS_PADING_MASK;
3155 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3157 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3158 /* configure GIG MAC to SGMII mode */
3159 val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
3160 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3162 /* configure AN 0xb8e8 */
3163 val = MVPP2_GMAC_AN_BYPASS_EN |
3164 MVPP2_GMAC_AN_SPEED_EN |
3165 MVPP2_GMAC_EN_FC_AN |
3166 MVPP2_GMAC_AN_DUPLEX_EN |
3167 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3168 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3171 /* Set the internal mux's to the required MAC in the GOP */
3172 static int gop_gmac_mode_cfg(struct mvpp2_port *port)
3176 /* Set TX FIFO thresholds */
3177 switch (port->phy_interface) {
3178 case PHY_INTERFACE_MODE_SGMII:
3179 if (port->phy_speed == 2500)
3180 gop_gmac_sgmii2_5_cfg(port);
3182 gop_gmac_sgmii_cfg(port);
3185 case PHY_INTERFACE_MODE_RGMII:
3186 case PHY_INTERFACE_MODE_RGMII_ID:
3187 gop_gmac_rgmii_cfg(port);
3194 /* Jumbo frame support - 0x1400*2= 0x2800 bytes */
3195 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3196 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
3197 val |= 0x1400 << MVPP2_GMAC_MAX_RX_SIZE_OFFS;
3198 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3200 /* PeriodicXonEn disable */
3201 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3202 val &= ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
3203 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
3208 static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port)
3212 /* relevant only for MAC0 (XLG0 and GMAC0) */
3213 if (port->gop_id > 0)
3216 /* configure 1Gig MAC mode */
3217 val = readl(port->base + MVPP22_XLG_CTRL3_REG);
3218 val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3219 val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
3220 writel(val, port->base + MVPP22_XLG_CTRL3_REG);
3223 static int gop_gpcs_reset(struct mvpp2_port *port, int reset)
3227 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3229 val &= ~MVPP2_GMAC_SGMII_MODE_MASK;
3231 val |= MVPP2_GMAC_SGMII_MODE_MASK;
3232 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3237 /* Set the internal mux's to the required PCS in the PI */
3238 static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
3243 switch (num_of_lanes) {
3257 /* configure XG MAC mode */
3258 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3259 val &= ~MVPP22_XPCS_PCSMODE_MASK;
3260 val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
3261 val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
3262 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3267 static int gop_mpcs_mode(struct mvpp2_port *port)
3271 /* configure PCS40G COMMON CONTROL */
3272 val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
3273 val &= ~FORWARD_ERROR_CORRECTION_MASK;
3274 writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
3276 /* configure PCS CLOCK RESET */
3277 val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
3278 val &= ~CLK_DIVISION_RATIO_MASK;
3279 val |= 1 << CLK_DIVISION_RATIO_OFFS;
3280 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
3282 val &= ~CLK_DIV_PHASE_SET_MASK;
3283 val |= MAC_CLK_RESET_MASK;
3284 val |= RX_SD_CLK_RESET_MASK;
3285 val |= TX_SD_CLK_RESET_MASK;
3286 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
3291 /* Set the internal mux's to the required MAC in the GOP */
3292 static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
3296 /* configure 10G MAC mode */
3297 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3298 val |= MVPP22_XLG_RX_FC_EN;
3299 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3301 val = readl(port->base + MVPP22_XLG_CTRL3_REG);
3302 val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3303 val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
3304 writel(val, port->base + MVPP22_XLG_CTRL3_REG);
3306 /* read - modify - write */
3307 val = readl(port->base + MVPP22_XLG_CTRL4_REG);
3308 val &= ~MVPP22_XLG_MODE_DMA_1G;
3309 val |= MVPP22_XLG_FORWARD_PFC_EN;
3310 val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
3311 val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
3312 writel(val, port->base + MVPP22_XLG_CTRL4_REG);
3314 /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
3315 val = readl(port->base + MVPP22_XLG_CTRL1_REG);
3316 val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
3317 val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
3318 writel(val, port->base + MVPP22_XLG_CTRL1_REG);
3320 /* unmask link change interrupt */
3321 val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
3322 val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
3323 val |= 1; /* unmask summary bit */
3324 writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
3329 /* Set PCS to reset or exit from reset */
3330 static int gop_xpcs_reset(struct mvpp2_port *port, int reset)
3334 /* read - modify - write */
3335 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3337 val &= ~MVPP22_XPCS_PCSRESET;
3339 val |= MVPP22_XPCS_PCSRESET;
3340 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3345 /* Set the MAC to reset or exit from reset */
3346 static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
3350 /* read - modify - write */
3351 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3353 val &= ~MVPP22_XLG_MAC_RESETN;
3355 val |= MVPP22_XLG_MAC_RESETN;
3356 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3364 * Init physical port. Configures the port mode and all it's elements
3366 * Does not verify that the selected mode/port number is valid at the
3369 static int gop_port_init(struct mvpp2_port *port)
3371 int mac_num = port->gop_id;
3372 int num_of_act_lanes;
3374 if (mac_num >= MVPP22_GOP_MAC_NUM) {
3375 netdev_err(NULL, "%s: illegal port number %d", __func__,
3380 switch (port->phy_interface) {
3381 case PHY_INTERFACE_MODE_RGMII:
3382 case PHY_INTERFACE_MODE_RGMII_ID:
3383 gop_gmac_reset(port, 1);
3386 gop_gpcs_mode_cfg(port, 0);
3387 gop_bypass_clk_cfg(port, 1);
3390 gop_gmac_mode_cfg(port);
3392 gop_gpcs_reset(port, 0);
3395 gop_gmac_reset(port, 0);
3398 case PHY_INTERFACE_MODE_SGMII:
3400 gop_gpcs_mode_cfg(port, 1);
3403 gop_gmac_mode_cfg(port);
3404 /* select proper Mac mode */
3405 gop_xlg_2_gig_mac_cfg(port);
3408 gop_gpcs_reset(port, 0);
3410 gop_gmac_reset(port, 0);
3413 case PHY_INTERFACE_MODE_SFI:
3414 num_of_act_lanes = 2;
3417 gop_xpcs_mode(port, num_of_act_lanes);
3418 gop_mpcs_mode(port);
3420 gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
3423 gop_xpcs_reset(port, 0);
3426 gop_xlg_mac_reset(port, 0);
3430 netdev_err(NULL, "%s: Requested port mode (%d) not supported\n",
3431 __func__, port->phy_interface);
3438 static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable)
3442 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3444 /* Enable port and MIB counters update */
3445 val |= MVPP22_XLG_PORT_EN;
3446 val &= ~MVPP22_XLG_MIBCNT_DIS;
3449 val &= ~MVPP22_XLG_PORT_EN;
3451 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3454 static void gop_port_enable(struct mvpp2_port *port, int enable)
3456 switch (port->phy_interface) {
3457 case PHY_INTERFACE_MODE_RGMII:
3458 case PHY_INTERFACE_MODE_RGMII_ID:
3459 case PHY_INTERFACE_MODE_SGMII:
3461 mvpp2_port_enable(port);
3463 mvpp2_port_disable(port);
3466 case PHY_INTERFACE_MODE_SFI:
3467 gop_xlg_mac_port_enable(port, enable);
3471 netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__,
3472 port->phy_interface);
3477 /* RFU1 functions */
3478 static inline u32 gop_rfu1_read(struct mvpp2 *priv, u32 offset)
3480 return readl(priv->rfu1_base + offset);
3483 static inline void gop_rfu1_write(struct mvpp2 *priv, u32 offset, u32 data)
3485 writel(data, priv->rfu1_base + offset);
3488 static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
3493 if (phy_type == PHY_INTERFACE_MODE_SGMII)
3494 val |= MV_NETC_GE_MAC2_SGMII;
3498 if (phy_type == PHY_INTERFACE_MODE_SGMII)
3499 val |= MV_NETC_GE_MAC3_SGMII;
3500 else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
3501 phy_type == PHY_INTERFACE_MODE_RGMII_ID)
3502 val |= MV_NETC_GE_MAC3_RGMII;
3508 static void gop_netc_active_port(struct mvpp2 *priv, int gop_id, u32 val)
3512 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
3513 reg &= ~(NETC_PORTS_ACTIVE_MASK(gop_id));
3515 val <<= NETC_PORTS_ACTIVE_OFFSET(gop_id);
3516 val &= NETC_PORTS_ACTIVE_MASK(gop_id);
3520 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
3523 static void gop_netc_mii_mode(struct mvpp2 *priv, int gop_id, u32 val)
3527 reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
3528 reg &= ~NETC_GBE_PORT1_MII_MODE_MASK;
3530 val <<= NETC_GBE_PORT1_MII_MODE_OFFS;
3531 val &= NETC_GBE_PORT1_MII_MODE_MASK;
3535 gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
3538 static void gop_netc_gop_reset(struct mvpp2 *priv, u32 val)
3542 reg = gop_rfu1_read(priv, GOP_SOFT_RESET_1_REG);
3543 reg &= ~NETC_GOP_SOFT_RESET_MASK;
3545 val <<= NETC_GOP_SOFT_RESET_OFFS;
3546 val &= NETC_GOP_SOFT_RESET_MASK;
3550 gop_rfu1_write(priv, GOP_SOFT_RESET_1_REG, reg);
3553 static void gop_netc_gop_clock_logic_set(struct mvpp2 *priv, u32 val)
3557 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3558 reg &= ~NETC_CLK_DIV_PHASE_MASK;
3560 val <<= NETC_CLK_DIV_PHASE_OFFS;
3561 val &= NETC_CLK_DIV_PHASE_MASK;
3565 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3568 static void gop_netc_port_rf_reset(struct mvpp2 *priv, int gop_id, u32 val)
3572 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
3573 reg &= ~(NETC_PORT_GIG_RF_RESET_MASK(gop_id));
3575 val <<= NETC_PORT_GIG_RF_RESET_OFFS(gop_id);
3576 val &= NETC_PORT_GIG_RF_RESET_MASK(gop_id);
3580 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
3583 static void gop_netc_gbe_sgmii_mode_select(struct mvpp2 *priv, int gop_id,
3586 u32 reg, mask, offset;
3589 mask = NETC_GBE_PORT0_SGMII_MODE_MASK;
3590 offset = NETC_GBE_PORT0_SGMII_MODE_OFFS;
3592 mask = NETC_GBE_PORT1_SGMII_MODE_MASK;
3593 offset = NETC_GBE_PORT1_SGMII_MODE_OFFS;
3595 reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
3603 gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
3606 static void gop_netc_bus_width_select(struct mvpp2 *priv, u32 val)
3610 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3611 reg &= ~NETC_BUS_WIDTH_SELECT_MASK;
3613 val <<= NETC_BUS_WIDTH_SELECT_OFFS;
3614 val &= NETC_BUS_WIDTH_SELECT_MASK;
3618 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3621 static void gop_netc_sample_stages_timing(struct mvpp2 *priv, u32 val)
3625 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3626 reg &= ~NETC_GIG_RX_DATA_SAMPLE_MASK;
3628 val <<= NETC_GIG_RX_DATA_SAMPLE_OFFS;
3629 val &= NETC_GIG_RX_DATA_SAMPLE_MASK;
3633 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3636 static void gop_netc_mac_to_xgmii(struct mvpp2 *priv, int gop_id,
3637 enum mv_netc_phase phase)
3640 case MV_NETC_FIRST_PHASE:
3641 /* Set Bus Width to HB mode = 1 */
3642 gop_netc_bus_width_select(priv, 1);
3643 /* Select RGMII mode */
3644 gop_netc_gbe_sgmii_mode_select(priv, gop_id, MV_NETC_GBE_XMII);
3647 case MV_NETC_SECOND_PHASE:
3648 /* De-assert the relevant port HB reset */
3649 gop_netc_port_rf_reset(priv, gop_id, 1);
3654 static void gop_netc_mac_to_sgmii(struct mvpp2 *priv, int gop_id,
3655 enum mv_netc_phase phase)
3658 case MV_NETC_FIRST_PHASE:
3659 /* Set Bus Width to HB mode = 1 */
3660 gop_netc_bus_width_select(priv, 1);
3661 /* Select SGMII mode */
3663 gop_netc_gbe_sgmii_mode_select(priv, gop_id,
3667 /* Configure the sample stages */
3668 gop_netc_sample_stages_timing(priv, 0);
3669 /* Configure the ComPhy Selector */
3670 /* gop_netc_com_phy_selector_config(netComplex); */
3673 case MV_NETC_SECOND_PHASE:
3674 /* De-assert the relevant port HB reset */
3675 gop_netc_port_rf_reset(priv, gop_id, 1);
3680 static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase)
3682 u32 c = priv->netc_config;
3684 if (c & MV_NETC_GE_MAC2_SGMII)
3685 gop_netc_mac_to_sgmii(priv, 2, phase);
3687 gop_netc_mac_to_xgmii(priv, 2, phase);
3689 if (c & MV_NETC_GE_MAC3_SGMII) {
3690 gop_netc_mac_to_sgmii(priv, 3, phase);
3692 gop_netc_mac_to_xgmii(priv, 3, phase);
3693 if (c & MV_NETC_GE_MAC3_RGMII)
3694 gop_netc_mii_mode(priv, 3, MV_NETC_GBE_RGMII);
3696 gop_netc_mii_mode(priv, 3, MV_NETC_GBE_MII);
3699 /* Activate gop ports 0, 2, 3 */
3700 gop_netc_active_port(priv, 0, 1);
3701 gop_netc_active_port(priv, 2, 1);
3702 gop_netc_active_port(priv, 3, 1);
3704 if (phase == MV_NETC_SECOND_PHASE) {
3705 /* Enable the GOP internal clock logic */
3706 gop_netc_gop_clock_logic_set(priv, 1);
3707 /* De-assert GOP unit reset */
3708 gop_netc_gop_reset(priv, 1);
3714 /* Set defaults to the MVPP2 port */
3715 static void mvpp2_defaults_set(struct mvpp2_port *port)
3717 int tx_port_num, val, queue, ptxq, lrxq;
3719 if (port->priv->hw_version == MVPP21) {
3720 /* Configure port to loopback if needed */
3721 if (port->flags & MVPP2_F_LOOPBACK)
3722 mvpp2_port_loopback_set(port);
3724 /* Update TX FIFO MIN Threshold */
3725 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3726 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3727 /* Min. TX threshold must be less than minimal packet length */
3728 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
3729 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3732 /* Disable Legacy WRR, Disable EJP, Release from reset */
3733 tx_port_num = mvpp2_egress_port(port);
3734 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
3736 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
3738 /* Close bandwidth for all queues */
3739 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
3740 ptxq = mvpp2_txq_phys(port->id, queue);
3741 mvpp2_write(port->priv,
3742 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
3745 /* Set refill period to 1 usec, refill tokens
3746 * and bucket size to maximum
3748 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
3749 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
3750 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
3751 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
3752 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
3753 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
3754 val = MVPP2_TXP_TOKEN_SIZE_MAX;
3755 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3757 /* Set MaximumLowLatencyPacketSize value to 256 */
3758 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
3759 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
3760 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
3762 /* Enable Rx cache snoop */
3763 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3764 queue = port->rxqs[lrxq]->id;
3765 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3766 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
3767 MVPP2_SNOOP_BUF_HDR_MASK;
3768 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3772 /* Enable/disable receiving packets */
3773 static void mvpp2_ingress_enable(struct mvpp2_port *port)
3778 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3779 queue = port->rxqs[lrxq]->id;
3780 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3781 val &= ~MVPP2_RXQ_DISABLE_MASK;
3782 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3786 static void mvpp2_ingress_disable(struct mvpp2_port *port)
3791 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3792 queue = port->rxqs[lrxq]->id;
3793 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3794 val |= MVPP2_RXQ_DISABLE_MASK;
3795 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3799 /* Enable transmit via physical egress queue
3800 * - HW starts take descriptors from DRAM
3802 static void mvpp2_egress_enable(struct mvpp2_port *port)
3806 int tx_port_num = mvpp2_egress_port(port);
3808 /* Enable all initialized TXs. */
3810 for (queue = 0; queue < txq_number; queue++) {
3811 struct mvpp2_tx_queue *txq = port->txqs[queue];
3813 if (txq->descs != NULL)
3814 qmap |= (1 << queue);
3817 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3818 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
3821 /* Disable transmit via physical egress queue
3822 * - HW doesn't take descriptors from DRAM
3824 static void mvpp2_egress_disable(struct mvpp2_port *port)
3828 int tx_port_num = mvpp2_egress_port(port);
3830 /* Issue stop command for active channels only */
3831 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3832 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
3833 MVPP2_TXP_SCHED_ENQ_MASK;
3835 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
3836 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
3838 /* Wait for all Tx activity to terminate. */
3841 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
3842 netdev_warn(port->dev,
3843 "Tx stop timed out, status=0x%08x\n",
3850 /* Check port TX Command register that all
3851 * Tx queues are stopped
3853 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
3854 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
3857 /* Rx descriptors helper methods */
3859 /* Get number of Rx descriptors occupied by received packets */
3861 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
3863 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
3865 return val & MVPP2_RXQ_OCCUPIED_MASK;
3868 /* Update Rx queue status with the number of occupied and available
3869 * Rx descriptor slots.
3872 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
3873 int used_count, int free_count)
3875 /* Decrement the number of used descriptors and increment count
3876 * increment the number of free descriptors.
3878 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
3880 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
3883 /* Get pointer to next RX descriptor to be processed by SW */
3884 static inline struct mvpp2_rx_desc *
3885 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
3887 int rx_desc = rxq->next_desc_to_proc;
3889 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
3890 prefetch(rxq->descs + rxq->next_desc_to_proc);
3891 return rxq->descs + rx_desc;
3894 /* Set rx queue offset */
3895 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
3896 int prxq, int offset)
3900 /* Convert offset from bytes to units of 32 bytes */
3901 offset = offset >> 5;
3903 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
3904 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
3907 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
3908 MVPP2_RXQ_PACKET_OFFSET_MASK);
3910 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3913 /* Obtain BM cookie information from descriptor */
3914 static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
3915 struct mvpp2_rx_desc *rx_desc)
3917 int cpu = smp_processor_id();
3920 pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
3921 MVPP2_RXD_BM_POOL_ID_MASK) >>
3922 MVPP2_RXD_BM_POOL_ID_OFFS;
3924 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
3925 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
3928 /* Tx descriptors helper methods */
3930 /* Get number of Tx descriptors waiting to be transmitted by HW */
3931 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
3932 struct mvpp2_tx_queue *txq)
3936 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3937 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3939 return val & MVPP2_TXQ_PENDING_MASK;
3942 /* Get pointer to next Tx descriptor to be processed (send) by HW */
3943 static struct mvpp2_tx_desc *
3944 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
3946 int tx_desc = txq->next_desc_to_proc;
3948 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
3949 return txq->descs + tx_desc;
3952 /* Update HW with number of aggregated Tx descriptors to be sent */
3953 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
3955 /* aggregated access - relevant TXQ number is written in TX desc */
3956 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
3959 /* Get number of sent descriptors and decrement counter.
3960 * The number of sent descriptors is returned.
3963 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
3964 struct mvpp2_tx_queue *txq)
3968 /* Reading status reg resets transmitted descriptor counter */
3969 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
3971 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
3972 MVPP2_TRANSMITTED_COUNT_OFFSET;
3975 static void mvpp2_txq_sent_counter_clear(void *arg)
3977 struct mvpp2_port *port = arg;
3980 for (queue = 0; queue < txq_number; queue++) {
3981 int id = port->txqs[queue]->id;
3983 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
3987 /* Set max sizes for Tx queues */
3988 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
3991 int txq, tx_port_num;
3993 mtu = port->pkt_size * 8;
3994 if (mtu > MVPP2_TXP_MTU_MAX)
3995 mtu = MVPP2_TXP_MTU_MAX;
3997 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
4000 /* Indirect access to registers */
4001 tx_port_num = mvpp2_egress_port(port);
4002 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4005 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
4006 val &= ~MVPP2_TXP_MTU_MAX;
4008 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
4010 /* TXP token size and all TXQs token size must be larger that MTU */
4011 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
4012 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
4015 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
4017 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
4020 for (txq = 0; txq < txq_number; txq++) {
4021 val = mvpp2_read(port->priv,
4022 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
4023 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
4027 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
4029 mvpp2_write(port->priv,
4030 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
4036 /* Free Tx queue skbuffs */
4037 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
4038 struct mvpp2_tx_queue *txq,
4039 struct mvpp2_txq_pcpu *txq_pcpu, int num)
4043 for (i = 0; i < num; i++)
4044 mvpp2_txq_inc_get(txq_pcpu);
4047 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
4050 int queue = fls(cause) - 1;
4052 return port->rxqs[queue];
4055 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
4058 int queue = fls(cause) - 1;
4060 return port->txqs[queue];
4063 /* Rx/Tx queue initialization/cleanup methods */
4065 /* Allocate and initialize descriptors for aggr TXQ */
4066 static int mvpp2_aggr_txq_init(struct udevice *dev,
4067 struct mvpp2_tx_queue *aggr_txq,
4068 int desc_num, int cpu,
4073 /* Allocate memory for TX descriptors */
4074 aggr_txq->descs = buffer_loc.aggr_tx_descs;
4075 aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
4076 if (!aggr_txq->descs)
4079 /* Make sure descriptor address is cache line size aligned */
4080 BUG_ON(aggr_txq->descs !=
4081 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4083 aggr_txq->last_desc = aggr_txq->size - 1;
4085 /* Aggr TXQ no reset WA */
4086 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
4087 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
4089 /* Set Tx descriptors queue starting address indirect
4092 if (priv->hw_version == MVPP21)
4093 txq_dma = aggr_txq->descs_dma;
4095 txq_dma = aggr_txq->descs_dma >>
4096 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
4098 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
4099 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
4104 /* Create a specified Rx queue */
4105 static int mvpp2_rxq_init(struct mvpp2_port *port,
4106 struct mvpp2_rx_queue *rxq)
4111 rxq->size = port->rx_ring_size;
4113 /* Allocate memory for RX descriptors */
4114 rxq->descs = buffer_loc.rx_descs;
4115 rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
4119 BUG_ON(rxq->descs !=
4120 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4122 rxq->last_desc = rxq->size - 1;
4124 /* Zero occupied and non-occupied counters - direct access */
4125 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4127 /* Set Rx descriptors queue starting address - indirect access */
4128 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4129 if (port->priv->hw_version == MVPP21)
4130 rxq_dma = rxq->descs_dma;
4132 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
4133 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
4134 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
4135 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
4138 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
4140 /* Add number of descriptors ready for receiving packets */
4141 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
4146 /* Push packets received by the RXQ to BM pool */
4147 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
4148 struct mvpp2_rx_queue *rxq)
4152 rx_received = mvpp2_rxq_received(port, rxq->id);
4156 for (i = 0; i < rx_received; i++) {
4157 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
4158 u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
4160 mvpp2_pool_refill(port, bm,
4161 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
4162 mvpp2_rxdesc_cookie_get(port, rx_desc));
4164 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
4167 /* Cleanup Rx queue */
4168 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
4169 struct mvpp2_rx_queue *rxq)
4171 mvpp2_rxq_drop_pkts(port, rxq);
4175 rxq->next_desc_to_proc = 0;
4178 /* Clear Rx descriptors queue starting address and size;
4179 * free descriptor number
4181 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4182 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4183 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
4184 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
4187 /* Create and initialize a Tx queue */
4188 static int mvpp2_txq_init(struct mvpp2_port *port,
4189 struct mvpp2_tx_queue *txq)
4192 int cpu, desc, desc_per_txq, tx_port_num;
4193 struct mvpp2_txq_pcpu *txq_pcpu;
4195 txq->size = port->tx_ring_size;
4197 /* Allocate memory for Tx descriptors */
4198 txq->descs = buffer_loc.tx_descs;
4199 txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
4203 /* Make sure descriptor address is cache line size aligned */
4204 BUG_ON(txq->descs !=
4205 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4207 txq->last_desc = txq->size - 1;
4209 /* Set Tx descriptors queue starting address - indirect access */
4210 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4211 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
4212 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
4213 MVPP2_TXQ_DESC_SIZE_MASK);
4214 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
4215 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
4216 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
4217 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
4218 val &= ~MVPP2_TXQ_PENDING_MASK;
4219 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
4221 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
4222 * for each existing TXQ.
4223 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
4224 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
4227 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
4228 (txq->log_id * desc_per_txq);
4230 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
4231 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
4232 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
4234 /* WRR / EJP configuration - indirect access */
4235 tx_port_num = mvpp2_egress_port(port);
4236 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4238 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
4239 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
4240 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
4241 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
4242 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
4244 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
4245 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
4248 for_each_present_cpu(cpu) {
4249 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4250 txq_pcpu->size = txq->size;
4256 /* Free allocated TXQ resources */
4257 static void mvpp2_txq_deinit(struct mvpp2_port *port,
4258 struct mvpp2_tx_queue *txq)
4262 txq->next_desc_to_proc = 0;
4265 /* Set minimum bandwidth for disabled TXQs */
4266 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
4268 /* Set Tx descriptors queue starting address and size */
4269 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4270 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
4271 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
4274 /* Cleanup Tx ports */
4275 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
4277 struct mvpp2_txq_pcpu *txq_pcpu;
4278 int delay, pending, cpu;
4281 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4282 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
4283 val |= MVPP2_TXQ_DRAIN_EN_MASK;
4284 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4286 /* The napi queue has been stopped so wait for all packets
4287 * to be transmitted.
4291 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
4292 netdev_warn(port->dev,
4293 "port %d: cleaning queue %d timed out\n",
4294 port->id, txq->log_id);
4300 pending = mvpp2_txq_pend_desc_num_get(port, txq);
4303 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
4304 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4306 for_each_present_cpu(cpu) {
4307 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4309 /* Release all packets */
4310 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
4313 txq_pcpu->count = 0;
4314 txq_pcpu->txq_put_index = 0;
4315 txq_pcpu->txq_get_index = 0;
4319 /* Cleanup all Tx queues */
4320 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
4322 struct mvpp2_tx_queue *txq;
4326 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
4328 /* Reset Tx ports and delete Tx queues */
4329 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
4330 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4332 for (queue = 0; queue < txq_number; queue++) {
4333 txq = port->txqs[queue];
4334 mvpp2_txq_clean(port, txq);
4335 mvpp2_txq_deinit(port, txq);
4338 mvpp2_txq_sent_counter_clear(port);
4340 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
4341 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4344 /* Cleanup all Rx queues */
4345 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
4349 for (queue = 0; queue < rxq_number; queue++)
4350 mvpp2_rxq_deinit(port, port->rxqs[queue]);
4353 /* Init all Rx queues for port */
4354 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
4358 for (queue = 0; queue < rxq_number; queue++) {
4359 err = mvpp2_rxq_init(port, port->rxqs[queue]);
4366 mvpp2_cleanup_rxqs(port);
4370 /* Init all tx queues for port */
4371 static int mvpp2_setup_txqs(struct mvpp2_port *port)
4373 struct mvpp2_tx_queue *txq;
4376 for (queue = 0; queue < txq_number; queue++) {
4377 txq = port->txqs[queue];
4378 err = mvpp2_txq_init(port, txq);
4383 mvpp2_txq_sent_counter_clear(port);
4387 mvpp2_cleanup_txqs(port);
4392 static void mvpp2_link_event(struct mvpp2_port *port)
4394 struct phy_device *phydev = port->phy_dev;
4395 int status_change = 0;
4399 if ((port->speed != phydev->speed) ||
4400 (port->duplex != phydev->duplex)) {
4403 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4404 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
4405 MVPP2_GMAC_CONFIG_GMII_SPEED |
4406 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
4407 MVPP2_GMAC_AN_SPEED_EN |
4408 MVPP2_GMAC_AN_DUPLEX_EN);
4411 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4413 if (phydev->speed == SPEED_1000)
4414 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4415 else if (phydev->speed == SPEED_100)
4416 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
4418 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4420 port->duplex = phydev->duplex;
4421 port->speed = phydev->speed;
4425 if (phydev->link != port->link) {
4426 if (!phydev->link) {
4431 port->link = phydev->link;
4435 if (status_change) {
4437 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4438 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
4439 MVPP2_GMAC_FORCE_LINK_DOWN);
4440 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4441 mvpp2_egress_enable(port);
4442 mvpp2_ingress_enable(port);
4444 mvpp2_ingress_disable(port);
4445 mvpp2_egress_disable(port);
4450 /* Main RX/TX processing routines */
4452 /* Display more error info */
4453 static void mvpp2_rx_error(struct mvpp2_port *port,
4454 struct mvpp2_rx_desc *rx_desc)
4456 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
4457 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
4459 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
4460 case MVPP2_RXD_ERR_CRC:
4461 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
4464 case MVPP2_RXD_ERR_OVERRUN:
4465 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
4468 case MVPP2_RXD_ERR_RESOURCE:
4469 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
4475 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
4476 static int mvpp2_rx_refill(struct mvpp2_port *port,
4477 struct mvpp2_bm_pool *bm_pool,
4478 u32 bm, dma_addr_t dma_addr)
4480 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
4484 /* Set hw internals when starting port */
4485 static void mvpp2_start_dev(struct mvpp2_port *port)
4487 switch (port->phy_interface) {
4488 case PHY_INTERFACE_MODE_RGMII:
4489 case PHY_INTERFACE_MODE_RGMII_ID:
4490 case PHY_INTERFACE_MODE_SGMII:
4491 mvpp2_gmac_max_rx_size_set(port);
4496 mvpp2_txp_max_tx_size_set(port);
4498 if (port->priv->hw_version == MVPP21)
4499 mvpp2_port_enable(port);
4501 gop_port_enable(port, 1);
4504 /* Set hw internals when stopping port */
4505 static void mvpp2_stop_dev(struct mvpp2_port *port)
4507 /* Stop new packets from arriving to RXQs */
4508 mvpp2_ingress_disable(port);
4510 mvpp2_egress_disable(port);
4512 if (port->priv->hw_version == MVPP21)
4513 mvpp2_port_disable(port);
4515 gop_port_enable(port, 0);
4518 static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
4520 struct phy_device *phy_dev;
4522 if (!port->init || port->link == 0) {
4523 phy_dev = phy_connect(port->priv->bus, port->phyaddr, dev,
4524 port->phy_interface);
4525 port->phy_dev = phy_dev;
4527 netdev_err(port->dev, "cannot connect to phy\n");
4530 phy_dev->supported &= PHY_GBIT_FEATURES;
4531 phy_dev->advertising = phy_dev->supported;
4533 port->phy_dev = phy_dev;
4538 phy_config(phy_dev);
4539 phy_startup(phy_dev);
4540 if (!phy_dev->link) {
4541 printf("%s: No link\n", phy_dev->dev->name);
4547 mvpp2_egress_enable(port);
4548 mvpp2_ingress_enable(port);
4554 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
4556 unsigned char mac_bcast[ETH_ALEN] = {
4557 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4560 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
4562 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
4565 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
4566 port->dev_addr, true);
4568 netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
4571 err = mvpp2_prs_def_flow(port);
4573 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
4577 /* Allocate the Rx/Tx queues */
4578 err = mvpp2_setup_rxqs(port);
4580 netdev_err(port->dev, "cannot allocate Rx queues\n");
4584 err = mvpp2_setup_txqs(port);
4586 netdev_err(port->dev, "cannot allocate Tx queues\n");
4590 if (port->phy_node) {
4591 err = mvpp2_phy_connect(dev, port);
4595 mvpp2_link_event(port);
4597 mvpp2_egress_enable(port);
4598 mvpp2_ingress_enable(port);
4601 mvpp2_start_dev(port);
4606 /* No Device ops here in U-Boot */
4608 /* Driver initialization */
4610 static void mvpp2_port_power_up(struct mvpp2_port *port)
4612 struct mvpp2 *priv = port->priv;
4614 /* On PPv2.2 the GoP / interface configuration has already been done */
4615 if (priv->hw_version == MVPP21)
4616 mvpp2_port_mii_set(port);
4617 mvpp2_port_periodic_xon_disable(port);
4618 if (priv->hw_version == MVPP21)
4619 mvpp2_port_fc_adv_enable(port);
4620 mvpp2_port_reset(port);
4623 /* Initialize port HW */
4624 static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
4626 struct mvpp2 *priv = port->priv;
4627 struct mvpp2_txq_pcpu *txq_pcpu;
4628 int queue, cpu, err;
4630 if (port->first_rxq + rxq_number >
4631 MVPP2_MAX_PORTS * priv->max_port_rxqs)
4635 mvpp2_egress_disable(port);
4636 if (priv->hw_version == MVPP21)
4637 mvpp2_port_disable(port);
4639 gop_port_enable(port, 0);
4641 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
4646 /* Associate physical Tx queues to this port and initialize.
4647 * The mapping is predefined.
4649 for (queue = 0; queue < txq_number; queue++) {
4650 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
4651 struct mvpp2_tx_queue *txq;
4653 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
4657 txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
4662 txq->id = queue_phy_id;
4663 txq->log_id = queue;
4664 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
4665 for_each_present_cpu(cpu) {
4666 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4667 txq_pcpu->cpu = cpu;
4670 port->txqs[queue] = txq;
4673 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
4678 /* Allocate and initialize Rx queue for this port */
4679 for (queue = 0; queue < rxq_number; queue++) {
4680 struct mvpp2_rx_queue *rxq;
4682 /* Map physical Rx queue to port's logical Rx queue */
4683 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
4686 /* Map this Rx queue to a physical queue */
4687 rxq->id = port->first_rxq + queue;
4688 rxq->port = port->id;
4689 rxq->logic_rxq = queue;
4691 port->rxqs[queue] = rxq;
4694 /* Configure Rx queue group interrupt for this port */
4695 if (priv->hw_version == MVPP21) {
4696 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
4701 val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
4702 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
4704 val = (CONFIG_MV_ETH_RXQ <<
4705 MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
4706 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
4709 /* Create Rx descriptor rings */
4710 for (queue = 0; queue < rxq_number; queue++) {
4711 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4713 rxq->size = port->rx_ring_size;
4714 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
4715 rxq->time_coal = MVPP2_RX_COAL_USEC;
4718 mvpp2_ingress_disable(port);
4720 /* Port default configuration */
4721 mvpp2_defaults_set(port);
4723 /* Port's classifier configuration */
4724 mvpp2_cls_oversize_rxq_set(port);
4725 mvpp2_cls_port_config(port);
4727 /* Provide an initial Rx packet size */
4728 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
4730 /* Initialize pools for swf */
4731 err = mvpp2_swf_bm_pool_init(port);
4738 static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
4740 int port_node = dev_of_offset(dev);
4741 const char *phy_mode_str;
4747 phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
4750 phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
4752 dev_err(&pdev->dev, "could not find phy address\n");
4759 phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
4761 phy_mode = phy_get_interface_by_name(phy_mode_str);
4762 if (phy_mode == -1) {
4763 dev_err(&pdev->dev, "incorrect phy mode\n");
4767 id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
4769 dev_err(&pdev->dev, "missing port-id value\n");
4773 #ifdef CONFIG_DM_GPIO
4774 gpio_request_by_name(dev, "phy-reset-gpios", 0,
4775 &port->phy_reset_gpio, GPIOD_IS_OUT);
4776 gpio_request_by_name(dev, "marvell,sfp-tx-disable-gpio", 0,
4777 &port->phy_tx_disable_gpio, GPIOD_IS_OUT);
4782 * Not sure if this DT property "phy-speed" will get accepted, so
4783 * this might change later
4785 /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
4786 port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
4790 if (port->priv->hw_version == MVPP21)
4791 port->first_rxq = port->id * rxq_number;
4793 port->first_rxq = port->id * port->priv->max_port_rxqs;
4794 port->phy_node = phy_node;
4795 port->phy_interface = phy_mode;
4796 port->phyaddr = phyaddr;
4801 #ifdef CONFIG_DM_GPIO
4802 /* Port GPIO initialization */
4803 static void mvpp2_gpio_init(struct mvpp2_port *port)
4805 if (dm_gpio_is_valid(&port->phy_reset_gpio)) {
4806 dm_gpio_set_value(&port->phy_reset_gpio, 0);
4808 dm_gpio_set_value(&port->phy_reset_gpio, 1);
4811 if (dm_gpio_is_valid(&port->phy_tx_disable_gpio))
4812 dm_gpio_set_value(&port->phy_tx_disable_gpio, 0);
4816 /* Ports initialization */
4817 static int mvpp2_port_probe(struct udevice *dev,
4818 struct mvpp2_port *port,
4824 port->tx_ring_size = MVPP2_MAX_TXD;
4825 port->rx_ring_size = MVPP2_MAX_RXD;
4827 err = mvpp2_port_init(dev, port);
4829 dev_err(&pdev->dev, "failed to init port %d\n", port->id);
4832 mvpp2_port_power_up(port);
4834 #ifdef CONFIG_DM_GPIO
4835 mvpp2_gpio_init(port);
4838 priv->port_list[port->id] = port;
4842 /* Initialize decoding windows */
4843 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
4849 for (i = 0; i < 6; i++) {
4850 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
4851 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
4854 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
4859 for (i = 0; i < dram->num_cs; i++) {
4860 const struct mbus_dram_window *cs = dram->cs + i;
4862 mvpp2_write(priv, MVPP2_WIN_BASE(i),
4863 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
4864 dram->mbus_dram_target_id);
4866 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
4867 (cs->size - 1) & 0xffff0000);
4869 win_enable |= (1 << i);
4872 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
4875 /* Initialize Rx FIFO's */
4876 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
4880 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4881 if (priv->hw_version == MVPP22) {
4884 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4885 MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
4887 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4888 MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
4889 } else if (port == 1) {
4891 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4892 MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
4894 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4895 MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
4898 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4899 MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
4901 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4902 MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
4905 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4906 MVPP21_RX_FIFO_PORT_DATA_SIZE);
4907 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4908 MVPP21_RX_FIFO_PORT_ATTR_SIZE);
4912 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
4913 MVPP2_RX_FIFO_PORT_MIN_PKT);
4914 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
4917 /* Initialize Tx FIFO's */
4918 static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
4922 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4923 /* Port 0 supports 10KB TX FIFO */
4925 val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
4926 MVPP22_TX_FIFO_SIZE_MASK;
4928 val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
4929 MVPP22_TX_FIFO_SIZE_MASK;
4931 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
4935 static void mvpp2_axi_init(struct mvpp2 *priv)
4937 u32 val, rdval, wrval;
4939 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
4941 /* AXI Bridge Configuration */
4943 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
4944 << MVPP22_AXI_ATTR_CACHE_OFFS;
4945 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4946 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4948 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
4949 << MVPP22_AXI_ATTR_CACHE_OFFS;
4950 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4951 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4954 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
4955 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
4958 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
4959 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
4960 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
4961 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
4964 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
4965 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
4967 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
4968 << MVPP22_AXI_CODE_CACHE_OFFS;
4969 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
4970 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4971 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
4972 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
4974 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
4975 << MVPP22_AXI_CODE_CACHE_OFFS;
4976 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4977 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4979 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
4981 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
4982 << MVPP22_AXI_CODE_CACHE_OFFS;
4983 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4984 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4986 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
4989 /* Initialize network controller common part HW */
4990 static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
4992 const struct mbus_dram_target_info *dram_target_info;
4996 /* Checks for hardware constraints (U-Boot uses only one rxq) */
4997 if ((rxq_number > priv->max_port_rxqs) ||
4998 (txq_number > MVPP2_MAX_TXQ)) {
4999 dev_err(&pdev->dev, "invalid queue size parameter\n");
5003 /* MBUS windows configuration */
5004 dram_target_info = mvebu_mbus_dram_info();
5005 if (dram_target_info)
5006 mvpp2_conf_mbus_windows(dram_target_info, priv);
5008 if (priv->hw_version == MVPP22)
5009 mvpp2_axi_init(priv);
5011 if (priv->hw_version == MVPP21) {
5012 /* Disable HW PHY polling */
5013 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5014 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
5015 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5017 /* Enable HW PHY polling */
5018 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5019 val |= MVPP22_SMI_POLLING_EN;
5020 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5023 /* Allocate and initialize aggregated TXQs */
5024 priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
5025 sizeof(struct mvpp2_tx_queue),
5027 if (!priv->aggr_txqs)
5030 for_each_present_cpu(i) {
5031 priv->aggr_txqs[i].id = i;
5032 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
5033 err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
5034 MVPP2_AGGR_TXQ_SIZE, i, priv);
5040 mvpp2_rx_fifo_init(priv);
5043 if (priv->hw_version == MVPP22)
5044 mvpp2_tx_fifo_init(priv);
5046 /* Reset Rx queue group interrupt configuration */
5047 for (i = 0; i < MVPP2_MAX_PORTS; i++) {
5048 if (priv->hw_version == MVPP21) {
5049 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i),
5055 val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
5056 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
5058 val = (CONFIG_MV_ETH_RXQ <<
5059 MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
5061 MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
5065 if (priv->hw_version == MVPP21)
5066 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
5067 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
5069 /* Allow cache snoop when transmiting packets */
5070 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
5072 /* Buffer Manager initialization */
5073 err = mvpp2_bm_init(dev, priv);
5077 /* Parser default initialization */
5078 err = mvpp2_prs_default_init(dev, priv);
5082 /* Classifier default initialization */
5083 mvpp2_cls_init(priv);
5088 /* SMI / MDIO functions */
5090 static int smi_wait_ready(struct mvpp2 *priv)
5092 u32 timeout = MVPP2_SMI_TIMEOUT;
5095 /* wait till the SMI is not busy */
5097 /* read smi register */
5098 smi_reg = readl(priv->mdio_base);
5099 if (timeout-- == 0) {
5100 printf("Error: SMI busy timeout\n");
5103 } while (smi_reg & MVPP2_SMI_BUSY);
5109 * mpp2_mdio_read - miiphy_read callback function.
5111 * Returns 16bit phy register value, or 0xffff on error
5113 static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
5115 struct mvpp2 *priv = bus->priv;
5119 /* check parameters */
5120 if (addr > MVPP2_PHY_ADDR_MASK) {
5121 printf("Error: Invalid PHY address %d\n", addr);
5125 if (reg > MVPP2_PHY_REG_MASK) {
5126 printf("Err: Invalid register offset %d\n", reg);
5130 /* wait till the SMI is not busy */
5131 if (smi_wait_ready(priv) < 0)
5134 /* fill the phy address and regiser offset and read opcode */
5135 smi_reg = (addr << MVPP2_SMI_DEV_ADDR_OFFS)
5136 | (reg << MVPP2_SMI_REG_ADDR_OFFS)
5137 | MVPP2_SMI_OPCODE_READ;
5139 /* write the smi register */
5140 writel(smi_reg, priv->mdio_base);
5142 /* wait till read value is ready */
5143 timeout = MVPP2_SMI_TIMEOUT;
5146 /* read smi register */
5147 smi_reg = readl(priv->mdio_base);
5148 if (timeout-- == 0) {
5149 printf("Err: SMI read ready timeout\n");
5152 } while (!(smi_reg & MVPP2_SMI_READ_VALID));
5154 /* Wait for the data to update in the SMI register */
5155 for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++)
5158 return readl(priv->mdio_base) & MVPP2_SMI_DATA_MASK;
5162 * mpp2_mdio_write - miiphy_write callback function.
5164 * Returns 0 if write succeed, -EINVAL on bad parameters
5167 static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
5170 struct mvpp2 *priv = bus->priv;
5173 /* check parameters */
5174 if (addr > MVPP2_PHY_ADDR_MASK) {
5175 printf("Error: Invalid PHY address %d\n", addr);
5179 if (reg > MVPP2_PHY_REG_MASK) {
5180 printf("Err: Invalid register offset %d\n", reg);
5184 /* wait till the SMI is not busy */
5185 if (smi_wait_ready(priv) < 0)
5188 /* fill the phy addr and reg offset and write opcode and data */
5189 smi_reg = value << MVPP2_SMI_DATA_OFFS;
5190 smi_reg |= (addr << MVPP2_SMI_DEV_ADDR_OFFS)
5191 | (reg << MVPP2_SMI_REG_ADDR_OFFS);
5192 smi_reg &= ~MVPP2_SMI_OPCODE_READ;
5194 /* write the smi register */
5195 writel(smi_reg, priv->mdio_base);
5200 static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
5202 struct mvpp2_port *port = dev_get_priv(dev);
5203 struct mvpp2_rx_desc *rx_desc;
5204 struct mvpp2_bm_pool *bm_pool;
5205 dma_addr_t dma_addr;
5207 int pool, rx_bytes, err;
5209 struct mvpp2_rx_queue *rxq;
5210 u32 cause_rx_tx, cause_rx, cause_misc;
5213 cause_rx_tx = mvpp2_read(port->priv,
5214 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
5215 cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
5216 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
5217 if (!cause_rx_tx && !cause_misc)
5220 cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
5222 /* Process RX packets */
5223 cause_rx |= port->pending_cause_rx;
5224 rxq = mvpp2_get_rx_queue(port, cause_rx);
5226 /* Get number of received packets and clamp the to-do */
5227 rx_received = mvpp2_rxq_received(port, rxq->id);
5229 /* Return if no packets are received */
5233 rx_desc = mvpp2_rxq_next_desc_get(rxq);
5234 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
5235 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
5236 rx_bytes -= MVPP2_MH_SIZE;
5237 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
5239 bm = mvpp2_bm_cookie_build(port, rx_desc);
5240 pool = mvpp2_bm_cookie_pool_get(bm);
5241 bm_pool = &port->priv->bm_pools[pool];
5243 /* In case of an error, release the requested buffer pointer
5244 * to the Buffer Manager. This request process is controlled
5245 * by the hardware, and the information about the buffer is
5246 * comprised by the RX descriptor.
5248 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
5249 mvpp2_rx_error(port, rx_desc);
5250 /* Return the buffer to the pool */
5251 mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
5255 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
5257 netdev_err(port->dev, "failed to refill BM pools\n");
5261 /* Update Rx queue management counters */
5263 mvpp2_rxq_status_update(port, rxq->id, 1, 1);
5265 /* give packet to stack - skip on first n bytes */
5266 data = (u8 *)dma_addr + 2 + 32;
5272 * No cache invalidation needed here, since the rx_buffer's are
5273 * located in a uncached memory region
5281 static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
5286 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
5287 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
5289 val |= MVPP2_TXQ_DRAIN_EN_MASK;
5291 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
5292 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
5295 static int mvpp2_send(struct udevice *dev, void *packet, int length)
5297 struct mvpp2_port *port = dev_get_priv(dev);
5298 struct mvpp2_tx_queue *txq, *aggr_txq;
5299 struct mvpp2_tx_desc *tx_desc;
5303 txq = port->txqs[0];
5304 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
5306 /* Get a descriptor for the first part of the packet */
5307 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
5308 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
5309 mvpp2_txdesc_size_set(port, tx_desc, length);
5310 mvpp2_txdesc_offset_set(port, tx_desc,
5311 (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
5312 mvpp2_txdesc_dma_addr_set(port, tx_desc,
5313 (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
5314 /* First and Last descriptor */
5315 mvpp2_txdesc_cmd_set(port, tx_desc,
5316 MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
5317 | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
5320 flush_dcache_range((unsigned long)packet,
5321 (unsigned long)packet + ALIGN(length, PKTALIGN));
5323 /* Enable transmit */
5325 mvpp2_aggr_txq_pend_desc_add(port, 1);
5327 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
5331 if (timeout++ > 10000) {
5332 printf("timeout: packet not sent from aggregated to phys TXQ\n");
5335 tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
5338 /* Enable TXQ drain */
5339 mvpp2_txq_drain(port, txq, 1);
5343 if (timeout++ > 10000) {
5344 printf("timeout: packet not sent\n");
5347 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
5350 /* Disable TXQ drain */
5351 mvpp2_txq_drain(port, txq, 0);
5356 static int mvpp2_start(struct udevice *dev)
5358 struct eth_pdata *pdata = dev_get_platdata(dev);
5359 struct mvpp2_port *port = dev_get_priv(dev);
5361 /* Load current MAC address */
5362 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
5364 /* Reconfigure parser accept the original MAC address */
5365 mvpp2_prs_update_mac_da(port, port->dev_addr);
5367 switch (port->phy_interface) {
5368 case PHY_INTERFACE_MODE_RGMII:
5369 case PHY_INTERFACE_MODE_RGMII_ID:
5370 case PHY_INTERFACE_MODE_SGMII:
5371 mvpp2_port_power_up(port);
5376 mvpp2_open(dev, port);
5381 static void mvpp2_stop(struct udevice *dev)
5383 struct mvpp2_port *port = dev_get_priv(dev);
5385 mvpp2_stop_dev(port);
5386 mvpp2_cleanup_rxqs(port);
5387 mvpp2_cleanup_txqs(port);
5390 static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
5392 writel(port->phyaddr, port->priv->iface_base +
5393 MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
5398 static int mvpp2_base_probe(struct udevice *dev)
5400 struct mvpp2 *priv = dev_get_priv(dev);
5401 struct mii_dev *bus;
5406 /* Save hw-version */
5407 priv->hw_version = dev_get_driver_data(dev);
5410 * U-Boot special buffer handling:
5412 * Allocate buffer area for descs and rx_buffers. This is only
5413 * done once for all interfaces. As only one interface can
5414 * be active. Make this area DMA-safe by disabling the D-cache
5417 /* Align buffer area for descs and rx_buffers to 1MiB */
5418 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
5419 mmu_set_region_dcache_behaviour((unsigned long)bd_space,
5420 BD_SPACE, DCACHE_OFF);
5422 buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
5423 size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
5425 buffer_loc.tx_descs =
5426 (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
5427 size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
5429 buffer_loc.rx_descs =
5430 (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
5431 size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
5433 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
5434 buffer_loc.bm_pool[i] =
5435 (unsigned long *)((unsigned long)bd_space + size);
5436 if (priv->hw_version == MVPP21)
5437 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
5439 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
5442 for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
5443 buffer_loc.rx_buffer[i] =
5444 (unsigned long *)((unsigned long)bd_space + size);
5445 size += RX_BUFFER_SIZE;
5448 /* Clear the complete area so that all descriptors are cleared */
5449 memset(bd_space, 0, size);
5451 /* Save base addresses for later use */
5452 priv->base = (void *)devfdt_get_addr_index(dev, 0);
5453 if (IS_ERR(priv->base))
5454 return PTR_ERR(priv->base);
5456 if (priv->hw_version == MVPP21) {
5457 priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
5458 if (IS_ERR(priv->lms_base))
5459 return PTR_ERR(priv->lms_base);
5461 priv->mdio_base = priv->lms_base + MVPP21_SMI;
5463 priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
5464 if (IS_ERR(priv->iface_base))
5465 return PTR_ERR(priv->iface_base);
5467 priv->mdio_base = priv->iface_base + MVPP22_SMI;
5469 /* Store common base addresses for all ports */
5470 priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
5471 priv->xpcs_base = priv->iface_base + MVPP22_XPCS;
5472 priv->rfu1_base = priv->iface_base + MVPP22_RFU1;
5475 if (priv->hw_version == MVPP21)
5476 priv->max_port_rxqs = 8;
5478 priv->max_port_rxqs = 32;
5480 /* Finally create and register the MDIO bus driver */
5483 printf("Failed to allocate MDIO bus\n");
5487 bus->read = mpp2_mdio_read;
5488 bus->write = mpp2_mdio_write;
5489 snprintf(bus->name, sizeof(bus->name), dev->name);
5490 bus->priv = (void *)priv;
5493 return mdio_register(bus);
5496 static int mvpp2_probe(struct udevice *dev)
5498 struct mvpp2_port *port = dev_get_priv(dev);
5499 struct mvpp2 *priv = dev_get_priv(dev->parent);
5502 /* Only call the probe function for the parent once */
5503 if (!priv->probe_done) {
5504 err = mvpp2_base_probe(dev->parent);
5505 priv->probe_done = 1;
5508 port->priv = dev_get_priv(dev->parent);
5510 err = phy_info_parse(dev, port);
5515 * We need the port specific io base addresses at this stage, since
5516 * gop_port_init() accesses these registers
5518 if (priv->hw_version == MVPP21) {
5519 int priv_common_regs_num = 2;
5521 port->base = (void __iomem *)devfdt_get_addr_index(
5522 dev->parent, priv_common_regs_num + port->id);
5523 if (IS_ERR(port->base))
5524 return PTR_ERR(port->base);
5526 port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
5528 if (port->id == -1) {
5529 dev_err(&pdev->dev, "missing gop-port-id value\n");
5533 port->base = priv->iface_base + MVPP22_PORT_BASE +
5534 port->gop_id * MVPP22_PORT_OFFSET;
5536 /* Set phy address of the port */
5538 mvpp22_smi_phy_addr_cfg(port);
5541 gop_port_init(port);
5544 /* Initialize network controller */
5545 err = mvpp2_init(dev, priv);
5547 dev_err(&pdev->dev, "failed to initialize controller\n");
5551 err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
5555 if (priv->hw_version == MVPP22) {
5556 priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id,
5557 port->phy_interface);
5559 /* Netcomplex configurations for all ports */
5560 gop_netc_init(priv, MV_NETC_FIRST_PHASE);
5561 gop_netc_init(priv, MV_NETC_SECOND_PHASE);
5568 * Empty BM pool and stop its activity before the OS is started
5570 static int mvpp2_remove(struct udevice *dev)
5572 struct mvpp2_port *port = dev_get_priv(dev);
5573 struct mvpp2 *priv = port->priv;
5576 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
5577 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
5582 static const struct eth_ops mvpp2_ops = {
5583 .start = mvpp2_start,
5589 static struct driver mvpp2_driver = {
5592 .probe = mvpp2_probe,
5593 .remove = mvpp2_remove,
5595 .priv_auto_alloc_size = sizeof(struct mvpp2_port),
5596 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
5597 .flags = DM_FLAG_ACTIVE_DMA,
5601 * Use a MISC device to bind the n instances (child nodes) of the
5602 * network base controller in UCLASS_ETH.
5604 static int mvpp2_base_bind(struct udevice *parent)
5606 const void *blob = gd->fdt_blob;
5607 int node = dev_of_offset(parent);
5608 struct uclass_driver *drv;
5609 struct udevice *dev;
5610 struct eth_pdata *plat;
5616 /* Lookup eth driver */
5617 drv = lists_uclass_lookup(UCLASS_ETH);
5619 puts("Cannot find eth driver\n");
5623 base_id_add = base_id;
5625 fdt_for_each_subnode(subnode, blob, node) {
5626 /* Increment base_id for all subnodes, also the disabled ones */
5629 /* Skip disabled ports */
5630 if (!fdtdec_get_is_enabled(blob, subnode))
5633 plat = calloc(1, sizeof(*plat));
5637 id = fdtdec_get_int(blob, subnode, "port-id", -1);
5640 name = calloc(1, 16);
5641 sprintf(name, "mvpp2-%d", id);
5643 /* Create child device UCLASS_ETH and bind it */
5644 device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
5645 dev_set_of_offset(dev, subnode);
5651 static const struct udevice_id mvpp2_ids[] = {
5653 .compatible = "marvell,armada-375-pp2",
5657 .compatible = "marvell,armada-7k-pp22",
5663 U_BOOT_DRIVER(mvpp2_base) = {
5664 .name = "mvpp2_base",
5666 .of_match = mvpp2_ids,
5667 .bind = mvpp2_base_bind,
5668 .priv_auto_alloc_size = sizeof(struct mvpp2),