2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
6 * SPDX-License-Identifier: GPL-2.0+
17 #if !defined(CONFIG_PHYLIB)
18 # error "PCH Gigabit Ethernet driver requires PHYLIB - missing CONFIG_PHYLIB"
21 static struct pci_device_id supported[] = {
22 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_GBE) },
26 static void pch_gbe_mac_read(struct pch_gbe_regs *mac_regs, u8 *addr)
28 u32 macid_hi, macid_lo;
30 macid_hi = readl(&mac_regs->mac_adr[0].high);
31 macid_lo = readl(&mac_regs->mac_adr[0].low) & 0xffff;
32 debug("pch_gbe: macid_hi %#x macid_lo %#x\n", macid_hi, macid_lo);
34 addr[0] = (u8)(macid_hi & 0xff);
35 addr[1] = (u8)((macid_hi >> 8) & 0xff);
36 addr[2] = (u8)((macid_hi >> 16) & 0xff);
37 addr[3] = (u8)((macid_hi >> 24) & 0xff);
38 addr[4] = (u8)(macid_lo & 0xff);
39 addr[5] = (u8)((macid_lo >> 8) & 0xff);
42 static int pch_gbe_mac_write(struct pch_gbe_regs *mac_regs, u8 *addr)
44 u32 macid_hi, macid_lo;
47 macid_hi = addr[0] + (addr[1] << 8) + (addr[2] << 16) + (addr[3] << 24);
48 macid_lo = addr[4] + (addr[5] << 8);
50 writel(macid_hi, &mac_regs->mac_adr[0].high);
51 writel(macid_lo, &mac_regs->mac_adr[0].low);
52 writel(0xfffe, &mac_regs->addr_mask);
55 while (get_timer(start) < PCH_GBE_TIMEOUT) {
56 if (!(readl(&mac_regs->addr_mask) & PCH_GBE_BUSY))
65 static int pch_gbe_reset(struct udevice *dev)
67 struct pch_gbe_priv *priv = dev_get_priv(dev);
68 struct eth_pdata *plat = dev_get_platdata(dev);
69 struct pch_gbe_regs *mac_regs = priv->mac_regs;
75 writel(PCH_GBE_ALL_RST, &mac_regs->reset);
78 * Configure the MAC to RGMII mode after reset
80 * For some unknown reason, we must do the configuration here right
81 * after resetting the whole MAC, otherwise the reset bit in the RESET
82 * register will never be cleared by the hardware. And there is another
83 * way of having the same magic, that is to configure the MODE register
84 * to have the MAC work in MII/GMII mode, which is how current Linux
85 * pch_gbe driver does. Since anyway we need program the MAC to RGMII
86 * mode in the driver, we just do it here.
88 * Note: this behavior is not documented in the hardware manual.
90 writel(PCH_GBE_RGMII_MODE_RGMII | PCH_GBE_CHIP_TYPE_INTERNAL,
91 &mac_regs->rgmii_ctrl);
94 while (get_timer(start) < PCH_GBE_TIMEOUT) {
95 if (!(readl(&mac_regs->reset) & PCH_GBE_ALL_RST)) {
97 * Soft reset clears hardware MAC address registers,
98 * so we have to reload MAC address here in order to
99 * make linux pch_gbe driver happy.
101 return pch_gbe_mac_write(mac_regs, plat->enetaddr);
107 debug("pch_gbe: reset timeout\n");
111 static void pch_gbe_rx_descs_init(struct udevice *dev)
113 struct pch_gbe_priv *priv = dev_get_priv(dev);
114 struct pch_gbe_regs *mac_regs = priv->mac_regs;
115 struct pch_gbe_rx_desc *rx_desc = &priv->rx_desc[0];
118 memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM);
119 for (i = 0; i < PCH_GBE_DESC_NUM; i++)
120 rx_desc[i].buffer_addr = dm_pci_virt_to_mem(priv->dev,
123 writel(dm_pci_virt_to_mem(priv->dev, rx_desc),
124 &mac_regs->rx_dsc_base);
125 writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1),
126 &mac_regs->rx_dsc_size);
128 writel(dm_pci_virt_to_mem(priv->dev, rx_desc + 1),
129 &mac_regs->rx_dsc_sw_p);
132 static void pch_gbe_tx_descs_init(struct udevice *dev)
134 struct pch_gbe_priv *priv = dev_get_priv(dev);
135 struct pch_gbe_regs *mac_regs = priv->mac_regs;
136 struct pch_gbe_tx_desc *tx_desc = &priv->tx_desc[0];
138 memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM);
140 writel(dm_pci_virt_to_mem(priv->dev, tx_desc),
141 &mac_regs->tx_dsc_base);
142 writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1),
143 &mac_regs->tx_dsc_size);
144 writel(dm_pci_virt_to_mem(priv->dev, tx_desc + 1),
145 &mac_regs->tx_dsc_sw_p);
148 static void pch_gbe_adjust_link(struct pch_gbe_regs *mac_regs,
149 struct phy_device *phydev)
152 printf("%s: No link.\n", phydev->dev->name);
156 clrbits_le32(&mac_regs->rgmii_ctrl,
157 PCH_GBE_RGMII_RATE_2_5M | PCH_GBE_CRS_SEL);
158 clrbits_le32(&mac_regs->mode,
159 PCH_GBE_MODE_GMII_ETHER | PCH_GBE_MODE_FULL_DUPLEX);
161 switch (phydev->speed) {
163 setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_125M);
164 setbits_le32(&mac_regs->mode, PCH_GBE_MODE_GMII_ETHER);
167 setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_25M);
168 setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
171 setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_2_5M);
172 setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
176 if (phydev->duplex) {
177 setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_CRS_SEL);
178 setbits_le32(&mac_regs->mode, PCH_GBE_MODE_FULL_DUPLEX);
181 printf("Speed: %d, %s duplex\n", phydev->speed,
182 (phydev->duplex) ? "full" : "half");
187 static int pch_gbe_start(struct udevice *dev)
189 struct pch_gbe_priv *priv = dev_get_priv(dev);
190 struct pch_gbe_regs *mac_regs = priv->mac_regs;
192 if (pch_gbe_reset(dev))
195 pch_gbe_rx_descs_init(dev);
196 pch_gbe_tx_descs_init(dev);
198 /* Enable frame bursting */
199 writel(PCH_GBE_MODE_FR_BST, &mac_regs->mode);
200 /* Disable TCP/IP accelerator */
201 writel(PCH_GBE_RX_TCPIPACC_OFF, &mac_regs->tcpip_acc);
202 /* Disable RX flow control */
203 writel(0, &mac_regs->rx_fctrl);
204 /* Configure RX/TX mode */
205 writel(PCH_GBE_RH_ALM_EMP_16 | PCH_GBE_RH_ALM_FULL_16 |
206 PCH_GBE_RH_RD_TRG_32, &mac_regs->rx_mode);
207 writel(PCH_GBE_TM_TH_TX_STRT_32 | PCH_GBE_TM_TH_ALM_EMP_16 |
208 PCH_GBE_TM_TH_ALM_FULL_32 | PCH_GBE_TM_ST_AND_FD |
209 PCH_GBE_TM_SHORT_PKT, &mac_regs->tx_mode);
211 /* Start up the PHY */
212 if (phy_startup(priv->phydev)) {
213 printf("Could not initialize PHY %s\n",
214 priv->phydev->dev->name);
218 pch_gbe_adjust_link(mac_regs, priv->phydev);
220 if (!priv->phydev->link)
224 writel(PCH_GBE_RX_DMA_EN | PCH_GBE_TX_DMA_EN, &mac_regs->dma_ctrl);
225 writel(PCH_GBE_MRE_MAC_RX_EN, &mac_regs->mac_rx_en);
230 static void pch_gbe_stop(struct udevice *dev)
232 struct pch_gbe_priv *priv = dev_get_priv(dev);
236 phy_shutdown(priv->phydev);
239 static int pch_gbe_send(struct udevice *dev, void *packet, int length)
241 struct pch_gbe_priv *priv = dev_get_priv(dev);
242 struct pch_gbe_regs *mac_regs = priv->mac_regs;
243 struct pch_gbe_tx_desc *tx_head, *tx_desc;
248 tx_head = &priv->tx_desc[0];
249 tx_desc = &priv->tx_desc[priv->tx_idx];
252 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
254 tx_desc->buffer_addr = dm_pci_virt_to_mem(priv->dev, packet);
255 tx_desc->length = length;
256 tx_desc->tx_words_eob = length + 3;
257 tx_desc->tx_frame_ctrl = frame_ctrl;
258 tx_desc->dma_status = 0;
259 tx_desc->gbec_status = 0;
261 /* Test the wrap-around condition */
262 if (++priv->tx_idx >= PCH_GBE_DESC_NUM)
265 writel(dm_pci_virt_to_mem(priv->dev, tx_head + priv->tx_idx),
266 &mac_regs->tx_dsc_sw_p);
268 start = get_timer(0);
269 while (get_timer(start) < PCH_GBE_TIMEOUT) {
270 int_st = readl(&mac_regs->int_st);
271 if (int_st & PCH_GBE_INT_TX_CMPLT)
277 debug("pch_gbe: sent failed\n");
281 static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp)
283 struct pch_gbe_priv *priv = dev_get_priv(dev);
284 struct pch_gbe_regs *mac_regs = priv->mac_regs;
285 struct pch_gbe_rx_desc *rx_desc;
286 ulong hw_desc, length;
289 rx_desc = &priv->rx_desc[priv->rx_idx];
291 readl(&mac_regs->int_st);
292 hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld);
294 /* Just return if not receiving any packet */
295 if (virt_to_phys(rx_desc) == hw_desc)
298 length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN;
299 buffer = dm_pci_mem_to_virt(priv->dev, rx_desc->buffer_addr, length, 0);
300 *packetp = (uchar *)buffer;
305 static int pch_gbe_free_pkt(struct udevice *dev, uchar *packet, int length)
307 struct pch_gbe_priv *priv = dev_get_priv(dev);
308 struct pch_gbe_regs *mac_regs = priv->mac_regs;
309 struct pch_gbe_rx_desc *rx_head = &priv->rx_desc[0];
312 /* Test the wrap-around condition */
313 if (++priv->rx_idx >= PCH_GBE_DESC_NUM)
315 rx_swp = priv->rx_idx;
316 if (++rx_swp >= PCH_GBE_DESC_NUM)
319 writel(dm_pci_virt_to_mem(priv->dev, rx_head + rx_swp),
320 &mac_regs->rx_dsc_sw_p);
325 static int pch_gbe_mdio_ready(struct pch_gbe_regs *mac_regs)
327 ulong start = get_timer(0);
329 while (get_timer(start) < PCH_GBE_TIMEOUT) {
330 if (readl(&mac_regs->miim) & PCH_GBE_MIIM_OPER_READY)
339 static int pch_gbe_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
341 struct pch_gbe_regs *mac_regs = bus->priv;
344 if (pch_gbe_mdio_ready(mac_regs))
347 miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
348 (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
349 PCH_GBE_MIIM_OPER_READ;
350 writel(miim, &mac_regs->miim);
352 if (pch_gbe_mdio_ready(mac_regs))
355 return readl(&mac_regs->miim) & 0xffff;
358 static int pch_gbe_mdio_write(struct mii_dev *bus, int addr, int devad,
361 struct pch_gbe_regs *mac_regs = bus->priv;
364 if (pch_gbe_mdio_ready(mac_regs))
367 miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
368 (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
369 PCH_GBE_MIIM_OPER_WRITE | val;
370 writel(miim, &mac_regs->miim);
372 if (pch_gbe_mdio_ready(mac_regs))
378 static int pch_gbe_mdio_init(const char *name, struct pch_gbe_regs *mac_regs)
384 debug("pch_gbe: failed to allocate MDIO bus\n");
388 bus->read = pch_gbe_mdio_read;
389 bus->write = pch_gbe_mdio_write;
390 strcpy(bus->name, name);
392 bus->priv = (void *)mac_regs;
394 return mdio_register(bus);
397 static int pch_gbe_phy_init(struct udevice *dev)
399 struct pch_gbe_priv *priv = dev_get_priv(dev);
400 struct eth_pdata *plat = dev_get_platdata(dev);
401 struct phy_device *phydev;
402 int mask = 0xffffffff;
404 phydev = phy_find_by_mask(priv->bus, mask, plat->phy_interface);
406 printf("pch_gbe: cannot find the phy\n");
410 phy_connect_dev(phydev, dev);
412 phydev->supported &= PHY_GBIT_FEATURES;
413 phydev->advertising = phydev->supported;
415 priv->phydev = phydev;
421 int pch_gbe_probe(struct udevice *dev)
423 struct pch_gbe_priv *priv;
424 struct eth_pdata *plat = dev_get_platdata(dev);
429 * The priv structure contains the descriptors and frame buffers which
430 * need a strict buswidth alignment (64 bytes). This is guaranteed by
431 * DM_FLAG_ALLOC_PRIV_DMA flag in the U_BOOT_DRIVER.
433 priv = dev_get_priv(dev);
437 iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, PCI_REGION_MEM);
439 plat->iobase = (ulong)iobase;
440 priv->mac_regs = (struct pch_gbe_regs *)iobase;
442 /* Read MAC address from SROM and initialize dev->enetaddr with it */
443 pch_gbe_mac_read(priv->mac_regs, plat->enetaddr);
445 plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
446 pch_gbe_mdio_init(dev->name, priv->mac_regs);
447 priv->bus = miiphy_get_dev_by_name(dev->name);
449 err = pch_gbe_reset(dev);
453 return pch_gbe_phy_init(dev);
456 int pch_gbe_remove(struct udevice *dev)
458 struct pch_gbe_priv *priv = dev_get_priv(dev);
461 mdio_unregister(priv->bus);
462 mdio_free(priv->bus);
467 static const struct eth_ops pch_gbe_ops = {
468 .start = pch_gbe_start,
469 .send = pch_gbe_send,
470 .recv = pch_gbe_recv,
471 .free_pkt = pch_gbe_free_pkt,
472 .stop = pch_gbe_stop,
475 static const struct udevice_id pch_gbe_ids[] = {
476 { .compatible = "intel,pch-gbe" },
480 U_BOOT_DRIVER(eth_pch_gbe) = {
483 .of_match = pch_gbe_ids,
484 .probe = pch_gbe_probe,
485 .remove = pch_gbe_remove,
487 .priv_auto_alloc_size = sizeof(struct pch_gbe_priv),
488 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
489 .flags = DM_FLAG_ALLOC_PRIV_DMA,
492 U_BOOT_PCI_DEVICE(eth_pch_gbe, supported);