4 * Florian Fainelli <f.fainelli@gmail.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 * PHY driver for Broadcom BCM53xx (roboswitch) Ethernet switches.
12 * This driver configures the b53 for basic use as a PHY. The switch supports
13 * vendor tags and VLAN configuration that can affect the switching decisions.
14 * This driver uses a simple configuration in which all ports are only allowed
15 * to send frames to the CPU port and receive frames from the CPU port this
16 * providing port isolation (no cross talk).
18 * The configuration determines which PHY ports to activate using the
19 * CONFIG_B53_PHY_PORTS bitmask. Set bit N will active port N and so on.
21 * This driver was written primarily for the Lamobo R1 platform using a BCM53152
22 * switch but the BCM53xx being largely register compatible, extending it to
23 * cover other switches would be trivial.
33 /* Pseudo-PHY address (non configurable) to access internal registers */
34 #define BRCM_PSEUDO_PHY_ADDR 30
36 /* Maximum number of ports possible */
39 #define B53_CTRL_PAGE 0x00 /* Control */
40 #define B53_MGMT_PAGE 0x02 /* Management Mode */
42 #define B53_PVLAN_PAGE 0x31
44 /* Control Page registers */
45 #define B53_PORT_CTRL(i) (0x00 + (i))
46 #define PORT_CTRL_RX_DISABLE BIT(0)
47 #define PORT_CTRL_TX_DISABLE BIT(1)
48 #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */
49 #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */
50 #define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */
52 /* Switch Mode Control Register (8 bit) */
53 #define B53_SWITCH_MODE 0x0b
54 #define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */
55 #define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */
57 /* IMP Port state override register (8 bit) */
58 #define B53_PORT_OVERRIDE_CTRL 0x0e
59 #define PORT_OVERRIDE_LINK BIT(0)
60 #define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */
61 #define PORT_OVERRIDE_SPEED_S 2
62 #define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S)
63 #define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S)
64 #define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S)
66 #define PORT_OVERRIDE_RV_MII_25 BIT(4)
67 #define PORT_OVERRIDE_RX_FLOW BIT(4)
68 #define PORT_OVERRIDE_TX_FLOW BIT(5)
69 /* BCM5301X only, requires setting 1000M */
70 #define PORT_OVERRIDE_SPEED_2000M BIT(6)
71 #define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */
73 #define B53_RGMII_CTRL_IMP 0x60
74 #define RGMII_CTRL_ENABLE_GMII BIT(7)
75 #define RGMII_CTRL_TIMING_SEL BIT(2)
76 #define RGMII_CTRL_DLL_RXC BIT(1)
77 #define RGMII_CTRL_DLL_TXC BIT(0)
79 /* Switch control (8 bit) */
80 #define B53_SWITCH_CTRL 0x22
81 #define B53_MII_DUMB_FWDG_EN BIT(6)
83 /* Software reset register (8 bit) */
84 #define B53_SOFTRESET 0x79
86 #define EN_CH_RST BIT(6)
87 #define EN_SW_RST BIT(4)
89 /* Fast Aging Control register (8 bit) */
90 #define B53_FAST_AGE_CTRL 0x88
91 #define FAST_AGE_STATIC BIT(0)
92 #define FAST_AGE_DYNAMIC BIT(1)
93 #define FAST_AGE_PORT BIT(2)
94 #define FAST_AGE_VLAN BIT(3)
95 #define FAST_AGE_STP BIT(4)
96 #define FAST_AGE_MC BIT(5)
97 #define FAST_AGE_DONE BIT(7)
99 /* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */
100 #define B53_PVLAN_PORT_MASK(i) ((i) * 2)
103 #define REG_MII_PAGE 0x10 /* MII Page register */
104 #define REG_MII_ADDR 0x11 /* MII Address register */
105 #define REG_MII_DATA0 0x18 /* MII Data register 0 */
106 #define REG_MII_DATA1 0x19 /* MII Data register 1 */
107 #define REG_MII_DATA2 0x1a /* MII Data register 2 */
108 #define REG_MII_DATA3 0x1b /* MII Data register 3 */
110 #define REG_MII_PAGE_ENABLE BIT(0)
111 #define REG_MII_ADDR_WRITE BIT(0)
112 #define REG_MII_ADDR_READ BIT(1)
116 unsigned int cpu_port;
119 static int b53_mdio_op(struct mii_dev *bus, u8 page, u8 reg, u16 op)
125 /* set page number */
126 v = (page << 8) | REG_MII_PAGE_ENABLE;
127 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
132 /* set register address */
134 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
139 /* check if operation completed */
140 for (i = 0; i < 5; ++i) {
141 v = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
143 if (!(v & (REG_MII_ADDR_WRITE | REG_MII_ADDR_READ)))
155 static int b53_mdio_read8(struct mii_dev *bus, u8 page, u8 reg, u8 *val)
159 ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
163 *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
164 REG_MII_DATA0) & 0xff;
169 static int b53_mdio_read16(struct mii_dev *bus, u8 page, u8 reg, u16 *val)
173 ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
177 *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
183 static int b53_mdio_read32(struct mii_dev *bus, u8 page, u8 reg, u32 *val)
187 ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
191 *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
193 *val |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
194 REG_MII_DATA1) << 16;
199 static int b53_mdio_read48(struct mii_dev *bus, u8 page, u8 reg, u64 *val)
205 ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
209 for (i = 2; i >= 0; i--) {
211 temp |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
220 static int b53_mdio_read64(struct mii_dev *bus, u8 page, u8 reg, u64 *val)
226 ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
230 for (i = 3; i >= 0; i--) {
232 temp |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
241 static int b53_mdio_write8(struct mii_dev *bus, u8 page, u8 reg, u8 value)
245 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
246 REG_MII_DATA0, value);
250 return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
253 static int b53_mdio_write16(struct mii_dev *bus, u8 page, u8 reg,
258 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
259 REG_MII_DATA0, value);
263 return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
266 static int b53_mdio_write32(struct mii_dev *bus, u8 page, u8 reg,
272 for (i = 0; i < 2; i++) {
273 int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR,
275 REG_MII_DATA0 + i, temp & 0xffff);
281 return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
284 static int b53_mdio_write48(struct mii_dev *bus, u8 page, u8 reg,
290 for (i = 0; i < 3; i++) {
291 int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR,
293 REG_MII_DATA0 + i, temp & 0xffff);
299 return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
302 static int b53_mdio_write64(struct mii_dev *bus, u8 page, u8 reg,
308 for (i = 0; i < 4; i++) {
309 int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR,
311 REG_MII_DATA0 + i, temp & 0xffff);
317 return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
320 static inline int b53_read8(struct b53_device *dev, u8 page,
323 return b53_mdio_read8(dev->bus, page, reg, value);
326 static inline int b53_read16(struct b53_device *dev, u8 page,
329 return b53_mdio_read16(dev->bus, page, reg, value);
332 static inline int b53_read32(struct b53_device *dev, u8 page,
335 return b53_mdio_read32(dev->bus, page, reg, value);
338 static inline int b53_read48(struct b53_device *dev, u8 page,
341 return b53_mdio_read48(dev->bus, page, reg, value);
344 static inline int b53_read64(struct b53_device *dev, u8 page,
347 return b53_mdio_read64(dev->bus, page, reg, value);
350 static inline int b53_write8(struct b53_device *dev, u8 page,
353 return b53_mdio_write8(dev->bus, page, reg, value);
356 static inline int b53_write16(struct b53_device *dev, u8 page,
359 return b53_mdio_write16(dev->bus, page, reg, value);
362 static inline int b53_write32(struct b53_device *dev, u8 page,
365 return b53_mdio_write32(dev->bus, page, reg, value);
368 static inline int b53_write48(struct b53_device *dev, u8 page,
371 return b53_mdio_write48(dev->bus, page, reg, value);
374 static inline int b53_write64(struct b53_device *dev, u8 page,
377 return b53_mdio_write64(dev->bus, page, reg, value);
380 static int b53_flush_arl(struct b53_device *dev, u8 mask)
384 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
385 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
387 for (i = 0; i < 10; i++) {
390 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
393 if (!(fast_age_ctrl & FAST_AGE_DONE))
401 /* Only age dynamic entries (default behavior) */
402 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
406 static int b53_switch_reset(struct phy_device *phydev)
408 struct b53_device *dev = phydev->priv;
409 unsigned int timeout = 1000;
413 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
414 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
415 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
418 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
423 } while (timeout-- > 0);
428 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
430 if (!(mgmt & SM_SW_FWD_EN)) {
431 mgmt &= ~SM_SW_FWD_MODE;
432 mgmt |= SM_SW_FWD_EN;
434 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
435 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
437 if (!(mgmt & SM_SW_FWD_EN)) {
438 printf("Failed to enable switch!\n");
443 /* Include IMP port in dumb forwarding mode when no tagging protocol
446 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
447 mgmt |= B53_MII_DUMB_FWDG_EN;
448 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
450 return b53_flush_arl(dev, FAST_AGE_STATIC);
453 static void b53_enable_cpu_port(struct phy_device *phydev)
455 struct b53_device *dev = phydev->priv;
458 port_ctrl = PORT_CTRL_RX_BCST_EN |
459 PORT_CTRL_RX_MCST_EN |
460 PORT_CTRL_RX_UCST_EN;
461 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(dev->cpu_port), port_ctrl);
463 port_ctrl = PORT_OVERRIDE_EN | PORT_OVERRIDE_LINK |
464 PORT_OVERRIDE_FULL_DUPLEX | PORT_OVERRIDE_SPEED_1000M;
465 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, port_ctrl);
467 b53_read8(dev, B53_CTRL_PAGE, B53_RGMII_CTRL_IMP, &port_ctrl);
470 static void b53_imp_vlan_setup(struct b53_device *dev, int cpu_port)
475 /* Enable the IMP port to be in the same VLAN as the other ports
476 * on a per-port basis such that we only have Port i and IMP in
479 for (port = 0; port < B53_N_PORTS; port++) {
480 if (!((1 << port) & CONFIG_B53_PHY_PORTS))
483 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port),
485 pvlan |= BIT(cpu_port);
486 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port),
491 static int b53_port_enable(struct phy_device *phydev, unsigned int port)
493 struct b53_device *dev = phydev->priv;
494 unsigned int cpu_port = dev->cpu_port;
497 /* Clear the Rx and Tx disable bits and set to no spanning tree */
498 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
500 /* Set this port, and only this one to be in the default VLAN */
501 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
504 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
506 b53_imp_vlan_setup(dev, cpu_port);
511 static int b53_switch_init(struct phy_device *phydev)
519 ret = b53_switch_reset(phydev);
523 b53_enable_cpu_port(phydev);
530 static int b53_probe(struct phy_device *phydev)
532 struct b53_device *dev;
535 dev = malloc(sizeof(*dev));
539 memset(dev, 0, sizeof(*dev));
542 dev->bus = phydev->bus;
543 dev->cpu_port = CONFIG_B53_CPU_PORT;
545 ret = b53_switch_reset(phydev);
552 static int b53_phy_config(struct phy_device *phydev)
557 res = b53_switch_init(phydev);
561 for (port = 0; port < B53_N_PORTS; port++) {
562 if (!((1 << port) & CONFIG_B53_PHY_PORTS))
565 res = b53_port_enable(phydev, port);
567 printf("Error enabling port %i\n", port);
571 res = genphy_config_aneg(phydev);
573 printf("Error setting PHY %i autoneg\n", port);
583 static int b53_phy_startup(struct phy_device *phydev)
588 for (port = 0; port < B53_N_PORTS; port++) {
589 if (!((1 << port) & CONFIG_B53_PHY_PORTS))
594 res = genphy_startup(phydev);
601 /* Since we are connected directly to the switch, hardcode the link
602 * parameters to match those of the CPU port configured in
603 * b53_enable_cpu_port, we cannot be dependent on the user-facing port
604 * settings (e.g: 100Mbits/sec would not work here)
606 phydev->speed = 1000;
613 static struct phy_driver b53_driver = {
614 .name = "Broadcom BCM53125",
617 .features = PHY_GBIT_FEATURES,
619 .config = b53_phy_config,
620 .startup = b53_phy_startup,
621 .shutdown = &genphy_shutdown,
624 int phy_b53_init(void)
626 phy_register(&b53_driver);
631 int do_b53_reg_read(const char *name, int argc, char * const argv[])
633 u8 page, offset, width;
641 bus = miiphy_get_dev_by_name(name);
643 printf("unable to find MDIO bus: %s\n", name);
647 page = simple_strtoul(argv[1], NULL, 16);
648 offset = simple_strtoul(argv[2], NULL, 16);
649 width = simple_strtoul(argv[3], NULL, 10);
653 ret = b53_mdio_read8(bus, page, offset, &value8);
654 printf("page=0x%02x, offset=0x%02x, value=0x%02x\n",
655 page, offset, value8);
658 ret = b53_mdio_read16(bus, page, offset, &value16);
659 printf("page=0x%02x, offset=0x%02x, value=0x%04x\n",
660 page, offset, value16);
663 ret = b53_mdio_read32(bus, page, offset, &value32);
664 printf("page=0x%02x, offset=0x%02x, value=0x%08x\n",
665 page, offset, value32);
668 ret = b53_mdio_read48(bus, page, offset, &value64);
669 printf("page=0x%02x, offset=0x%02x, value=0x%012llx\n",
670 page, offset, value64);
673 ret = b53_mdio_read48(bus, page, offset, &value64);
674 printf("page=0x%02x, offset=0x%02x, value=0x%016llx\n",
675 page, offset, value64);
678 printf("Unsupported width: %d\n", width);
685 int do_b53_reg_write(const char *name, int argc, char * const argv[])
687 u8 page, offset, width;
693 bus = miiphy_get_dev_by_name(name);
695 printf("unable to find MDIO bus: %s\n", name);
699 page = simple_strtoul(argv[1], NULL, 16);
700 offset = simple_strtoul(argv[2], NULL, 16);
701 width = simple_strtoul(argv[3], NULL, 10);
702 if (width == 48 || width == 64)
703 value64 = simple_strtoull(argv[4], NULL, 16);
705 value = simple_strtoul(argv[4], NULL, 16);
709 ret = b53_mdio_write8(bus, page, offset, value & 0xff);
712 ret = b53_mdio_write16(bus, page, offset, value);
715 ret = b53_mdio_write32(bus, page, offset, value);
718 ret = b53_mdio_write48(bus, page, offset, value64);
721 ret = b53_mdio_write64(bus, page, offset, value64);
724 printf("Unsupported width: %d\n", width);
731 int do_b53_reg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
733 const char *cmd, *mdioname;
737 return cmd_usage(cmdtp);
743 if (!strcmp(cmd, "write")) {
745 return cmd_usage(cmdtp);
749 ret = do_b53_reg_write(mdioname, argc, argv);
750 } else if (!strcmp(cmd, "read")) {
752 return cmd_usage(cmdtp);
756 ret = do_b53_reg_read(mdioname, argc, argv);
758 return cmd_usage(cmdtp);
764 U_BOOT_CMD(b53_reg, 7, 1, do_b53_reg,
765 "Broadcom B53 switch register access",
766 "write mdioname page (hex) offset (hex) width (dec) value (hex)\n"
767 "read mdioname page (hex) offset (hex) width (dec)\n"