4 * SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2010-2011 Freescale Semiconductor, Inc.
14 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
16 #define MII_MARVELL_PHY_PAGE 22
18 /* 88E1011 PHY Status Register */
19 #define MIIM_88E1xxx_PHY_STATUS 0x11
20 #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000
21 #define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000
22 #define MIIM_88E1xxx_PHYSTAT_100 0x4000
23 #define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000
24 #define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800
25 #define MIIM_88E1xxx_PHYSTAT_LINK 0x0400
27 #define MIIM_88E1xxx_PHY_SCR 0x10
28 #define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060
30 /* 88E1111 PHY LED Control Register */
31 #define MIIM_88E1111_PHY_LED_CONTROL 24
32 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100
33 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C
35 /* 88E1111 Extended PHY Specific Control Register */
36 #define MIIM_88E1111_PHY_EXT_CR 0x14
37 #define MIIM_88E1111_RX_DELAY 0x80
38 #define MIIM_88E1111_TX_DELAY 0x2
40 /* 88E1111 Extended PHY Specific Status Register */
41 #define MIIM_88E1111_PHY_EXT_SR 0x1b
42 #define MIIM_88E1111_HWCFG_MODE_MASK 0xf
43 #define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb
44 #define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3
45 #define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4
46 #define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9
47 #define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000
48 #define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000
50 #define MIIM_88E1111_COPPER 0
51 #define MIIM_88E1111_FIBER 1
53 /* 88E1118 PHY defines */
54 #define MIIM_88E1118_PHY_PAGE 22
55 #define MIIM_88E1118_PHY_LED_PAGE 3
57 /* 88E1121 PHY LED Control Register */
58 #define MIIM_88E1121_PHY_LED_CTRL 16
59 #define MIIM_88E1121_PHY_LED_PAGE 3
60 #define MIIM_88E1121_PHY_LED_DEF 0x0030
62 /* 88E1121 PHY IRQ Enable/Status Register */
63 #define MIIM_88E1121_PHY_IRQ_EN 18
64 #define MIIM_88E1121_PHY_IRQ_STATUS 19
66 #define MIIM_88E1121_PHY_PAGE 22
68 /* 88E1145 Extended PHY Specific Control Register */
69 #define MIIM_88E1145_PHY_EXT_CR 20
70 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
71 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
73 #define MIIM_88E1145_PHY_LED_CONTROL 24
74 #define MIIM_88E1145_PHY_LED_DIRECT 0x4100
76 #define MIIM_88E1145_PHY_PAGE 29
77 #define MIIM_88E1145_PHY_CAL_OV 30
79 #define MIIM_88E1149_PHY_PAGE 29
81 /* 88E1310 PHY defines */
82 #define MIIM_88E1310_PHY_LED_CTRL 16
83 #define MIIM_88E1310_PHY_IRQ_EN 18
84 #define MIIM_88E1310_PHY_RGMII_CTRL 21
85 #define MIIM_88E1310_PHY_PAGE 22
87 /* 88E151x PHY defines */
88 /* Page 2 registers */
89 #define MIIM_88E151x_PHY_MSCR 21
90 #define MIIM_88E151x_RGMII_RX_DELAY BIT(5)
91 #define MIIM_88E151x_RGMII_TX_DELAY BIT(4)
92 #define MIIM_88E151x_RGMII_RXTX_DELAY (BIT(5) | BIT(4))
93 /* Page 3 registers */
94 #define MIIM_88E151x_LED_FUNC_CTRL 16
95 #define MIIM_88E151x_LED_FLD_SZ 4
96 #define MIIM_88E151x_LED0_OFFS (0 * MIIM_88E151x_LED_FLD_SZ)
97 #define MIIM_88E151x_LED1_OFFS (1 * MIIM_88E151x_LED_FLD_SZ)
98 #define MIIM_88E151x_LED0_ACT 3
99 #define MIIM_88E151x_LED1_100_1000_LINK 6
100 #define MIIM_88E151x_LED_TIMER_CTRL 18
101 #define MIIM_88E151x_INT_EN_OFFS 7
102 /* Page 18 registers */
103 #define MIIM_88E151x_GENERAL_CTRL 20
104 #define MIIM_88E151x_MODE_SGMII 1
105 #define MIIM_88E151x_RESET_OFFS 15
107 static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr,
108 int devaddr, int regnum)
110 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
113 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
114 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
115 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
120 static int m88e1xxx_phy_extwrite(struct phy_device *phydev, int addr,
121 int devaddr, int regnum, u16 val)
123 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
125 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
126 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
127 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
132 /* Marvell 88E1011S */
133 static int m88e1011s_config(struct phy_device *phydev)
135 /* Reset and configure the PHY */
136 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
138 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
139 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
140 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
141 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0);
142 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
144 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
146 genphy_config_aneg(phydev);
151 /* Parse the 88E1011's status register for speed and duplex
154 static int m88e1xxx_parse_status(struct phy_device *phydev)
157 unsigned int mii_reg;
159 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);
161 if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) &&
162 !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
165 puts("Waiting for PHY realtime link");
166 while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
167 /* Timeout reached ? */
168 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
169 puts(" TIMEOUT !\n");
174 if ((i++ % 1000) == 0)
177 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
178 MIIM_88E1xxx_PHY_STATUS);
181 mdelay(500); /* another 500 ms (results in faster booting) */
183 if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK)
189 if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX)
190 phydev->duplex = DUPLEX_FULL;
192 phydev->duplex = DUPLEX_HALF;
194 speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED;
197 case MIIM_88E1xxx_PHYSTAT_GBIT:
198 phydev->speed = SPEED_1000;
200 case MIIM_88E1xxx_PHYSTAT_100:
201 phydev->speed = SPEED_100;
204 phydev->speed = SPEED_10;
211 static int m88e1011s_startup(struct phy_device *phydev)
215 ret = genphy_update_link(phydev);
219 return m88e1xxx_parse_status(phydev);
222 /* Marvell 88E1111S */
223 static int m88e1111s_config(struct phy_device *phydev)
227 if (phy_interface_is_rgmii(phydev)) {
228 reg = phy_read(phydev,
229 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
230 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
231 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
232 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
233 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
234 reg &= ~MIIM_88E1111_TX_DELAY;
235 reg |= MIIM_88E1111_RX_DELAY;
236 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
237 reg &= ~MIIM_88E1111_RX_DELAY;
238 reg |= MIIM_88E1111_TX_DELAY;
242 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
244 reg = phy_read(phydev,
245 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
247 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
249 if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
250 reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
252 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
255 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg);
258 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
259 reg = phy_read(phydev,
260 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
262 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
263 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
264 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
266 phy_write(phydev, MDIO_DEVAD_NONE,
267 MIIM_88E1111_PHY_EXT_SR, reg);
270 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
271 reg = phy_read(phydev,
272 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
273 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
275 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
277 reg = phy_read(phydev, MDIO_DEVAD_NONE,
278 MIIM_88E1111_PHY_EXT_SR);
279 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
280 MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
281 reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
282 phy_write(phydev, MDIO_DEVAD_NONE,
283 MIIM_88E1111_PHY_EXT_SR, reg);
288 reg = phy_read(phydev, MDIO_DEVAD_NONE,
289 MIIM_88E1111_PHY_EXT_SR);
290 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
291 MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
292 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
293 MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
294 phy_write(phydev, MDIO_DEVAD_NONE,
295 MIIM_88E1111_PHY_EXT_SR, reg);
301 genphy_config_aneg(phydev);
302 genphy_restart_aneg(phydev);
308 * m88e1518_phy_writebits - write bits to a register
310 void m88e1518_phy_writebits(struct phy_device *phydev,
311 u8 reg_num, u16 offset, u16 len, u16 data)
315 if ((len + offset) >= 16)
316 mask = 0 - (1 << offset);
318 mask = (1 << (len + offset)) - (1 << offset);
320 reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
323 reg |= data << offset;
325 phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
328 static int m88e1518_config(struct phy_device *phydev)
333 * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
334 * /88E1514 Rev A0, Errata Section 3.1
337 /* EEE initialization */
338 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff);
339 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
340 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
341 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
342 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
343 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
344 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
345 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
346 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
347 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
349 /* SGMII-to-Copper mode initialization */
350 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
352 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 18);
354 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
355 m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
356 0, 3, MIIM_88E151x_MODE_SGMII);
358 /* PHY reset is necessary after changing MODE[2:0] */
359 m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
360 MIIM_88E151x_RESET_OFFS, 1, 1);
362 /* Reset page selection */
363 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0);
368 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
369 reg = phy_read(phydev, MDIO_DEVAD_NONE,
370 MIIM_88E1111_PHY_EXT_SR);
372 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
373 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
374 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
376 phy_write(phydev, MDIO_DEVAD_NONE,
377 MIIM_88E1111_PHY_EXT_SR, reg);
380 if (phy_interface_is_rgmii(phydev)) {
381 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 2);
383 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR);
384 reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY;
385 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
386 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
387 reg |= MIIM_88E151x_RGMII_RXTX_DELAY;
388 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
389 reg |= MIIM_88E151x_RGMII_RX_DELAY;
390 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
391 reg |= MIIM_88E151x_RGMII_TX_DELAY;
392 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR, reg);
394 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 0);
400 genphy_config_aneg(phydev);
401 genphy_restart_aneg(phydev);
406 /* Marvell 88E1510 */
407 static int m88e1510_config(struct phy_device *phydev)
410 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE,
411 MIIM_88E1118_PHY_LED_PAGE);
413 /* Enable INTn output on LED[2] */
414 m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_TIMER_CTRL,
415 MIIM_88E151x_INT_EN_OFFS, 1, 1);
418 /* LED[0]:0011 (ACT) */
419 m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL,
420 MIIM_88E151x_LED0_OFFS, MIIM_88E151x_LED_FLD_SZ,
421 MIIM_88E151x_LED0_ACT);
422 /* LED[1]:0110 (LINK 100/1000 Mbps) */
423 m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL,
424 MIIM_88E151x_LED1_OFFS, MIIM_88E151x_LED_FLD_SZ,
425 MIIM_88E151x_LED1_100_1000_LINK);
427 /* Reset page selection */
428 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0);
430 return m88e1518_config(phydev);
433 /* Marvell 88E1118 */
434 static int m88e1118_config(struct phy_device *phydev)
436 /* Change Page Number */
437 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002);
438 /* Delay RGMII TX and RX */
439 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070);
440 /* Change Page Number */
441 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003);
442 /* Adjust LED control */
443 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e);
444 /* Change Page Number */
445 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
447 return genphy_config_aneg(phydev);
450 static int m88e1118_startup(struct phy_device *phydev)
454 /* Change Page Number */
455 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
457 ret = genphy_update_link(phydev);
461 return m88e1xxx_parse_status(phydev);
464 /* Marvell 88E1121R */
465 static int m88e1121_config(struct phy_device *phydev)
469 /* Configure the PHY */
470 genphy_config_aneg(phydev);
472 /* Switch the page to access the led register */
473 pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE);
474 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE,
475 MIIM_88E1121_PHY_LED_PAGE);
477 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL,
478 MIIM_88E1121_PHY_LED_DEF);
479 /* Restore the page pointer */
480 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg);
482 /* Disable IRQs and de-assert interrupt */
483 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0);
484 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS);
489 /* Marvell 88E1145 */
490 static int m88e1145_config(struct phy_device *phydev)
495 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b);
496 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f);
497 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016);
498 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da);
500 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR,
501 MIIM_88E1xxx_PHY_MDI_X_AUTO);
503 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR);
504 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
505 reg |= MIIM_M88E1145_RGMII_RX_DELAY |
506 MIIM_M88E1145_RGMII_TX_DELAY;
507 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg);
509 genphy_config_aneg(phydev);
512 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
514 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
519 static int m88e1145_startup(struct phy_device *phydev)
523 ret = genphy_update_link(phydev);
527 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
528 MIIM_88E1145_PHY_LED_DIRECT);
529 return m88e1xxx_parse_status(phydev);
532 /* Marvell 88E1149S */
533 static int m88e1149_config(struct phy_device *phydev)
535 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f);
536 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
537 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5);
538 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0);
539 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
541 genphy_config_aneg(phydev);
548 /* Marvell 88E1310 */
549 static int m88e1310_config(struct phy_device *phydev)
553 /* LED link and activity */
554 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
555 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
556 reg = (reg & ~0xf) | 0x1;
557 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
559 /* Set LED2/INT to INT mode, low active */
560 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
561 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
562 reg = (reg & 0x77ff) | 0x0880;
563 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
565 /* Set RGMII delay */
566 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
567 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
569 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
571 /* Ensure to return to page 0 */
572 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
574 return genphy_config_aneg(phydev);
577 static int m88e1680_config(struct phy_device *phydev)
580 * As per Marvell Release Notes - Alaska V 88E1680 Rev A2
586 /* Matrix LED mode (not neede if single LED mode is used */
587 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0004);
588 reg = phy_read(phydev, MDIO_DEVAD_NONE, 27);
590 phy_write(phydev, MDIO_DEVAD_NONE, 27, reg);
592 /* QSGMII TX amplitude change */
593 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00fd);
594 phy_write(phydev, MDIO_DEVAD_NONE, 8, 0x0b53);
595 phy_write(phydev, MDIO_DEVAD_NONE, 7, 0x200d);
596 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
598 /* EEE initialization */
599 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff);
600 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xb030);
601 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x215c);
602 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00fc);
603 phy_write(phydev, MDIO_DEVAD_NONE, 24, 0x888c);
604 phy_write(phydev, MDIO_DEVAD_NONE, 25, 0x888c);
605 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
606 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
608 res = genphy_config_aneg(phydev);
613 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
615 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
620 static struct phy_driver M88E1011S_driver = {
621 .name = "Marvell 88E1011S",
624 .features = PHY_GBIT_FEATURES,
625 .config = &m88e1011s_config,
626 .startup = &m88e1011s_startup,
627 .shutdown = &genphy_shutdown,
630 static struct phy_driver M88E1111S_driver = {
631 .name = "Marvell 88E1111S",
634 .features = PHY_GBIT_FEATURES,
635 .config = &m88e1111s_config,
636 .startup = &m88e1011s_startup,
637 .shutdown = &genphy_shutdown,
640 static struct phy_driver M88E1118_driver = {
641 .name = "Marvell 88E1118",
644 .features = PHY_GBIT_FEATURES,
645 .config = &m88e1118_config,
646 .startup = &m88e1118_startup,
647 .shutdown = &genphy_shutdown,
650 static struct phy_driver M88E1118R_driver = {
651 .name = "Marvell 88E1118R",
654 .features = PHY_GBIT_FEATURES,
655 .config = &m88e1118_config,
656 .startup = &m88e1118_startup,
657 .shutdown = &genphy_shutdown,
660 static struct phy_driver M88E1121R_driver = {
661 .name = "Marvell 88E1121R",
664 .features = PHY_GBIT_FEATURES,
665 .config = &m88e1121_config,
666 .startup = &genphy_startup,
667 .shutdown = &genphy_shutdown,
670 static struct phy_driver M88E1145_driver = {
671 .name = "Marvell 88E1145",
674 .features = PHY_GBIT_FEATURES,
675 .config = &m88e1145_config,
676 .startup = &m88e1145_startup,
677 .shutdown = &genphy_shutdown,
680 static struct phy_driver M88E1149S_driver = {
681 .name = "Marvell 88E1149S",
684 .features = PHY_GBIT_FEATURES,
685 .config = &m88e1149_config,
686 .startup = &m88e1011s_startup,
687 .shutdown = &genphy_shutdown,
690 static struct phy_driver M88E1510_driver = {
691 .name = "Marvell 88E1510",
694 .features = PHY_GBIT_FEATURES,
695 .config = &m88e1510_config,
696 .startup = &m88e1011s_startup,
697 .shutdown = &genphy_shutdown,
698 .readext = &m88e1xxx_phy_extread,
699 .writeext = &m88e1xxx_phy_extwrite,
704 * 88E1518, uid 0x1410dd1
705 * 88E1512, uid 0x1410dd4
707 static struct phy_driver M88E1518_driver = {
708 .name = "Marvell 88E1518",
711 .features = PHY_GBIT_FEATURES,
712 .config = &m88e1518_config,
713 .startup = &m88e1011s_startup,
714 .shutdown = &genphy_shutdown,
715 .readext = &m88e1xxx_phy_extread,
716 .writeext = &m88e1xxx_phy_extwrite,
719 static struct phy_driver M88E1310_driver = {
720 .name = "Marvell 88E1310",
723 .features = PHY_GBIT_FEATURES,
724 .config = &m88e1310_config,
725 .startup = &m88e1011s_startup,
726 .shutdown = &genphy_shutdown,
729 static struct phy_driver M88E1680_driver = {
730 .name = "Marvell 88E1680",
733 .features = PHY_GBIT_FEATURES,
734 .config = &m88e1680_config,
735 .startup = &genphy_startup,
736 .shutdown = &genphy_shutdown,
739 int phy_marvell_init(void)
741 phy_register(&M88E1310_driver);
742 phy_register(&M88E1149S_driver);
743 phy_register(&M88E1145_driver);
744 phy_register(&M88E1121R_driver);
745 phy_register(&M88E1118_driver);
746 phy_register(&M88E1118R_driver);
747 phy_register(&M88E1111S_driver);
748 phy_register(&M88E1011S_driver);
749 phy_register(&M88E1510_driver);
750 phy_register(&M88E1518_driver);
751 phy_register(&M88E1680_driver);