git.sur5r.net Git - u-boot/blob - drivers/net/phy/marvell.c

   1 /*
   2  * Marvell PHY drivers
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   7  * author Andy Fleming
   8  */
   9 #include <config.h>
  10 #include <common.h>
  11 #include <phy.h>
  12
  13 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
  14
  15 /* 88E1011 PHY Status Register */
  16 #define MIIM_88E1xxx_PHY_STATUS         0x11
  17 #define MIIM_88E1xxx_PHYSTAT_SPEED      0xc000
  18 #define MIIM_88E1xxx_PHYSTAT_GBIT       0x8000
  19 #define MIIM_88E1xxx_PHYSTAT_100        0x4000
  20 #define MIIM_88E1xxx_PHYSTAT_DUPLEX     0x2000
  21 #define MIIM_88E1xxx_PHYSTAT_SPDDONE    0x0800
  22 #define MIIM_88E1xxx_PHYSTAT_LINK       0x0400
  23
  24 #define MIIM_88E1xxx_PHY_SCR            0x10
  25 #define MIIM_88E1xxx_PHY_MDI_X_AUTO     0x0060
  26
  27 /* 88E1111 PHY LED Control Register */
  28 #define MIIM_88E1111_PHY_LED_CONTROL    24
  29 #define MIIM_88E1111_PHY_LED_DIRECT     0x4100
  30 #define MIIM_88E1111_PHY_LED_COMBINE    0x411C
  31
  32 /* 88E1111 Extended PHY Specific Control Register */
  33 #define MIIM_88E1111_PHY_EXT_CR         0x14
  34 #define MIIM_88E1111_RX_DELAY           0x80
  35 #define MIIM_88E1111_TX_DELAY           0x2
  36
  37 /* 88E1111 Extended PHY Specific Status Register */
  38 #define MIIM_88E1111_PHY_EXT_SR         0x1b
  39 #define MIIM_88E1111_HWCFG_MODE_MASK            0xf
  40 #define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII    0xb
  41 #define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII     0x3
  42 #define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK    0x4
  43 #define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI     0x9
  44 #define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO    0x8000
  45 #define MIIM_88E1111_HWCFG_FIBER_COPPER_RES     0x2000
  46
  47 #define MIIM_88E1111_COPPER             0
  48 #define MIIM_88E1111_FIBER              1
  49
  50 /* 88E1118 PHY defines */
  51 #define MIIM_88E1118_PHY_PAGE           22
  52 #define MIIM_88E1118_PHY_LED_PAGE       3
  53
  54 /* 88E1121 PHY LED Control Register */
  55 #define MIIM_88E1121_PHY_LED_CTRL       16
  56 #define MIIM_88E1121_PHY_LED_PAGE       3
  57 #define MIIM_88E1121_PHY_LED_DEF        0x0030
  58
  59 /* 88E1121 PHY IRQ Enable/Status Register */
  60 #define MIIM_88E1121_PHY_IRQ_EN         18
  61 #define MIIM_88E1121_PHY_IRQ_STATUS     19
  62
  63 #define MIIM_88E1121_PHY_PAGE           22
  64
  65 /* 88E1145 Extended PHY Specific Control Register */
  66 #define MIIM_88E1145_PHY_EXT_CR 20
  67 #define MIIM_M88E1145_RGMII_RX_DELAY    0x0080
  68 #define MIIM_M88E1145_RGMII_TX_DELAY    0x0002
  69
  70 #define MIIM_88E1145_PHY_LED_CONTROL    24
  71 #define MIIM_88E1145_PHY_LED_DIRECT     0x4100
  72
  73 #define MIIM_88E1145_PHY_PAGE   29
  74 #define MIIM_88E1145_PHY_CAL_OV 30
  75
  76 #define MIIM_88E1149_PHY_PAGE   29
  77
  78 /* 88E1310 PHY defines */
  79 #define MIIM_88E1310_PHY_LED_CTRL       16
  80 #define MIIM_88E1310_PHY_IRQ_EN         18
  81 #define MIIM_88E1310_PHY_RGMII_CTRL     21
  82 #define MIIM_88E1310_PHY_PAGE           22
  83
  84 /* Marvell 88E1011S */
  85 static int m88e1011s_config(struct phy_device *phydev)
  86 {
  87         /* Reset and configure the PHY */
  88         phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
  89
  90         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  91         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
  92         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  93         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0);
  94         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  95
  96         phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
  97
  98         genphy_config_aneg(phydev);
  99
 100         return 0;
 101 }
 102
 103 /* Parse the 88E1011's status register for speed and duplex
 104  * information
 105  */
 106 static int m88e1xxx_parse_status(struct phy_device *phydev)
 107 {
 108         unsigned int speed;
 109         unsigned int mii_reg;
 110
 111         mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);
 112
 113         if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) &&
 114                 !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
 115                 int i = 0;
 116
 117                 puts("Waiting for PHY realtime link");
 118                 while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
 119                         /* Timeout reached ? */
 120                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 121                                 puts(" TIMEOUT !\n");
 122                                 phydev->link = 0;
 123                                 return -ETIMEDOUT;
 124                         }
 125
 126                         if ((i++ % 1000) == 0)
 127                                 putc('.');
 128                         udelay(1000);
 129                         mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
 130                                         MIIM_88E1xxx_PHY_STATUS);
 131                 }
 132                 puts(" done\n");
 133                 udelay(500000); /* another 500 ms (results in faster booting) */
 134         } else {
 135                 if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK)
 136                         phydev->link = 1;
 137                 else
 138                         phydev->link = 0;
 139         }
 140
 141         if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX)
 142                 phydev->duplex = DUPLEX_FULL;
 143         else
 144                 phydev->duplex = DUPLEX_HALF;
 145
 146         speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED;
 147
 148         switch (speed) {
 149         case MIIM_88E1xxx_PHYSTAT_GBIT:
 150                 phydev->speed = SPEED_1000;
 151                 break;
 152         case MIIM_88E1xxx_PHYSTAT_100:
 153                 phydev->speed = SPEED_100;
 154                 break;
 155         default:
 156                 phydev->speed = SPEED_10;
 157                 break;
 158         }
 159
 160         return 0;
 161 }
 162
 163 static int m88e1011s_startup(struct phy_device *phydev)
 164 {
 165         int ret;
 166
 167         ret = genphy_update_link(phydev);
 168         if (ret)
 169                 return ret;
 170
 171         return m88e1xxx_parse_status(phydev);
 172 }
 173
 174 /* Marvell 88E1111S */
 175 static int m88e1111s_config(struct phy_device *phydev)
 176 {
 177         int reg;
 178
 179         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
 180                         (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 181                         (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 182                         (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 183                 reg = phy_read(phydev,
 184                         MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
 185                 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
 186                         (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
 187                         reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
 188                 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
 189                         reg &= ~MIIM_88E1111_TX_DELAY;
 190                         reg |= MIIM_88E1111_RX_DELAY;
 191                 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
 192                         reg &= ~MIIM_88E1111_RX_DELAY;
 193                         reg |= MIIM_88E1111_TX_DELAY;
 194                 }
 195
 196                 phy_write(phydev,
 197                         MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
 198
 199                 reg = phy_read(phydev,
 200                         MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
 201
 202                 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
 203
 204                 if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
 205                         reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
 206                 else
 207                         reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
 208
 209                 phy_write(phydev,
 210                         MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg);
 211         }
 212
 213         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 214                 reg = phy_read(phydev,
 215                         MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
 216
 217                 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
 218                 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
 219                 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
 220
 221                 phy_write(phydev, MDIO_DEVAD_NONE,
 222                         MIIM_88E1111_PHY_EXT_SR, reg);
 223         }
 224
 225         if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
 226                 reg = phy_read(phydev,
 227                         MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
 228                 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
 229                 phy_write(phydev,
 230                         MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
 231
 232                 reg = phy_read(phydev, MDIO_DEVAD_NONE,
 233                         MIIM_88E1111_PHY_EXT_SR);
 234                 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
 235                         MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
 236                 reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
 237                 phy_write(phydev, MDIO_DEVAD_NONE,
 238                         MIIM_88E1111_PHY_EXT_SR, reg);
 239
 240                 /* soft reset */
 241                 phy_reset(phydev);
 242
 243                 reg = phy_read(phydev, MDIO_DEVAD_NONE,
 244                         MIIM_88E1111_PHY_EXT_SR);
 245                 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
 246                         MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
 247                 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
 248                         MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
 249                 phy_write(phydev, MDIO_DEVAD_NONE,
 250                         MIIM_88E1111_PHY_EXT_SR, reg);
 251         }
 252
 253         /* soft reset */
 254         phy_reset(phydev);
 255
 256         genphy_config_aneg(phydev);
 257         genphy_restart_aneg(phydev);
 258
 259         return 0;
 260 }
 261
 262 /**
 263  * m88e1518_phy_writebits - write bits to a register
 264  */
 265 void m88e1518_phy_writebits(struct phy_device *phydev,
 266                    u8 reg_num, u16 offset, u16 len, u16 data)
 267 {
 268         u16 reg, mask;
 269
 270         if ((len + offset) >= 16)
 271                 mask = 0 - (1 << offset);
 272         else
 273                 mask = (1 << (len + offset)) - (1 << offset);
 274
 275         reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
 276
 277         reg &= ~mask;
 278         reg |= data << offset;
 279
 280         phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
 281 }
 282
 283 static int m88e1518_config(struct phy_device *phydev)
 284 {
 285         /*
 286          * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
 287          * /88E1514 Rev A0, Errata Section 3.1
 288          */
 289
 290         /* EEE initialization */
 291         phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff);
 292         phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
 293         phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
 294         phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
 295         phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
 296         phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
 297         phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
 298         phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
 299         phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
 300         phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
 301
 302         /* SGMII-to-Copper mode initialization */
 303         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 304                 /* Select page 18 */
 305                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 18);
 306
 307                 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
 308                 m88e1518_phy_writebits(phydev, 20, 0, 3, 1);
 309
 310                 /* PHY reset is necessary after changing MODE[2:0] */
 311                 m88e1518_phy_writebits(phydev, 20, 15, 1, 1);
 312
 313                 /* Reset page selection */
 314                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 315
 316                 udelay(100);
 317         }
 318
 319         return m88e1111s_config(phydev);
 320 }
 321
 322 /* Marvell 88E1510 */
 323 static int m88e1510_config(struct phy_device *phydev)
 324 {
 325         /* Select page 3 */
 326         phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 327
 328         /* Enable INTn output on LED[2] */
 329         m88e1518_phy_writebits(phydev, 18, 7, 1, 1);
 330
 331         /* Configure LEDs */
 332         m88e1518_phy_writebits(phydev, 16, 0, 4, 3); /* LED[0]:0011 (ACT) */
 333         m88e1518_phy_writebits(phydev, 16, 4, 4, 6); /* LED[1]:0110 (LINK) */
 334
 335         /* Reset page selection */
 336         phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 337
 338         return m88e1518_config(phydev);
 339 }
 340
 341 /* Marvell 88E1118 */
 342 static int m88e1118_config(struct phy_device *phydev)
 343 {
 344         /* Change Page Number */
 345         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002);
 346         /* Delay RGMII TX and RX */
 347         phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070);
 348         /* Change Page Number */
 349         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003);
 350         /* Adjust LED control */
 351         phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e);
 352         /* Change Page Number */
 353         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
 354
 355         return genphy_config_aneg(phydev);
 356 }
 357
 358 static int m88e1118_startup(struct phy_device *phydev)
 359 {
 360         int ret;
 361
 362         /* Change Page Number */
 363         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
 364
 365         ret = genphy_update_link(phydev);
 366         if (ret)
 367                 return ret;
 368
 369         return m88e1xxx_parse_status(phydev);
 370 }
 371
 372 /* Marvell 88E1121R */
 373 static int m88e1121_config(struct phy_device *phydev)
 374 {
 375         int pg;
 376
 377         /* Configure the PHY */
 378         genphy_config_aneg(phydev);
 379
 380         /* Switch the page to access the led register */
 381         pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE);
 382         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE,
 383                         MIIM_88E1121_PHY_LED_PAGE);
 384         /* Configure leds */
 385         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL,
 386                         MIIM_88E1121_PHY_LED_DEF);
 387         /* Restore the page pointer */
 388         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg);
 389
 390         /* Disable IRQs and de-assert interrupt */
 391         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0);
 392         phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS);
 393
 394         return 0;
 395 }
 396
 397 /* Marvell 88E1145 */
 398 static int m88e1145_config(struct phy_device *phydev)
 399 {
 400         int reg;
 401
 402         /* Errata E0, E1 */
 403         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b);
 404         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f);
 405         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016);
 406         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da);
 407
 408         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR,
 409                         MIIM_88E1xxx_PHY_MDI_X_AUTO);
 410
 411         reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR);
 412         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 413                 reg |= MIIM_M88E1145_RGMII_RX_DELAY |
 414                         MIIM_M88E1145_RGMII_TX_DELAY;
 415         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg);
 416
 417         genphy_config_aneg(phydev);
 418
 419         phy_reset(phydev);
 420
 421         return 0;
 422 }
 423
 424 static int m88e1145_startup(struct phy_device *phydev)
 425 {
 426         int ret;
 427
 428         ret = genphy_update_link(phydev);
 429         if (ret)
 430                 return ret;
 431
 432         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
 433                         MIIM_88E1145_PHY_LED_DIRECT);
 434         return m88e1xxx_parse_status(phydev);
 435 }
 436
 437 /* Marvell 88E1149S */
 438 static int m88e1149_config(struct phy_device *phydev)
 439 {
 440         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f);
 441         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
 442         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5);
 443         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0);
 444         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
 445
 446         genphy_config_aneg(phydev);
 447
 448         phy_reset(phydev);
 449
 450         return 0;
 451 }
 452
 453 /* Marvell 88E1310 */
 454 static int m88e1310_config(struct phy_device *phydev)
 455 {
 456         u16 reg;
 457
 458         /* LED link and activity */
 459         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
 460         reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
 461         reg = (reg & ~0xf) | 0x1;
 462         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
 463
 464         /* Set LED2/INT to INT mode, low active */
 465         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
 466         reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
 467         reg = (reg & 0x77ff) | 0x0880;
 468         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
 469
 470         /* Set RGMII delay */
 471         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
 472         reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
 473         reg |= 0x0030;
 474         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
 475
 476         /* Ensure to return to page 0 */
 477         phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
 478
 479         genphy_config_aneg(phydev);
 480         phy_reset(phydev);
 481
 482         return 0;
 483 }
 484
 485 static struct phy_driver M88E1011S_driver = {
 486         .name = "Marvell 88E1011S",
 487         .uid = 0x1410c60,
 488         .mask = 0xffffff0,
 489         .features = PHY_GBIT_FEATURES,
 490         .config = &m88e1011s_config,
 491         .startup = &m88e1011s_startup,
 492         .shutdown = &genphy_shutdown,
 493 };
 494
 495 static struct phy_driver M88E1111S_driver = {
 496         .name = "Marvell 88E1111S",
 497         .uid = 0x1410cc0,
 498         .mask = 0xffffff0,
 499         .features = PHY_GBIT_FEATURES,
 500         .config = &m88e1111s_config,
 501         .startup = &m88e1011s_startup,
 502         .shutdown = &genphy_shutdown,
 503 };
 504
 505 static struct phy_driver M88E1118_driver = {
 506         .name = "Marvell 88E1118",
 507         .uid = 0x1410e10,
 508         .mask = 0xffffff0,
 509         .features = PHY_GBIT_FEATURES,
 510         .config = &m88e1118_config,
 511         .startup = &m88e1118_startup,
 512         .shutdown = &genphy_shutdown,
 513 };
 514
 515 static struct phy_driver M88E1118R_driver = {
 516         .name = "Marvell 88E1118R",
 517         .uid = 0x1410e40,
 518         .mask = 0xffffff0,
 519         .features = PHY_GBIT_FEATURES,
 520         .config = &m88e1118_config,
 521         .startup = &m88e1118_startup,
 522         .shutdown = &genphy_shutdown,
 523 };
 524
 525 static struct phy_driver M88E1121R_driver = {
 526         .name = "Marvell 88E1121R",
 527         .uid = 0x1410cb0,
 528         .mask = 0xffffff0,
 529         .features = PHY_GBIT_FEATURES,
 530         .config = &m88e1121_config,
 531         .startup = &genphy_startup,
 532         .shutdown = &genphy_shutdown,
 533 };
 534
 535 static struct phy_driver M88E1145_driver = {
 536         .name = "Marvell 88E1145",
 537         .uid = 0x1410cd0,
 538         .mask = 0xffffff0,
 539         .features = PHY_GBIT_FEATURES,
 540         .config = &m88e1145_config,
 541         .startup = &m88e1145_startup,
 542         .shutdown = &genphy_shutdown,
 543 };
 544
 545 static struct phy_driver M88E1149S_driver = {
 546         .name = "Marvell 88E1149S",
 547         .uid = 0x1410ca0,
 548         .mask = 0xffffff0,
 549         .features = PHY_GBIT_FEATURES,
 550         .config = &m88e1149_config,
 551         .startup = &m88e1011s_startup,
 552         .shutdown = &genphy_shutdown,
 553 };
 554
 555 static struct phy_driver M88E1510_driver = {
 556         .name = "Marvell 88E1510",
 557         .uid = 0x1410dd0,
 558         .mask = 0xffffff0,
 559         .features = PHY_GBIT_FEATURES,
 560         .config = &m88e1510_config,
 561         .startup = &m88e1011s_startup,
 562         .shutdown = &genphy_shutdown,
 563 };
 564
 565 static struct phy_driver M88E1518_driver = {
 566         .name = "Marvell 88E1518",
 567         .uid = 0x1410dd1,
 568         .mask = 0xffffff0,
 569         .features = PHY_GBIT_FEATURES,
 570         .config = &m88e1518_config,
 571         .startup = &m88e1011s_startup,
 572         .shutdown = &genphy_shutdown,
 573 };
 574
 575 static struct phy_driver M88E1310_driver = {
 576         .name = "Marvell 88E1310",
 577         .uid = 0x01410e90,
 578         .mask = 0xffffff0,
 579         .features = PHY_GBIT_FEATURES,
 580         .config = &m88e1310_config,
 581         .startup = &m88e1011s_startup,
 582         .shutdown = &genphy_shutdown,
 583 };
 584
 585 int phy_marvell_init(void)
 586 {
 587         phy_register(&M88E1310_driver);
 588         phy_register(&M88E1149S_driver);
 589         phy_register(&M88E1145_driver);
 590         phy_register(&M88E1121R_driver);
 591         phy_register(&M88E1118_driver);
 592         phy_register(&M88E1118R_driver);
 593         phy_register(&M88E1111S_driver);
 594         phy_register(&M88E1011S_driver);
 595         phy_register(&M88E1510_driver);
 596         phy_register(&M88E1518_driver);
 597
 598         return 0;
 599 }