4 * SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * (C) 2012 NetModule AG, David Andrey, added KSZ9031
18 DECLARE_GLOBAL_DATA_PTR;
20 static struct phy_driver KSZ804_driver = {
21 .name = "Micrel KSZ804",
24 .features = PHY_BASIC_FEATURES,
25 .config = &genphy_config,
26 .startup = &genphy_startup,
27 .shutdown = &genphy_shutdown,
30 #define MII_KSZPHY_OMSO 0x16
31 #define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
33 static int ksz_genconfig_bcastoff(struct phy_device *phydev)
37 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO);
41 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO,
42 ret | KSZPHY_OMSO_B_CAST_OFF);
46 return genphy_config(phydev);
49 static struct phy_driver KSZ8031_driver = {
50 .name = "Micrel KSZ8021/KSZ8031",
53 .features = PHY_BASIC_FEATURES,
54 .config = &ksz_genconfig_bcastoff,
55 .startup = &genphy_startup,
56 .shutdown = &genphy_shutdown,
62 #define MII_KSZ8051_PHY_OMSO 0x16
63 #define MII_KSZ8051_PHY_OMSO_NAND_TREE_ON (1 << 5)
65 static int ksz8051_config(struct phy_device *phydev)
69 /* Disable NAND-tree */
70 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO);
71 val &= ~MII_KSZ8051_PHY_OMSO_NAND_TREE_ON;
72 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val);
74 return genphy_config(phydev);
77 static struct phy_driver KSZ8051_driver = {
78 .name = "Micrel KSZ8051",
81 .features = PHY_BASIC_FEATURES,
82 .config = &ksz8051_config,
83 .startup = &genphy_startup,
84 .shutdown = &genphy_shutdown,
87 static struct phy_driver KSZ8081_driver = {
88 .name = "Micrel KSZ8081",
91 .features = PHY_BASIC_FEATURES,
92 .config = &ksz_genconfig_bcastoff,
93 .startup = &genphy_startup,
94 .shutdown = &genphy_shutdown,
101 static unsigned short smireg_to_phy(unsigned short reg)
103 return ((reg & 0xc0) >> 3) + 0x06 + ((reg & 0x20) >> 5);
106 static unsigned short smireg_to_reg(unsigned short reg)
111 static void ksz8895_write_smireg(struct phy_device *phydev, int smireg, int val)
113 phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE,
114 smireg_to_reg(smireg), val);
118 static int ksz8895_read_smireg(struct phy_device *phydev, int smireg)
120 return phydev->bus->read(phydev->bus, smireg_to_phy(smireg),
121 MDIO_DEVAD_NONE, smireg_to_reg(smireg));
125 int ksz8895_config(struct phy_device *phydev)
127 /* we are connected directly to the switch without
128 * dedicated PHY. SCONF1 == 001 */
130 phydev->duplex = DUPLEX_FULL;
131 phydev->speed = SPEED_100;
133 /* Force the switch to start */
134 ksz8895_write_smireg(phydev, 1, 1);
139 static int ksz8895_startup(struct phy_device *phydev)
144 static struct phy_driver ksz8895_driver = {
145 .name = "Micrel KSZ8895/KSZ8864",
148 .features = PHY_BASIC_FEATURES,
149 .config = &ksz8895_config,
150 .startup = &ksz8895_startup,
151 .shutdown = &genphy_shutdown,
154 #ifndef CONFIG_PHY_MICREL_KSZ9021
156 * I can't believe Micrel used the exact same part number
157 * for the KSZ9021. Shame Micrel, Shame!
159 static struct phy_driver KS8721_driver = {
160 .name = "Micrel KS8721BL",
163 .features = PHY_BASIC_FEATURES,
164 .config = &genphy_config,
165 .startup = &genphy_startup,
166 .shutdown = &genphy_shutdown,
172 * KSZ9021 - KSZ9031 common
175 #define MII_KSZ90xx_PHY_CTL 0x1f
176 #define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6)
177 #define MIIM_KSZ90xx_PHYCTL_100 (1 << 5)
178 #define MIIM_KSZ90xx_PHYCTL_10 (1 << 4)
179 #define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3)
181 static int ksz90xx_startup(struct phy_device *phydev)
186 ret = genphy_update_link(phydev);
190 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
192 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
193 phydev->duplex = DUPLEX_FULL;
195 phydev->duplex = DUPLEX_HALF;
197 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
198 phydev->speed = SPEED_1000;
199 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
200 phydev->speed = SPEED_100;
201 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
202 phydev->speed = SPEED_10;
206 /* Common OF config bits for KSZ9021 and KSZ9031 */
207 #if defined(CONFIG_PHY_MICREL_KSZ9021) || defined(CONFIG_PHY_MICREL_KSZ9031)
209 struct ksz90x1_reg_field {
211 const u8 size; /* Size of the bitfield, in bits */
212 const u8 off; /* Offset from bit 0 */
213 const u8 dflt; /* Default value */
216 struct ksz90x1_ofcfg {
219 const struct ksz90x1_reg_field *grp;
223 static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
224 { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
225 { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
228 static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
229 { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
230 { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
233 static int ksz90x1_of_config_group(struct phy_device *phydev,
234 struct ksz90x1_ofcfg *ofcfg)
236 struct udevice *dev = phydev->dev;
237 struct phy_driver *drv = phydev->drv;
238 const int ps_to_regval = 60;
240 int i, changed = 0, offset, max;
243 if (!drv || !drv->writeext)
246 for (i = 0; i < ofcfg->grpsz; i++) {
247 val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
248 ofcfg->grp[i].name, -1);
249 offset = ofcfg->grp[i].off;
251 /* Default register value for KSZ9021 */
252 regval |= ofcfg->grp[i].dflt << offset;
254 changed = 1; /* Value was changed in OF */
255 /* Calculate the register value and fix corner cases */
256 if (val[i] > ps_to_regval * 0xf) {
257 max = (1 << ofcfg->grp[i].size) - 1;
258 regval |= max << offset;
260 regval |= (val[i] / ps_to_regval) << offset;
268 return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
273 #ifdef CONFIG_PHY_MICREL_KSZ9021
279 #define MII_KSZ9021_EXTENDED_CTRL 0x0b
280 #define MII_KSZ9021_EXTENDED_DATAW 0x0c
281 #define MII_KSZ9021_EXTENDED_DATAR 0x0d
283 #define CTRL1000_PREFER_MASTER (1 << 10)
284 #define CTRL1000_CONFIG_MASTER (1 << 11)
285 #define CTRL1000_MANUAL_CONFIG (1 << 12)
287 #if defined(CONFIG_DM_ETH) && (defined(CONFIG_PHY_MICREL_KSZ9021) || \
288 defined(CONFIG_PHY_MICREL_KSZ9031))
289 static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
290 { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
291 { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
294 static int ksz9021_of_config(struct phy_device *phydev)
296 struct ksz90x1_ofcfg ofcfg[] = {
297 { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
298 { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
299 { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
303 for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
304 ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
312 static int ksz9021_of_config(struct phy_device *phydev)
318 int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
320 /* extended registers */
321 phy_write(phydev, MDIO_DEVAD_NONE,
322 MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
323 return phy_write(phydev, MDIO_DEVAD_NONE,
324 MII_KSZ9021_EXTENDED_DATAW, val);
327 int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
329 /* extended registers */
330 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
331 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
335 static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
338 return ksz9021_phy_extended_read(phydev, regnum);
341 static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
342 int devaddr, int regnum, u16 val)
344 return ksz9021_phy_extended_write(phydev, regnum, val);
348 static int ksz9021_config(struct phy_device *phydev)
350 unsigned ctrl1000 = 0;
351 const unsigned master = CTRL1000_PREFER_MASTER |
352 CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
353 unsigned features = phydev->drv->features;
356 ret = ksz9021_of_config(phydev);
360 if (getenv("disable_giga"))
361 features &= ~(SUPPORTED_1000baseT_Half |
362 SUPPORTED_1000baseT_Full);
363 /* force master mode for 1000BaseT due to chip errata */
364 if (features & SUPPORTED_1000baseT_Half)
365 ctrl1000 |= ADVERTISE_1000HALF | master;
366 if (features & SUPPORTED_1000baseT_Full)
367 ctrl1000 |= ADVERTISE_1000FULL | master;
368 phydev->advertising = phydev->supported = features;
369 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
370 genphy_config_aneg(phydev);
371 genphy_restart_aneg(phydev);
375 static struct phy_driver ksz9021_driver = {
376 .name = "Micrel ksz9021",
379 .features = PHY_GBIT_FEATURES,
380 .config = &ksz9021_config,
381 .startup = &ksz90xx_startup,
382 .shutdown = &genphy_shutdown,
383 .writeext = &ksz9021_phy_extwrite,
384 .readext = &ksz9021_phy_extread,
392 #define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
393 #define MII_KSZ9031_MMD_REG_DATA 0x0e
395 #if defined(CONFIG_DM_ETH) && (defined(CONFIG_PHY_MICREL_KSZ9021) || \
396 defined(CONFIG_PHY_MICREL_KSZ9031))
397 static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
398 { { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } };
399 static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
400 { { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } };
402 static int ksz9031_of_config(struct phy_device *phydev)
404 struct ksz90x1_ofcfg ofcfg[] = {
405 { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
406 { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
407 { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
408 { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
412 for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
413 ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
421 static int ksz9031_center_flp_timing(struct phy_device *phydev)
423 struct phy_driver *drv = phydev->drv;
426 if (!drv || !drv->writeext)
429 ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
433 ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
437 static int ksz9031_of_config(struct phy_device *phydev)
441 static int ksz9031_center_flp_timing(struct phy_device *phydev)
447 /* Accessors to extended registers*/
448 int ksz9031_phy_extended_write(struct phy_device *phydev,
449 int devaddr, int regnum, u16 mode, u16 val)
451 /*select register addr for mmd*/
452 phy_write(phydev, MDIO_DEVAD_NONE,
453 MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
454 /*select register for mmd*/
455 phy_write(phydev, MDIO_DEVAD_NONE,
456 MII_KSZ9031_MMD_REG_DATA, regnum);
458 phy_write(phydev, MDIO_DEVAD_NONE,
459 MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
461 return phy_write(phydev, MDIO_DEVAD_NONE,
462 MII_KSZ9031_MMD_REG_DATA, val);
465 int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
466 int regnum, u16 mode)
468 phy_write(phydev, MDIO_DEVAD_NONE,
469 MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
470 phy_write(phydev, MDIO_DEVAD_NONE,
471 MII_KSZ9031_MMD_REG_DATA, regnum);
472 phy_write(phydev, MDIO_DEVAD_NONE,
473 MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
474 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
477 static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
480 return ksz9031_phy_extended_read(phydev, devaddr, regnum,
481 MII_KSZ9031_MOD_DATA_NO_POST_INC);
484 static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
485 int devaddr, int regnum, u16 val)
487 return ksz9031_phy_extended_write(phydev, devaddr, regnum,
488 MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
491 static int ksz9031_config(struct phy_device *phydev)
494 ret = ksz9031_of_config(phydev);
497 ret = ksz9031_center_flp_timing(phydev);
500 return genphy_config(phydev);
503 static struct phy_driver ksz9031_driver = {
504 .name = "Micrel ksz9031",
507 .features = PHY_GBIT_FEATURES,
508 .config = &ksz9031_config,
509 .startup = &ksz90xx_startup,
510 .shutdown = &genphy_shutdown,
511 .writeext = &ksz9031_phy_extwrite,
512 .readext = &ksz9031_phy_extread,
515 int ksz886x_config(struct phy_device *phydev)
517 /* we are connected directly to the switch without
520 phydev->duplex = DUPLEX_FULL;
521 phydev->speed = SPEED_100;
525 static int ksz886x_startup(struct phy_device *phydev)
530 static struct phy_driver ksz886x_driver = {
531 .name = "Micrel KSZ886x Switch",
534 .features = PHY_BASIC_FEATURES,
535 .config = &ksz886x_config,
536 .startup = &ksz886x_startup,
537 .shutdown = &genphy_shutdown,
540 int phy_micrel_init(void)
542 phy_register(&KSZ804_driver);
543 phy_register(&KSZ8031_driver);
544 phy_register(&KSZ8051_driver);
545 phy_register(&KSZ8081_driver);
546 #ifdef CONFIG_PHY_MICREL_KSZ9021
547 phy_register(&ksz9021_driver);
549 phy_register(&KS8721_driver);
551 phy_register(&ksz9031_driver);
552 phy_register(&ksz8895_driver);
553 phy_register(&ksz886x_driver);