4 * SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * (C) 2012 NetModule AG, David Andrey, added KSZ9031
9 * (C) Copyright 2017 Adaptrum, Inc.
10 * Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
20 DECLARE_GLOBAL_DATA_PTR;
23 * KSZ9021 - KSZ9031 common
26 #define MII_KSZ90xx_PHY_CTL 0x1f
27 #define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6)
28 #define MIIM_KSZ90xx_PHYCTL_100 (1 << 5)
29 #define MIIM_KSZ90xx_PHYCTL_10 (1 << 4)
30 #define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3)
32 /* KSZ9021 PHY Registers */
33 #define MII_KSZ9021_EXTENDED_CTRL 0x0b
34 #define MII_KSZ9021_EXTENDED_DATAW 0x0c
35 #define MII_KSZ9021_EXTENDED_DATAR 0x0d
37 #define CTRL1000_PREFER_MASTER (1 << 10)
38 #define CTRL1000_CONFIG_MASTER (1 << 11)
39 #define CTRL1000_MANUAL_CONFIG (1 << 12)
41 /* KSZ9031 PHY Registers */
42 #define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
43 #define MII_KSZ9031_MMD_REG_DATA 0x0e
45 static int ksz90xx_startup(struct phy_device *phydev)
50 ret = genphy_update_link(phydev);
54 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
56 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
57 phydev->duplex = DUPLEX_FULL;
59 phydev->duplex = DUPLEX_HALF;
61 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
62 phydev->speed = SPEED_1000;
63 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
64 phydev->speed = SPEED_100;
65 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
66 phydev->speed = SPEED_10;
70 /* Common OF config bits for KSZ9021 and KSZ9031 */
72 struct ksz90x1_reg_field {
74 const u8 size; /* Size of the bitfield, in bits */
75 const u8 off; /* Offset from bit 0 */
76 const u8 dflt; /* Default value */
79 struct ksz90x1_ofcfg {
82 const struct ksz90x1_reg_field *grp;
86 static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
87 { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
88 { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
91 static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
92 { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
93 { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
96 static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
97 { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
98 { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
101 static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = {
102 { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 }
105 static const struct ksz90x1_reg_field ksz9031_clk_grp[] = {
106 { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf }
109 static int ksz90x1_of_config_group(struct phy_device *phydev,
110 struct ksz90x1_ofcfg *ofcfg)
112 struct udevice *dev = phydev->dev;
113 struct phy_driver *drv = phydev->drv;
114 const int ps_to_regval = 60;
116 int i, changed = 0, offset, max;
119 if (!drv || !drv->writeext)
122 for (i = 0; i < ofcfg->grpsz; i++) {
123 val[i] = dev_read_u32_default(dev, ofcfg->grp[i].name, ~0);
124 offset = ofcfg->grp[i].off;
126 /* Default register value for KSZ9021 */
127 regval |= ofcfg->grp[i].dflt << offset;
129 changed = 1; /* Value was changed in OF */
130 /* Calculate the register value and fix corner cases */
131 if (val[i] > ps_to_regval * 0xf) {
132 max = (1 << ofcfg->grp[i].size) - 1;
133 regval |= max << offset;
135 regval |= (val[i] / ps_to_regval) << offset;
143 return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
146 static int ksz9021_of_config(struct phy_device *phydev)
148 struct ksz90x1_ofcfg ofcfg[] = {
149 { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
150 { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
151 { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
155 for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
156 ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
164 static int ksz9031_of_config(struct phy_device *phydev)
166 struct ksz90x1_ofcfg ofcfg[] = {
167 { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
168 { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
169 { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
170 { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
174 for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
175 ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
183 static int ksz9031_center_flp_timing(struct phy_device *phydev)
185 struct phy_driver *drv = phydev->drv;
188 if (!drv || !drv->writeext)
191 ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
195 ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
199 #else /* !CONFIG_DM_ETH */
200 static int ksz9021_of_config(struct phy_device *phydev)
205 static int ksz9031_of_config(struct phy_device *phydev)
210 static int ksz9031_center_flp_timing(struct phy_device *phydev)
219 int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
221 /* extended registers */
222 phy_write(phydev, MDIO_DEVAD_NONE,
223 MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
224 return phy_write(phydev, MDIO_DEVAD_NONE,
225 MII_KSZ9021_EXTENDED_DATAW, val);
228 int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
230 /* extended registers */
231 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
232 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
236 static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
239 return ksz9021_phy_extended_read(phydev, regnum);
242 static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
243 int devaddr, int regnum, u16 val)
245 return ksz9021_phy_extended_write(phydev, regnum, val);
248 static int ksz9021_config(struct phy_device *phydev)
250 unsigned ctrl1000 = 0;
251 const unsigned master = CTRL1000_PREFER_MASTER |
252 CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
253 unsigned features = phydev->drv->features;
256 ret = ksz9021_of_config(phydev);
260 if (env_get("disable_giga"))
261 features &= ~(SUPPORTED_1000baseT_Half |
262 SUPPORTED_1000baseT_Full);
263 /* force master mode for 1000BaseT due to chip errata */
264 if (features & SUPPORTED_1000baseT_Half)
265 ctrl1000 |= ADVERTISE_1000HALF | master;
266 if (features & SUPPORTED_1000baseT_Full)
267 ctrl1000 |= ADVERTISE_1000FULL | master;
268 phydev->advertising = features;
269 phydev->supported = features;
270 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
271 genphy_config_aneg(phydev);
272 genphy_restart_aneg(phydev);
276 static struct phy_driver ksz9021_driver = {
277 .name = "Micrel ksz9021",
280 .features = PHY_GBIT_FEATURES,
281 .config = &ksz9021_config,
282 .startup = &ksz90xx_startup,
283 .shutdown = &genphy_shutdown,
284 .writeext = &ksz9021_phy_extwrite,
285 .readext = &ksz9021_phy_extread,
291 int ksz9031_phy_extended_write(struct phy_device *phydev,
292 int devaddr, int regnum, u16 mode, u16 val)
294 /*select register addr for mmd*/
295 phy_write(phydev, MDIO_DEVAD_NONE,
296 MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
297 /*select register for mmd*/
298 phy_write(phydev, MDIO_DEVAD_NONE,
299 MII_KSZ9031_MMD_REG_DATA, regnum);
301 phy_write(phydev, MDIO_DEVAD_NONE,
302 MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
304 return phy_write(phydev, MDIO_DEVAD_NONE,
305 MII_KSZ9031_MMD_REG_DATA, val);
308 int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
309 int regnum, u16 mode)
311 phy_write(phydev, MDIO_DEVAD_NONE,
312 MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
313 phy_write(phydev, MDIO_DEVAD_NONE,
314 MII_KSZ9031_MMD_REG_DATA, regnum);
315 phy_write(phydev, MDIO_DEVAD_NONE,
316 MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
317 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
320 static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
323 return ksz9031_phy_extended_read(phydev, devaddr, regnum,
324 MII_KSZ9031_MOD_DATA_NO_POST_INC);
327 static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
328 int devaddr, int regnum, u16 val)
330 return ksz9031_phy_extended_write(phydev, devaddr, regnum,
331 MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
334 static int ksz9031_config(struct phy_device *phydev)
338 ret = ksz9031_of_config(phydev);
341 ret = ksz9031_center_flp_timing(phydev);
345 /* add an option to disable the gigabit feature of this PHY */
346 if (env_get("disable_giga")) {
350 /* disable speed 1000 in features supported by the PHY */
351 features = phydev->drv->features;
352 features &= ~(SUPPORTED_1000baseT_Half |
353 SUPPORTED_1000baseT_Full);
354 phydev->advertising = phydev->supported = features;
356 /* disable speed 1000 in Basic Control Register */
357 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
359 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr);
361 /* disable speed 1000 in 1000Base-T Control Register */
362 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);
365 genphy_config_aneg(phydev);
366 genphy_restart_aneg(phydev);
371 return genphy_config(phydev);
374 static struct phy_driver ksz9031_driver = {
375 .name = "Micrel ksz9031",
378 .features = PHY_GBIT_FEATURES,
379 .config = &ksz9031_config,
380 .startup = &ksz90xx_startup,
381 .shutdown = &genphy_shutdown,
382 .writeext = &ksz9031_phy_extwrite,
383 .readext = &ksz9031_phy_extread,
386 int phy_micrel_ksz90x1_init(void)
388 phy_register(&ksz9021_driver);
389 phy_register(&ksz9031_driver);