4 * Copyright 2010-2014 Freescale Semiconductor, Inc.
5 * Original Author: Andy Fleming
6 * Add vsc8662 phy support - Priyanka Jain
7 * SPDX-License-Identifier: GPL-2.0+
11 /* Cicada Auxiliary Control/Status Register */
12 #define MIIM_CIS82xx_AUX_CONSTAT 0x1c
13 #define MIIM_CIS82xx_AUXCONSTAT_INIT 0x0004
14 #define MIIM_CIS82xx_AUXCONSTAT_DUPLEX 0x0020
15 #define MIIM_CIS82xx_AUXCONSTAT_SPEED 0x0018
16 #define MIIM_CIS82xx_AUXCONSTAT_GBIT 0x0010
17 #define MIIM_CIS82xx_AUXCONSTAT_100 0x0008
19 /* Cicada Extended Control Register 1 */
20 #define MIIM_CIS82xx_EXT_CON1 0x17
21 #define MIIM_CIS8201_EXTCON1_INIT 0x0000
23 /* Cicada 8204 Extended PHY Control Register 1 */
24 #define MIIM_CIS8204_EPHY_CON 0x17
25 #define MIIM_CIS8204_EPHYCON_INIT 0x0006
26 #define MIIM_CIS8204_EPHYCON_RGMII 0x1100
28 /* Cicada 8204 Serial LED Control Register */
29 #define MIIM_CIS8204_SLED_CON 0x1b
30 #define MIIM_CIS8204_SLEDCON_INIT 0x1115
32 /* Vitesse VSC8601 Extended PHY Control Register 1 */
33 #define MIIM_VSC8601_EPHY_CON 0x17
34 #define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
35 #define MIIM_VSC8601_SKEW_CTRL 0x1c
37 #define PHY_EXT_PAGE_ACCESS 0x1f
38 #define PHY_EXT_PAGE_ACCESS_GENERAL 0x10
39 #define PHY_EXT_PAGE_ACCESS_EXTENDED3 0x3
41 /* Vitesse VSC8574 control register */
42 #define MIIM_VSC8574_MAC_SERDES_CON 0x10
43 #define MIIM_VSC8574_MAC_SERDES_ANEG 0x80
44 #define MIIM_VSC8574_GENERAL18 0x12
45 #define MIIM_VSC8574_GENERAL19 0x13
47 /* Vitesse VSC8574 gerenal purpose register 18 */
48 #define MIIM_VSC8574_18G_SGMII 0x80f0
49 #define MIIM_VSC8574_18G_QSGMII 0x80e0
50 #define MIIM_VSC8574_18G_CMDSTAT 0x8000
52 /* Vitesse VSC8514 control register */
53 #define MIIM_VSC8514_MAC_SERDES_CON 0x10
54 #define MIIM_VSC8514_GENERAL18 0x12
55 #define MIIM_VSC8514_GENERAL19 0x13
56 #define MIIM_VSC8514_GENERAL23 0x17
58 /* Vitesse VSC8514 gerenal purpose register 18 */
59 #define MIIM_VSC8514_18G_QSGMII 0x80e0
60 #define MIIM_VSC8514_18G_CMDSTAT 0x8000
62 /* Vitesse VSC8664 Control/Status Register */
63 #define MIIM_VSC8664_SERDES_AND_SIGDET 0x13
64 #define MIIM_VSC8664_ADDITIONAL_DEV 0x16
65 #define MIIM_VSC8664_EPHY_CON 0x17
66 #define MIIM_VSC8664_LED_CON 0x1E
68 #define PHY_EXT_PAGE_ACCESS_EXTENDED 0x0001
71 static int vitesse_config(struct phy_device *phydev)
73 /* Override PHY config settings */
74 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT,
75 MIIM_CIS82xx_AUXCONSTAT_INIT);
76 /* Set up the interface mode */
77 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_EXT_CON1,
78 MIIM_CIS8201_EXTCON1_INIT);
80 genphy_config_aneg(phydev);
85 static int vitesse_parse_status(struct phy_device *phydev)
90 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT);
92 if (mii_reg & MIIM_CIS82xx_AUXCONSTAT_DUPLEX)
93 phydev->duplex = DUPLEX_FULL;
95 phydev->duplex = DUPLEX_HALF;
97 speed = mii_reg & MIIM_CIS82xx_AUXCONSTAT_SPEED;
99 case MIIM_CIS82xx_AUXCONSTAT_GBIT:
100 phydev->speed = SPEED_1000;
102 case MIIM_CIS82xx_AUXCONSTAT_100:
103 phydev->speed = SPEED_100;
106 phydev->speed = SPEED_10;
113 static int vitesse_startup(struct phy_device *phydev)
115 genphy_update_link(phydev);
116 vitesse_parse_status(phydev);
121 static int cis8204_config(struct phy_device *phydev)
123 /* Override PHY config settings */
124 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT,
125 MIIM_CIS82xx_AUXCONSTAT_INIT);
127 genphy_config_aneg(phydev);
129 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
130 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
131 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
132 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON,
133 MIIM_CIS8204_EPHYCON_INIT |
134 MIIM_CIS8204_EPHYCON_RGMII);
136 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON,
137 MIIM_CIS8204_EPHYCON_INIT);
142 /* Vitesse VSC8601 */
143 static int vsc8601_config(struct phy_device *phydev)
145 /* Configure some basic stuff */
146 #ifdef CONFIG_SYS_VSC8601_SKEWFIX
147 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8601_EPHY_CON,
148 MIIM_VSC8601_EPHY_CON_INIT_SKEW);
149 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
150 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 1);
151 #define VSC8101_SKEW \
152 ((CONFIG_SYS_VSC8601_SKEW_TX << 14) \
153 | (CONFIG_SYS_VSC8601_SKEW_RX << 12))
154 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8601_SKEW_CTRL,
156 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
160 genphy_config_aneg(phydev);
165 static int vsc8574_config(struct phy_device *phydev)
168 /* configure register 19G for MAC */
169 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
170 PHY_EXT_PAGE_ACCESS_GENERAL);
172 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19);
173 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
174 /* set bit 15:14 to '01' for QSGMII mode */
175 val = (val & 0x3fff) | (1 << 14);
176 phy_write(phydev, MDIO_DEVAD_NONE,
177 MIIM_VSC8574_GENERAL19, val);
178 /* Enable 4 ports MAC QSGMII */
179 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18,
180 MIIM_VSC8574_18G_QSGMII);
182 /* set bit 15:14 to '00' for SGMII mode */
184 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19, val);
185 /* Enable 4 ports MAC SGMII */
186 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18,
187 MIIM_VSC8574_18G_SGMII);
189 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18);
190 /* When bit 15 is cleared the command has completed */
191 while (val & MIIM_VSC8574_18G_CMDSTAT)
192 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18);
194 /* Enable Serdes Auto-negotiation */
195 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
196 PHY_EXT_PAGE_ACCESS_EXTENDED3);
197 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON);
198 val = val | MIIM_VSC8574_MAC_SERDES_ANEG;
199 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON, val);
201 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
203 genphy_config_aneg(phydev);
208 static int vsc8514_config(struct phy_device *phydev)
211 int timeout = 1000000;
213 /* configure register to access 19G */
214 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
215 PHY_EXT_PAGE_ACCESS_GENERAL);
217 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL19);
218 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
219 /* set bit 15:14 to '01' for QSGMII mode */
220 val = (val & 0x3fff) | (1 << 14);
221 phy_write(phydev, MDIO_DEVAD_NONE,
222 MIIM_VSC8514_GENERAL19, val);
223 /* Enable 4 ports MAC QSGMII */
224 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18,
225 MIIM_VSC8514_18G_QSGMII);
227 /*TODO Add SGMII functionality once spec sheet
228 * for VSC8514 defines complete functionality
232 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18);
233 /* When bit 15 is cleared the command has completed */
234 while ((val & MIIM_VSC8514_18G_CMDSTAT) && timeout--)
235 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18);
238 printf("PHY 8514 config failed\n");
242 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
244 /* configure register to access 23 */
245 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23);
246 /* set bits 10:8 to '000' */
247 val = (val & 0xf8ff);
248 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23, val);
250 /* Enable Serdes Auto-negotiation */
251 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
252 PHY_EXT_PAGE_ACCESS_EXTENDED3);
253 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON);
254 val = val | MIIM_VSC8574_MAC_SERDES_ANEG;
255 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON, val);
256 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
258 genphy_config_aneg(phydev);
263 static int vsc8664_config(struct phy_device *phydev)
267 /* Enable MAC interface auto-negotiation */
268 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
269 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON);
271 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON, val);
273 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
274 PHY_EXT_PAGE_ACCESS_EXTENDED);
275 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET);
277 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET, val);
278 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
280 /* Enable LED blink */
281 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON);
283 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON, val);
285 genphy_config_aneg(phydev);
290 static struct phy_driver VSC8211_driver = {
291 .name = "Vitesse VSC8211",
294 .features = PHY_GBIT_FEATURES,
295 .config = &vitesse_config,
296 .startup = &vitesse_startup,
297 .shutdown = &genphy_shutdown,
300 static struct phy_driver VSC8221_driver = {
301 .name = "Vitesse VSC8221",
304 .features = PHY_GBIT_FEATURES,
305 .config = &genphy_config_aneg,
306 .startup = &vitesse_startup,
307 .shutdown = &genphy_shutdown,
310 static struct phy_driver VSC8244_driver = {
311 .name = "Vitesse VSC8244",
314 .features = PHY_GBIT_FEATURES,
315 .config = &genphy_config_aneg,
316 .startup = &vitesse_startup,
317 .shutdown = &genphy_shutdown,
320 static struct phy_driver VSC8234_driver = {
321 .name = "Vitesse VSC8234",
324 .features = PHY_GBIT_FEATURES,
325 .config = &genphy_config_aneg,
326 .startup = &vitesse_startup,
327 .shutdown = &genphy_shutdown,
330 static struct phy_driver VSC8574_driver = {
331 .name = "Vitesse VSC8574",
334 .features = PHY_GBIT_FEATURES,
335 .config = &vsc8574_config,
336 .startup = &vitesse_startup,
337 .shutdown = &genphy_shutdown,
340 static struct phy_driver VSC8514_driver = {
341 .name = "Vitesse VSC8514",
344 .features = PHY_GBIT_FEATURES,
345 .config = &vsc8514_config,
346 .startup = &vitesse_startup,
347 .shutdown = &genphy_shutdown,
350 static struct phy_driver VSC8601_driver = {
351 .name = "Vitesse VSC8601",
354 .features = PHY_GBIT_FEATURES,
355 .config = &vsc8601_config,
356 .startup = &vitesse_startup,
357 .shutdown = &genphy_shutdown,
360 static struct phy_driver VSC8641_driver = {
361 .name = "Vitesse VSC8641",
364 .features = PHY_GBIT_FEATURES,
365 .config = &genphy_config_aneg,
366 .startup = &vitesse_startup,
367 .shutdown = &genphy_shutdown,
370 static struct phy_driver VSC8662_driver = {
371 .name = "Vitesse VSC8662",
374 .features = PHY_GBIT_FEATURES,
375 .config = &genphy_config_aneg,
376 .startup = &vitesse_startup,
377 .shutdown = &genphy_shutdown,
380 static struct phy_driver VSC8664_driver = {
381 .name = "Vitesse VSC8664",
384 .features = PHY_GBIT_FEATURES,
385 .config = &vsc8664_config,
386 .startup = &vitesse_startup,
387 .shutdown = &genphy_shutdown,
390 /* Vitesse bought Cicada, so we'll put these here */
391 static struct phy_driver cis8201_driver = {
395 .features = PHY_GBIT_FEATURES,
396 .config = &vitesse_config,
397 .startup = &vitesse_startup,
398 .shutdown = &genphy_shutdown,
401 static struct phy_driver cis8204_driver = {
402 .name = "Cicada Cis8204",
405 .features = PHY_GBIT_FEATURES,
406 .config = &cis8204_config,
407 .startup = &vitesse_startup,
408 .shutdown = &genphy_shutdown,
411 int phy_vitesse_init(void)
413 phy_register(&VSC8641_driver);
414 phy_register(&VSC8601_driver);
415 phy_register(&VSC8234_driver);
416 phy_register(&VSC8244_driver);
417 phy_register(&VSC8211_driver);
418 phy_register(&VSC8221_driver);
419 phy_register(&VSC8574_driver);
420 phy_register(&VSC8514_driver);
421 phy_register(&VSC8662_driver);
422 phy_register(&VSC8664_driver);
423 phy_register(&cis8201_driver);
424 phy_register(&cis8204_driver);