1 // SPDX-License-Identifier: GPL-2.0+
4 * This file is driver for Renesas Ethernet AVB.
6 * Copyright (C) 2015-2017 Renesas Electronics Corporation
8 * Based on the SuperH Ethernet driver.
17 #include <linux/mii.h>
23 #define RAVB_REG_CCC 0x000
24 #define RAVB_REG_DBAT 0x004
25 #define RAVB_REG_CSR 0x00C
26 #define RAVB_REG_APSR 0x08C
27 #define RAVB_REG_RCR 0x090
28 #define RAVB_REG_TGC 0x300
29 #define RAVB_REG_TCCR 0x304
30 #define RAVB_REG_RIC0 0x360
31 #define RAVB_REG_RIC1 0x368
32 #define RAVB_REG_RIC2 0x370
33 #define RAVB_REG_TIC 0x378
34 #define RAVB_REG_ECMR 0x500
35 #define RAVB_REG_RFLR 0x508
36 #define RAVB_REG_ECSIPR 0x518
37 #define RAVB_REG_PIR 0x520
38 #define RAVB_REG_GECMR 0x5b0
39 #define RAVB_REG_MAHR 0x5c0
40 #define RAVB_REG_MALR 0x5c8
42 #define CCC_OPC_CONFIG BIT(0)
43 #define CCC_OPC_OPERATION BIT(1)
44 #define CCC_BOC BIT(20)
46 #define CSR_OPS 0x0000000F
47 #define CSR_OPS_CONFIG BIT(1)
49 #define TCCR_TSRQ0 BIT(0)
51 #define RFLR_RFL_MIN 0x05EE
53 #define PIR_MDI BIT(3)
54 #define PIR_MDO BIT(2)
55 #define PIR_MMD BIT(1)
56 #define PIR_MDC BIT(0)
58 #define ECMR_TRCCM BIT(26)
59 #define ECMR_RZPF BIT(20)
60 #define ECMR_PFR BIT(18)
61 #define ECMR_RXF BIT(17)
62 #define ECMR_RE BIT(6)
63 #define ECMR_TE BIT(5)
64 #define ECMR_DM BIT(1)
65 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)
68 #define RAVB_NUM_BASE_DESC 16
69 #define RAVB_NUM_TX_DESC 8
70 #define RAVB_NUM_RX_DESC 8
72 #define RAVB_TX_QUEUE_OFFSET 0
73 #define RAVB_RX_QUEUE_OFFSET 4
75 #define RAVB_DESC_DT(n) ((n) << 28)
76 #define RAVB_DESC_DT_FSINGLE RAVB_DESC_DT(0x7)
77 #define RAVB_DESC_DT_LINKFIX RAVB_DESC_DT(0x9)
78 #define RAVB_DESC_DT_EOS RAVB_DESC_DT(0xa)
79 #define RAVB_DESC_DT_FEMPTY RAVB_DESC_DT(0xc)
80 #define RAVB_DESC_DT_EEMPTY RAVB_DESC_DT(0x3)
81 #define RAVB_DESC_DT_MASK RAVB_DESC_DT(0xf)
83 #define RAVB_DESC_DS(n) (((n) & 0xfff) << 0)
84 #define RAVB_DESC_DS_MASK 0xfff
86 #define RAVB_RX_DESC_MSC_MC BIT(23)
87 #define RAVB_RX_DESC_MSC_CEEF BIT(22)
88 #define RAVB_RX_DESC_MSC_CRL BIT(21)
89 #define RAVB_RX_DESC_MSC_FRE BIT(20)
90 #define RAVB_RX_DESC_MSC_RTLF BIT(19)
91 #define RAVB_RX_DESC_MSC_RTSF BIT(18)
92 #define RAVB_RX_DESC_MSC_RFE BIT(17)
93 #define RAVB_RX_DESC_MSC_CRC BIT(16)
94 #define RAVB_RX_DESC_MSC_MASK (0xff << 16)
96 #define RAVB_RX_DESC_MSC_RX_ERR_MASK \
97 (RAVB_RX_DESC_MSC_CRC | RAVB_RX_DESC_MSC_RFE | RAVB_RX_DESC_MSC_RTLF | \
98 RAVB_RX_DESC_MSC_RTSF | RAVB_RX_DESC_MSC_CEEF)
100 #define RAVB_TX_TIMEOUT_MS 1000
108 struct ravb_desc data;
109 struct ravb_desc link;
111 u8 packet[PKTSIZE_ALIGN];
115 struct ravb_desc base_desc[RAVB_NUM_BASE_DESC];
116 struct ravb_desc tx_desc[RAVB_NUM_TX_DESC];
117 struct ravb_rxdesc rx_desc[RAVB_NUM_RX_DESC];
121 struct phy_device *phydev;
123 void __iomem *iobase;
125 struct gpio_desc reset_gpio;
128 static inline void ravb_flush_dcache(u32 addr, u32 len)
130 flush_dcache_range(addr, addr + len);
133 static inline void ravb_invalidate_dcache(u32 addr, u32 len)
135 u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
136 u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
137 invalidate_dcache_range(start, end);
140 static int ravb_send(struct udevice *dev, void *packet, int len)
142 struct ravb_priv *eth = dev_get_priv(dev);
143 struct ravb_desc *desc = ð->tx_desc[eth->tx_desc_idx];
146 /* Update TX descriptor */
147 ravb_flush_dcache((uintptr_t)packet, len);
148 memset(desc, 0x0, sizeof(*desc));
149 desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len);
150 desc->dptr = (uintptr_t)packet;
151 ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
153 /* Restart the transmitter if disabled */
154 if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
155 setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);
157 /* Wait until packet is transmitted */
158 start = get_timer(0);
159 while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
160 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
161 if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
166 if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
169 eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
173 static int ravb_recv(struct udevice *dev, int flags, uchar **packetp)
175 struct ravb_priv *eth = dev_get_priv(dev);
176 struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx];
180 /* Check if the rx descriptor is ready */
181 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
182 if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
185 /* Check for errors */
186 if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
187 desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
191 len = desc->data.ctrl & RAVB_DESC_DS_MASK;
192 packet = (u8 *)(uintptr_t)desc->data.dptr;
193 ravb_invalidate_dcache((uintptr_t)packet, len);
199 static int ravb_free_pkt(struct udevice *dev, uchar *packet, int length)
201 struct ravb_priv *eth = dev_get_priv(dev);
202 struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx];
204 /* Make current descriptor available again */
205 desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN);
206 ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
208 /* Point to the next descriptor */
209 eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
210 desc = ð->rx_desc[eth->rx_desc_idx];
211 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
216 static int ravb_reset(struct udevice *dev)
218 struct ravb_priv *eth = dev_get_priv(dev);
220 /* Set config mode */
221 writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
223 /* Check the operating mode is changed to the config mode. */
224 return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
225 CSR_OPS_CONFIG, true, 100, true);
228 static void ravb_base_desc_init(struct ravb_priv *eth)
230 const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
233 /* Initialize all descriptors */
234 memset(eth->base_desc, 0x0, desc_size);
236 for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
237 eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;
239 ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);
241 /* Register the descriptor base address table */
242 writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
245 static void ravb_tx_desc_init(struct ravb_priv *eth)
247 const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
250 /* Initialize all descriptors */
251 memset(eth->tx_desc, 0x0, desc_size);
252 eth->tx_desc_idx = 0;
254 for (i = 0; i < RAVB_NUM_TX_DESC; i++)
255 eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;
257 /* Mark the end of the descriptors */
258 eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
259 eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
260 ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);
262 /* Point the controller to the TX descriptor list. */
263 eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
264 eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
265 ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_TX_QUEUE_OFFSET],
266 sizeof(struct ravb_desc));
269 static void ravb_rx_desc_init(struct ravb_priv *eth)
271 const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
274 /* Initialize all descriptors */
275 memset(eth->rx_desc, 0x0, desc_size);
276 eth->rx_desc_idx = 0;
278 for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
279 eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY |
280 RAVB_DESC_DS(PKTSIZE_ALIGN);
281 eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;
283 eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
284 eth->rx_desc[i].link.dptr = (uintptr_t)ð->rx_desc[i + 1];
287 /* Mark the end of the descriptors */
288 eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
289 eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
290 ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);
292 /* Point the controller to the rx descriptor list */
293 eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
294 eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
295 ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_RX_QUEUE_OFFSET],
296 sizeof(struct ravb_desc));
299 static int ravb_phy_config(struct udevice *dev)
301 struct ravb_priv *eth = dev_get_priv(dev);
302 struct eth_pdata *pdata = dev_get_platdata(dev);
303 struct phy_device *phydev;
304 int mask = 0xffffffff, reg;
306 if (dm_gpio_is_valid(ð->reset_gpio)) {
307 dm_gpio_set_value(ð->reset_gpio, 1);
309 dm_gpio_set_value(ð->reset_gpio, 0);
313 phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
317 phy_connect_dev(phydev, dev);
319 eth->phydev = phydev;
321 /* 10BASE is not supported for Ethernet AVB MAC */
322 phydev->supported &= ~(SUPPORTED_10baseT_Full
323 | SUPPORTED_10baseT_Half);
324 if (pdata->max_speed != 1000) {
325 phydev->supported &= ~(SUPPORTED_1000baseT_Half
326 | SUPPORTED_1000baseT_Full);
327 reg = phy_read(phydev, -1, MII_CTRL1000);
328 reg &= ~(BIT(9) | BIT(8));
329 phy_write(phydev, -1, MII_CTRL1000, reg);
337 /* Set Mac address */
338 static int ravb_write_hwaddr(struct udevice *dev)
340 struct ravb_priv *eth = dev_get_priv(dev);
341 struct eth_pdata *pdata = dev_get_platdata(dev);
342 unsigned char *mac = pdata->enetaddr;
344 writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],
345 eth->iobase + RAVB_REG_MAHR);
347 writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR);
352 /* E-MAC init function */
353 static int ravb_mac_init(struct ravb_priv *eth)
355 /* Disable MAC Interrupt */
356 writel(0, eth->iobase + RAVB_REG_ECSIPR);
358 /* Recv frame limit set register */
359 writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);
364 /* AVB-DMAC init function */
365 static int ravb_dmac_init(struct udevice *dev)
367 struct ravb_priv *eth = dev_get_priv(dev);
368 struct eth_pdata *pdata = dev_get_platdata(dev);
371 /* Set CONFIG mode */
372 ret = ravb_reset(dev);
376 /* Disable all interrupts */
377 writel(0, eth->iobase + RAVB_REG_RIC0);
378 writel(0, eth->iobase + RAVB_REG_RIC1);
379 writel(0, eth->iobase + RAVB_REG_RIC2);
380 writel(0, eth->iobase + RAVB_REG_TIC);
382 /* Set little endian */
383 clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);
386 writel(0x18000001, eth->iobase + RAVB_REG_RCR);
389 writel(0x00222210, eth->iobase + RAVB_REG_TGC);
392 if (pdata->max_speed == 1000)
393 writel(BIT(14), eth->iobase + RAVB_REG_APSR);
398 static int ravb_config(struct udevice *dev)
400 struct ravb_priv *eth = dev_get_priv(dev);
401 struct phy_device *phy = eth->phydev;
402 u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
405 /* Configure AVB-DMAC register */
408 /* Configure E-MAC registers */
410 ravb_write_hwaddr(dev);
412 ret = phy_startup(phy);
416 /* Set the transfer speed */
417 if (phy->speed == 100)
418 writel(0, eth->iobase + RAVB_REG_GECMR);
419 else if (phy->speed == 1000)
420 writel(1, eth->iobase + RAVB_REG_GECMR);
422 /* Check if full duplex mode is supported by the phy */
426 writel(mask, eth->iobase + RAVB_REG_ECMR);
428 phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19);
433 static int ravb_start(struct udevice *dev)
435 struct ravb_priv *eth = dev_get_priv(dev);
438 ret = ravb_reset(dev);
442 ravb_base_desc_init(eth);
443 ravb_tx_desc_init(eth);
444 ravb_rx_desc_init(eth);
446 ret = ravb_config(dev);
450 /* Setting the control will start the AVB-DMAC process. */
451 writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
456 clk_disable(ð->clk);
460 static void ravb_stop(struct udevice *dev)
462 struct ravb_priv *eth = dev_get_priv(dev);
464 phy_shutdown(eth->phydev);
468 static int ravb_probe(struct udevice *dev)
470 struct eth_pdata *pdata = dev_get_platdata(dev);
471 struct ravb_priv *eth = dev_get_priv(dev);
472 struct mii_dev *mdiodev;
473 void __iomem *iobase;
476 iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
477 eth->iobase = iobase;
479 ret = clk_get_by_index(dev, 0, ð->clk);
483 gpio_request_by_name(dev, "reset-gpios", 0, ð->reset_gpio,
486 mdiodev = mdio_alloc();
492 mdiodev->read = bb_miiphy_read;
493 mdiodev->write = bb_miiphy_write;
494 bb_miiphy_buses[0].priv = eth;
495 snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
497 ret = mdio_register(mdiodev);
499 goto err_mdio_register;
501 eth->bus = miiphy_get_dev_by_name(dev->name);
504 ret = clk_enable(ð->clk);
506 goto err_mdio_register;
508 ret = ravb_reset(dev);
512 ret = ravb_phy_config(dev);
519 clk_disable(ð->clk);
523 unmap_physmem(eth->iobase, MAP_NOCACHE);
527 static int ravb_remove(struct udevice *dev)
529 struct ravb_priv *eth = dev_get_priv(dev);
531 clk_disable(ð->clk);
534 mdio_unregister(eth->bus);
536 if (dm_gpio_is_valid(ð->reset_gpio))
537 dm_gpio_free(dev, ð->reset_gpio);
538 unmap_physmem(eth->iobase, MAP_NOCACHE);
543 int ravb_bb_init(struct bb_miiphy_bus *bus)
548 int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
550 struct ravb_priv *eth = bus->priv;
552 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
557 int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
559 struct ravb_priv *eth = bus->priv;
561 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
566 int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
568 struct ravb_priv *eth = bus->priv;
571 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
573 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
578 int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
580 struct ravb_priv *eth = bus->priv;
582 *v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
587 int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
589 struct ravb_priv *eth = bus->priv;
592 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
594 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
599 int ravb_bb_delay(struct bb_miiphy_bus *bus)
606 struct bb_miiphy_bus bb_miiphy_buses[] = {
609 .init = ravb_bb_init,
610 .mdio_active = ravb_bb_mdio_active,
611 .mdio_tristate = ravb_bb_mdio_tristate,
612 .set_mdio = ravb_bb_set_mdio,
613 .get_mdio = ravb_bb_get_mdio,
614 .set_mdc = ravb_bb_set_mdc,
615 .delay = ravb_bb_delay,
618 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
620 static const struct eth_ops ravb_ops = {
624 .free_pkt = ravb_free_pkt,
626 .write_hwaddr = ravb_write_hwaddr,
629 int ravb_ofdata_to_platdata(struct udevice *dev)
631 struct eth_pdata *pdata = dev_get_platdata(dev);
632 const char *phy_mode;
636 pdata->iobase = devfdt_get_addr(dev);
637 pdata->phy_interface = -1;
638 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
641 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
642 if (pdata->phy_interface == -1) {
643 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
647 pdata->max_speed = 1000;
648 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
650 pdata->max_speed = fdt32_to_cpu(*cell);
652 sprintf(bb_miiphy_buses[0].name, dev->name);
657 static const struct udevice_id ravb_ids[] = {
658 { .compatible = "renesas,etheravb-r8a7795" },
659 { .compatible = "renesas,etheravb-r8a7796" },
660 { .compatible = "renesas,etheravb-r8a77965" },
661 { .compatible = "renesas,etheravb-r8a77970" },
662 { .compatible = "renesas,etheravb-r8a77995" },
663 { .compatible = "renesas,etheravb-rcar-gen3" },
667 U_BOOT_DRIVER(eth_ravb) = {
670 .of_match = ravb_ids,
671 .ofdata_to_platdata = ravb_ofdata_to_platdata,
673 .remove = ravb_remove,
675 .priv_auto_alloc_size = sizeof(struct ravb_priv),
676 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
677 .flags = DM_FLAG_ALLOC_PRIV_DMA,