2 * rtl8169.c : U-Boot driver for the RealTek RTL8169
4 * Masami Komiya (mkomiya@sonare.it)
6 * Most part is taken from r8169.c of etherboot
10 /**************************************************************************
11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
12 * Written 2003 by Timothy Legge <tlegge@rogers.com>
14 * SPDX-License-Identifier: GPL-2.0+
16 * Portions of this code based on:
17 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
18 * for Linux kernel 2.4.x.
20 * Written 2002 ShuChen <shuchen@realtek.com.tw>
21 * See Linux Driver for full information
23 * Linux Driver Version 1.27a, 10.02.2002
26 * Jean Chen of RealTek Semiconductor Corp. for
27 * providing the evaluation NIC used to develop
28 * this driver. RealTek's support for Etherboot
34 * v1.0 11-26-2003 timlegge Initial port of Linux driver
35 * v1.5 01-17-2004 timlegge Initial driver output cleanup
37 * Indent Options: indent -kr -i8
38 ***************************************************************************/
40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
41 * Modified to use le32_to_cpu and cpu_to_le32 properly
55 #undef DEBUG_RTL8169_TX
56 #undef DEBUG_RTL8169_RX
58 #define drv_version "v1.5"
59 #define drv_date "01-17-2004"
61 static unsigned long ioaddr;
63 /* Condensed operations for readability. */
64 #define currticks() get_timer(0)
68 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
70 /* MAC address length*/
71 #define MAC_ADDR_LEN 6
73 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
74 #define MAX_ETH_FRAME_SIZE 1536
76 #define TX_FIFO_THRESH 256 /* In bytes */
78 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
79 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
80 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
81 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
82 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
83 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
85 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
86 #ifdef CONFIG_SYS_RX_ETH_BUFFER
87 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER
89 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
91 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
92 #define RX_BUF_LEN 8192
94 #define RTL_MIN_IO_SIZE 0x80
95 #define TX_TIMEOUT (6*HZ)
97 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
98 #define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg))
99 #define RTL_W16(reg, val16) writew((val16), ioaddr + (reg))
100 #define RTL_W32(reg, val32) writel((val32), ioaddr + (reg))
101 #define RTL_R8(reg) readb(ioaddr + (reg))
102 #define RTL_R16(reg) readw(ioaddr + (reg))
103 #define RTL_R32(reg) readl(ioaddr + (reg))
105 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE
106 #define ETH_ALEN MAC_ADDR_LEN
109 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
110 (pci_addr_t)(unsigned long)a)
111 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \
114 enum RTL8169_registers {
115 MAC0 = 0, /* Ethernet hardware address. */
116 MAR0 = 8, /* Multicast filter. */
117 TxDescStartAddrLow = 0x20,
118 TxDescStartAddrHigh = 0x24,
119 TxHDescStartAddrLow = 0x28,
120 TxHDescStartAddrHigh = 0x2c,
145 RxDescStartAddrLow = 0xE4,
146 RxDescStartAddrHigh = 0xE8,
149 FuncEventMask = 0xF4,
150 FuncPresetState = 0xF8,
151 FuncForceEvent = 0xFC,
154 enum RTL8169_register_content {
155 /*InterruptStatusBits */
159 TxDescUnavail = 0x80,
182 Cfg9346_Unlock = 0xC0,
187 AcceptBroadcast = 0x08,
188 AcceptMulticast = 0x04,
190 AcceptAllPhys = 0x01,
197 TxInterFrameGapShift = 24,
198 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
200 /*rtl8169_PHYstatus */
210 /*GIGABIT_PHY_registers */
213 PHY_AUTO_NEGO_REG = 4,
214 PHY_1000_CTRL_REG = 9,
216 /*GIGABIT_PHY_REG_BIT */
217 PHY_Restart_Auto_Nego = 0x0200,
218 PHY_Enable_Auto_Nego = 0x1000,
220 /* PHY_STAT_REG = 1; */
221 PHY_Auto_Nego_Comp = 0x0020,
223 /* PHY_AUTO_NEGO_REG = 4; */
224 PHY_Cap_10_Half = 0x0020,
225 PHY_Cap_10_Full = 0x0040,
226 PHY_Cap_100_Half = 0x0080,
227 PHY_Cap_100_Full = 0x0100,
229 /* PHY_1000_CTRL_REG = 9; */
230 PHY_Cap_1000_Full = 0x0200,
242 TBILinkOK = 0x02000000,
247 u8 version; /* depend on RTL8169 docs */
248 u32 RxConfigMask; /* should clear the bits supported by this chip */
249 } rtl_chip_info[] = {
250 {"RTL-8169", 0x00, 0xff7e1880,},
251 {"RTL-8169", 0x04, 0xff7e1880,},
252 {"RTL-8169", 0x00, 0xff7e1880,},
253 {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
254 {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
255 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
256 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
257 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
258 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
259 {"RTL-8168d/8111d", 0x28, 0xff7e1880,},
260 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
261 {"RTL-8168/8111g", 0x4c, 0xff7e1880,},
262 {"RTL-8101e", 0x34, 0xff7e1880,},
263 {"RTL-8100e", 0x32, 0xff7e1880,},
266 enum _DescStatusBit {
287 static unsigned char rxdata[RX_BUF_LEN];
289 #define RTL8169_DESC_SIZE 16
291 #if ARCH_DMA_MINALIGN > 256
292 # define RTL8169_ALIGN ARCH_DMA_MINALIGN
294 # define RTL8169_ALIGN 256
298 * Warn if the cache-line size is larger than the descriptor size. In such
299 * cases the driver will likely fail because the CPU needs to flush the cache
300 * when requeuing RX buffers, therefore descriptors written by the hardware
303 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
304 * the driver to allocate descriptors from a pool of non-cached memory.
306 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
307 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
308 !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
309 #warning cache-line size is larger than descriptor size
314 * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All
315 * descriptors point to a part of this buffer.
317 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
320 * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All
321 * descriptors point to a part of this buffer.
323 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
325 struct rtl8169_private {
327 void *mmio_addr; /* memory map physical address */
329 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
330 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
331 unsigned long dirty_tx;
332 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
333 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
334 unsigned char *RxBufferRings; /* Index of Rx Buffer */
335 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
336 unsigned char *Tx_skbuff[NUM_TX_DESC];
339 static struct rtl8169_private *tpc;
341 static const u16 rtl8169_intr_mask =
342 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr |
344 static const unsigned int rtl8169_rx_config =
345 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
347 static struct pci_device_id supported[] = {
348 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) },
349 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) },
350 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) },
354 void mdio_write(int RegAddr, int value)
358 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
361 for (i = 2000; i > 0; i--) {
362 /* Check if the RTL8169 has completed writing to the specified MII register */
363 if (!(RTL_R32(PHYAR) & 0x80000000)) {
371 int mdio_read(int RegAddr)
375 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
378 for (i = 2000; i > 0; i--) {
379 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
380 if (RTL_R32(PHYAR) & 0x80000000) {
381 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
390 static int rtl8169_init_board(unsigned long dev_iobase, const char *name)
396 printf ("%s\n", __FUNCTION__);
400 /* Soft reset the chip. */
401 RTL_W8(ChipCmd, CmdReset);
403 /* Check that the chip has finished the reset. */
404 for (i = 1000; i > 0; i--)
405 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
410 /* identify chip attached to board */
411 tmp = RTL_R32(TxConfig);
412 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
414 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
415 if (tmp == rtl_chip_info[i].version) {
421 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
422 printf("PCI device %s: unknown chip version, assuming RTL-8169\n",
424 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
432 * TX and RX descriptors are 16 bytes. This causes problems with the cache
433 * maintenance on CPUs where the cache-line size exceeds the size of these
434 * descriptors. What will happen is that when the driver receives a packet
435 * it will be immediately requeued for the hardware to reuse. The CPU will
436 * therefore need to flush the cache-line containing the descriptor, which
437 * will cause all other descriptors in the same cache-line to be flushed
438 * along with it. If one of those descriptors had been written to by the
439 * device those changes (and the associated packet) will be lost.
441 * To work around this, we make use of non-cached memory if available. If
442 * descriptors are mapped uncached there's no need to manually flush them
443 * or invalidate them.
445 * Note that this only applies to descriptors. The packet data buffers do
446 * not have the same constraints since they are 1536 bytes large, so they
447 * are unlikely to share cache-lines.
449 static void *rtl_alloc_descs(unsigned int num)
451 size_t size = num * RTL8169_DESC_SIZE;
453 #ifdef CONFIG_SYS_NONCACHED_MEMORY
454 return (void *)noncached_alloc(size, RTL8169_ALIGN);
456 return memalign(RTL8169_ALIGN, size);
461 * Cache maintenance functions. These are simple wrappers around the more
462 * general purpose flush_cache() and invalidate_dcache_range() functions.
465 static void rtl_inval_rx_desc(struct RxDesc *desc)
467 #ifndef CONFIG_SYS_NONCACHED_MEMORY
468 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
469 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
471 invalidate_dcache_range(start, end);
475 static void rtl_flush_rx_desc(struct RxDesc *desc)
477 #ifndef CONFIG_SYS_NONCACHED_MEMORY
478 flush_cache((unsigned long)desc, sizeof(*desc));
482 static void rtl_inval_tx_desc(struct TxDesc *desc)
484 #ifndef CONFIG_SYS_NONCACHED_MEMORY
485 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
486 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
488 invalidate_dcache_range(start, end);
492 static void rtl_flush_tx_desc(struct TxDesc *desc)
494 #ifndef CONFIG_SYS_NONCACHED_MEMORY
495 flush_cache((unsigned long)desc, sizeof(*desc));
499 static void rtl_inval_buffer(void *buf, size_t size)
501 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
502 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
504 invalidate_dcache_range(start, end);
507 static void rtl_flush_buffer(void *buf, size_t size)
509 flush_cache((unsigned long)buf, size);
512 /**************************************************************************
513 RECV - Receive a frame
514 ***************************************************************************/
515 static int rtl_recv_common(pci_dev_t bdf, unsigned long dev_iobase,
518 /* return true if there's an ethernet packet ready to read */
519 /* nic->packet should contain data on return */
520 /* nic->packetlen should contain length of data */
524 #ifdef DEBUG_RTL8169_RX
525 printf ("%s\n", __FUNCTION__);
529 cur_rx = tpc->cur_rx;
531 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
533 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
534 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
535 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
536 status) & 0x00001FFF) - 4;
538 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
539 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
541 if (cur_rx == NUM_RX_DESC - 1)
542 tpc->RxDescArray[cur_rx].status =
543 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
545 tpc->RxDescArray[cur_rx].status =
546 cpu_to_le32(OWNbit + RX_BUF_SIZE);
547 tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
548 pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)
549 tpc->RxBufferRing[cur_rx]));
550 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
554 net_process_received_packet(rxdata, length);
560 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
561 tpc->cur_rx = cur_rx;
565 ushort sts = RTL_R8(IntrStatus);
566 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
567 udelay(100); /* wait */
569 tpc->cur_rx = cur_rx;
570 return (0); /* initially as this is called to flush the input */
574 int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp)
576 struct rtl8169_private *priv = dev_get_priv(dev);
578 return rtl_recv_common(pci_get_bdf(dev), priv->iobase, packetp);
581 static int rtl_recv(struct eth_device *dev)
583 return rtl_recv_common((pci_dev_t)dev->priv, dev->iobase, NULL);
585 #endif /* nCONFIG_DM_ETH */
588 /**************************************************************************
589 SEND - Transmit a frame
590 ***************************************************************************/
591 static int rtl_send_common(pci_dev_t bdf, unsigned long dev_iobase,
592 void *packet, int length)
594 /* send the packet to destination */
598 int entry = tpc->cur_tx % NUM_TX_DESC;
602 #ifdef DEBUG_RTL8169_TX
603 int stime = currticks();
604 printf ("%s\n", __FUNCTION__);
605 printf("sending %d bytes\n", len);
610 /* point to the current txb incase multiple tx_rings are used */
611 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
612 memcpy(ptxb, (char *)packet, (int)length);
613 rtl_flush_buffer(ptxb, length);
615 while (len < ETH_ZLEN)
618 tpc->TxDescArray[entry].buf_Haddr = 0;
619 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
620 pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)ptxb));
621 if (entry != (NUM_TX_DESC - 1)) {
622 tpc->TxDescArray[entry].status =
623 cpu_to_le32((OWNbit | FSbit | LSbit) |
624 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
626 tpc->TxDescArray[entry].status =
627 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
628 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
630 rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
631 RTL_W8(TxPoll, 0x40); /* set polling bit */
634 to = currticks() + TX_TIMEOUT;
636 rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
637 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
638 && (currticks() < to)); /* wait */
640 if (currticks() >= to) {
641 #ifdef DEBUG_RTL8169_TX
642 puts("tx timeout/error\n");
643 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
647 #ifdef DEBUG_RTL8169_TX
652 /* Delay to make net console (nc) work properly */
658 int rtl8169_eth_send(struct udevice *dev, void *packet, int length)
660 struct rtl8169_private *priv = dev_get_priv(dev);
662 return rtl_send_common(pci_get_bdf(dev), priv->iobase, packet, length);
666 static int rtl_send(struct eth_device *dev, void *packet, int length)
668 return rtl_send_common((pci_dev_t)dev->priv, dev->iobase, packet,
673 static void rtl8169_set_rx_mode(void)
675 u32 mc_filter[2]; /* Multicast hash filter */
680 printf ("%s\n", __FUNCTION__);
684 /* Too many to filter perfectly -- accept all multicasts. */
685 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
686 mc_filter[1] = mc_filter[0] = 0xffffffff;
688 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
689 rtl_chip_info[tpc->chipset].RxConfigMask);
691 RTL_W32(RxConfig, tmp);
692 RTL_W32(MAR0 + 0, mc_filter[0]);
693 RTL_W32(MAR0 + 4, mc_filter[1]);
696 static void rtl8169_hw_start(pci_dev_t bdf)
701 int stime = currticks();
702 printf ("%s\n", __FUNCTION__);
706 /* Soft reset the chip. */
707 RTL_W8(ChipCmd, CmdReset);
709 /* Check that the chip has finished the reset. */
710 for (i = 1000; i > 0; i--) {
711 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
718 RTL_W8(Cfg9346, Cfg9346_Unlock);
720 /* RTL-8169sb/8110sb or previous version */
721 if (tpc->chipset <= 5)
722 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
724 RTL_W8(EarlyTxThres, EarlyTxThld);
726 /* For gigabit rtl8169 */
727 RTL_W16(RxMaxSize, RxPacketMaxSize);
729 /* Set Rx Config register */
730 i = rtl8169_rx_config | (RTL_R32(RxConfig) &
731 rtl_chip_info[tpc->chipset].RxConfigMask);
732 RTL_W32(RxConfig, i);
734 /* Set DMA burst size and Interframe Gap Time */
735 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
736 (InterFrameGap << TxInterFrameGapShift));
741 RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(bdf,
742 (pci_addr_t)(unsigned long)tpc->TxDescArray));
743 RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
744 RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
745 bdf, (pci_addr_t)(unsigned long)tpc->RxDescArray));
746 RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
748 /* RTL-8169sc/8110sc or later version */
749 if (tpc->chipset > 5)
750 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
752 RTL_W8(Cfg9346, Cfg9346_Lock);
755 RTL_W32(RxMissed, 0);
757 rtl8169_set_rx_mode();
759 /* no early-rx interrupts */
760 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
763 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
767 static void rtl8169_init_ring(pci_dev_t bdf)
772 int stime = currticks();
773 printf ("%s\n", __FUNCTION__);
779 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
780 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
782 for (i = 0; i < NUM_TX_DESC; i++) {
783 tpc->Tx_skbuff[i] = &txb[i];
786 for (i = 0; i < NUM_RX_DESC; i++) {
787 if (i == (NUM_RX_DESC - 1))
788 tpc->RxDescArray[i].status =
789 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
791 tpc->RxDescArray[i].status =
792 cpu_to_le32(OWNbit + RX_BUF_SIZE);
794 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
795 tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys(
796 bdf, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
797 rtl_flush_rx_desc(&tpc->RxDescArray[i]);
801 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
805 static void rtl8169_common_start(pci_dev_t bdf, unsigned char *enetaddr)
810 int stime = currticks();
811 printf ("%s\n", __FUNCTION__);
814 rtl8169_init_ring(bdf);
815 rtl8169_hw_start(bdf);
816 /* Construct a perfect filter frame with the mac address as first match
817 * and broadcast for all others */
818 for (i = 0; i < 192; i++)
821 txb[0] = enetaddr[0];
822 txb[1] = enetaddr[1];
823 txb[2] = enetaddr[2];
824 txb[3] = enetaddr[3];
825 txb[4] = enetaddr[4];
826 txb[5] = enetaddr[5];
829 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
834 static int rtl8169_eth_start(struct udevice *dev)
836 struct eth_pdata *plat = dev_get_platdata(dev);
838 rtl8169_common_start(pci_get_bdf(dev), plat->enetaddr);
843 /**************************************************************************
844 RESET - Finish setting up the ethernet interface
845 ***************************************************************************/
846 static int rtl_reset(struct eth_device *dev, bd_t *bis)
848 rtl8169_common_start((pci_dev_t)dev->priv, dev->enetaddr);
852 #endif /* nCONFIG_DM_ETH */
854 static void rtl_halt_common(unsigned long dev_iobase)
859 printf ("%s\n", __FUNCTION__);
864 /* Stop the chip's Tx and Rx DMA processes. */
865 RTL_W8(ChipCmd, 0x00);
867 /* Disable interrupts by clearing the interrupt mask. */
868 RTL_W16(IntrMask, 0x0000);
870 RTL_W32(RxMissed, 0);
872 for (i = 0; i < NUM_RX_DESC; i++) {
873 tpc->RxBufferRing[i] = NULL;
878 void rtl8169_eth_stop(struct udevice *dev)
880 struct rtl8169_private *priv = dev_get_priv(dev);
882 rtl_halt_common(priv->iobase);
885 /**************************************************************************
886 HALT - Turn off ethernet interface
887 ***************************************************************************/
888 static void rtl_halt(struct eth_device *dev)
890 rtl_halt_common(dev->iobase);
894 /**************************************************************************
895 INIT - Look for an adapter, this routine's visible to the outside
896 ***************************************************************************/
898 #define board_found 1
900 static int rtl_init(unsigned long dev_ioaddr, const char *name,
901 unsigned char *enetaddr)
903 static int board_idx = -1;
905 int option = -1, Cap10_100 = 0, Cap1000 = 0;
908 printf ("%s\n", __FUNCTION__);
914 /* point to private storage */
917 rc = rtl8169_init_board(ioaddr, name);
921 /* Get MAC address. FIXME: read EEPROM */
922 for (i = 0; i < MAC_ADDR_LEN; i++)
923 enetaddr[i] = RTL_R8(MAC0 + i);
926 printf("chipset = %d\n", tpc->chipset);
927 printf("MAC Address");
928 for (i = 0; i < MAC_ADDR_LEN; i++)
929 printf(":%02x", enetaddr[i]);
934 /* Print out some hardware info */
935 printf("%s: at ioaddr 0x%lx\n", name, ioaddr);
938 /* if TBI is not endbled */
939 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
940 int val = mdio_read(PHY_AUTO_NEGO_REG);
942 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
943 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
946 printf("%s: Force-mode Enabled.\n", dev->name);
948 Cap10_100 = 0, Cap1000 = 0;
951 Cap10_100 = PHY_Cap_10_Half;
952 Cap1000 = PHY_Cap_Null;
955 Cap10_100 = PHY_Cap_10_Full;
956 Cap1000 = PHY_Cap_Null;
959 Cap10_100 = PHY_Cap_100_Half;
960 Cap1000 = PHY_Cap_Null;
963 Cap10_100 = PHY_Cap_100_Full;
964 Cap1000 = PHY_Cap_Null;
967 Cap10_100 = PHY_Cap_Null;
968 Cap1000 = PHY_Cap_1000_Full;
973 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
974 mdio_write(PHY_1000_CTRL_REG, Cap1000);
977 printf("%s: Auto-negotiation Enabled.\n",
980 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
981 mdio_write(PHY_AUTO_NEGO_REG,
982 PHY_Cap_10_Half | PHY_Cap_10_Full |
983 PHY_Cap_100_Half | PHY_Cap_100_Full |
986 /* enable 1000 Full Mode */
987 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
991 /* Enable auto-negotiation and restart auto-nigotiation */
992 mdio_write(PHY_CTRL_REG,
993 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
996 /* wait for auto-negotiation process */
997 for (i = 10000; i > 0; i--) {
998 /* check if auto-negotiation complete */
999 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
1001 option = RTL_R8(PHYstatus);
1002 if (option & _1000bpsF) {
1003 #ifdef DEBUG_RTL8169
1004 printf("%s: 1000Mbps Full-duplex operation.\n",
1008 #ifdef DEBUG_RTL8169
1009 printf("%s: %sMbps %s-duplex operation.\n",
1011 (option & _100bps) ? "100" :
1013 (option & FullDup) ? "Full" :
1021 } /* end for-loop to wait for auto-negotiation process */
1025 #ifdef DEBUG_RTL8169
1027 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1029 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
1034 tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
1035 if (!tpc->RxDescArray)
1038 tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC);
1039 if (!tpc->TxDescArray)
1045 #ifndef CONFIG_DM_ETH
1046 int rtl8169_initialize(bd_t *bis)
1049 int card_number = 0;
1050 struct eth_device *dev;
1055 unsigned int region;
1060 if ((devno = pci_find_devices(supported, idx++)) < 0)
1063 pci_read_config_word(devno, PCI_DEVICE_ID, &device);
1074 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
1077 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
1079 dev = (struct eth_device *)malloc(sizeof *dev);
1081 printf("Can not allocate memory of rtl8169\n");
1085 memset(dev, 0, sizeof(*dev));
1086 sprintf (dev->name, "RTL8169#%d", card_number);
1088 dev->priv = (void *)(unsigned long)devno;
1089 dev->iobase = (int)pci_mem_to_phys(devno, iobase);
1091 dev->init = rtl_reset;
1092 dev->halt = rtl_halt;
1093 dev->send = rtl_send;
1094 dev->recv = rtl_recv;
1096 err = rtl_init(dev->iobase, dev->name, dev->enetaddr);
1098 printf(pr_fmt("failed to initialize card: %d\n"), err);
1111 #ifdef CONFIG_DM_ETH
1112 static int rtl8169_eth_probe(struct udevice *dev)
1114 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
1115 struct rtl8169_private *priv = dev_get_priv(dev);
1116 struct eth_pdata *plat = dev_get_platdata(dev);
1121 debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
1122 switch (pplat->device) {
1130 pci_read_config32(pci_get_bdf(dev), PCI_BASE_ADDRESS_0 + region * 4,
1133 priv->iobase = (int)pci_mem_to_phys(pci_get_bdf(dev), iobase);
1135 ret = rtl_init(priv->iobase, dev->name, plat->enetaddr);
1137 printf(pr_fmt("failed to initialize card: %d\n"), ret);
1144 static const struct eth_ops rtl8169_eth_ops = {
1145 .start = rtl8169_eth_start,
1146 .send = rtl8169_eth_send,
1147 .recv = rtl8169_eth_recv,
1148 .stop = rtl8169_eth_stop,
1151 static const struct udevice_id rtl8169_eth_ids[] = {
1152 { .compatible = "realtek,rtl8169" },
1156 U_BOOT_DRIVER(eth_rtl8169) = {
1157 .name = "eth_rtl8169",
1159 .of_match = rtl8169_eth_ids,
1160 .probe = rtl8169_eth_probe,
1161 .ops = &rtl8169_eth_ops,
1162 .priv_auto_alloc_size = sizeof(struct rtl8169_private),
1163 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1166 U_BOOT_PCI_DEVICE(eth_rtl8169, supported);