]> git.sur5r.net Git - u-boot/blob - drivers/net/sh_eth.c
net: sh-eth: Remove bd_t from sh_eth_config()
[u-boot] / drivers / net / sh_eth.c
1 /*
2  * sh_eth.c - Driver for Renesas ethernet controller.
3  *
4  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
5  * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
6  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
7  * Copyright (C) 2013, 2014 Renesas Electronics Corporation
8  *
9  * SPDX-License-Identifier:     GPL-2.0+
10  */
11
12 #include <config.h>
13 #include <common.h>
14 #include <malloc.h>
15 #include <net.h>
16 #include <netdev.h>
17 #include <miiphy.h>
18 #include <linux/errno.h>
19 #include <asm/io.h>
20
21 #include "sh_eth.h"
22
23 #ifndef CONFIG_SH_ETHER_USE_PORT
24 # error "Please define CONFIG_SH_ETHER_USE_PORT"
25 #endif
26 #ifndef CONFIG_SH_ETHER_PHY_ADDR
27 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
28 #endif
29
30 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
31 #define flush_cache_wback(addr, len)    \
32                 flush_dcache_range((u32)addr, (u32)(addr + len - 1))
33 #else
34 #define flush_cache_wback(...)
35 #endif
36
37 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
38 #define invalidate_cache(addr, len)             \
39         {       \
40                 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;    \
41                 u32 start, end; \
42                 \
43                 start = (u32)addr;      \
44                 end = start + len;      \
45                 start &= ~(line_size - 1);      \
46                 end = ((end + line_size - 1) & ~(line_size - 1));       \
47                 \
48                 invalidate_dcache_range(start, end);    \
49         }
50 #else
51 #define invalidate_cache(...)
52 #endif
53
54 #define TIMEOUT_CNT 1000
55
56 int sh_eth_send(struct eth_device *dev, void *packet, int len)
57 {
58         struct sh_eth_dev *eth = dev->priv;
59         int port = eth->port, ret = 0, timeout;
60         struct sh_eth_info *port_info = &eth->port_info[port];
61
62         if (!packet || len > 0xffff) {
63                 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
64                 ret = -EINVAL;
65                 goto err;
66         }
67
68         /* packet must be a 4 byte boundary */
69         if ((int)packet & 3) {
70                 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
71                                 , __func__);
72                 ret = -EFAULT;
73                 goto err;
74         }
75
76         /* Update tx descriptor */
77         flush_cache_wback(packet, len);
78         port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
79         port_info->tx_desc_cur->td1 = len << 16;
80         /* Must preserve the end of descriptor list indication */
81         if (port_info->tx_desc_cur->td0 & TD_TDLE)
82                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
83         else
84                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
85
86         flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
87
88         /* Restart the transmitter if disabled */
89         if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
90                 sh_eth_write(eth, EDTRR_TRNS, EDTRR);
91
92         /* Wait until packet is transmitted */
93         timeout = TIMEOUT_CNT;
94         do {
95                 invalidate_cache(port_info->tx_desc_cur,
96                                  sizeof(struct tx_desc_s));
97                 udelay(100);
98         } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
99
100         if (timeout < 0) {
101                 printf(SHETHER_NAME ": transmit timeout\n");
102                 ret = -ETIMEDOUT;
103                 goto err;
104         }
105
106         port_info->tx_desc_cur++;
107         if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
108                 port_info->tx_desc_cur = port_info->tx_desc_base;
109
110 err:
111         return ret;
112 }
113
114 int sh_eth_recv(struct eth_device *dev)
115 {
116         struct sh_eth_dev *eth = dev->priv;
117         int port = eth->port, len = 0;
118         struct sh_eth_info *port_info = &eth->port_info[port];
119         uchar *packet;
120
121         /* Check if the rx descriptor is ready */
122         invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
123         if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
124                 /* Check for errors */
125                 if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
126                         len = port_info->rx_desc_cur->rd1 & 0xffff;
127                         packet = (uchar *)
128                                 ADDR_TO_P2(port_info->rx_desc_cur->rd2);
129                         invalidate_cache(packet, len);
130                         net_process_received_packet(packet, len);
131                 }
132
133                 /* Make current descriptor available again */
134                 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
135                         port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
136                 else
137                         port_info->rx_desc_cur->rd0 = RD_RACT;
138
139                 flush_cache_wback(port_info->rx_desc_cur,
140                                   sizeof(struct rx_desc_s));
141
142                 /* Point to the next descriptor */
143                 port_info->rx_desc_cur++;
144                 if (port_info->rx_desc_cur >=
145                     port_info->rx_desc_base + NUM_RX_DESC)
146                         port_info->rx_desc_cur = port_info->rx_desc_base;
147         }
148
149         /* Restart the receiver if disabled */
150         if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
151                 sh_eth_write(eth, EDRRR_R, EDRRR);
152
153         return len;
154 }
155
156 static int sh_eth_reset(struct sh_eth_dev *eth)
157 {
158 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
159         int ret = 0, i;
160
161         /* Start e-dmac transmitter and receiver */
162         sh_eth_write(eth, EDSR_ENALL, EDSR);
163
164         /* Perform a software reset and wait for it to complete */
165         sh_eth_write(eth, EDMR_SRST, EDMR);
166         for (i = 0; i < TIMEOUT_CNT; i++) {
167                 if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
168                         break;
169                 udelay(1000);
170         }
171
172         if (i == TIMEOUT_CNT) {
173                 printf(SHETHER_NAME  ": Software reset timeout\n");
174                 ret = -EIO;
175         }
176
177         return ret;
178 #else
179         sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR);
180         udelay(3000);
181         sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);
182
183         return 0;
184 #endif
185 }
186
187 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
188 {
189         int port = eth->port, i, ret = 0;
190         u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
191         struct sh_eth_info *port_info = &eth->port_info[port];
192         struct tx_desc_s *cur_tx_desc;
193
194         /*
195          * Allocate rx descriptors. They must be aligned to size of struct
196          * tx_desc_s.
197          */
198         port_info->tx_desc_alloc =
199                 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
200         if (!port_info->tx_desc_alloc) {
201                 printf(SHETHER_NAME ": memalign failed\n");
202                 ret = -ENOMEM;
203                 goto err;
204         }
205
206         flush_cache_wback((u32)port_info->tx_desc_alloc, alloc_desc_size);
207
208         /* Make sure we use a P2 address (non-cacheable) */
209         port_info->tx_desc_base =
210                 (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
211         port_info->tx_desc_cur = port_info->tx_desc_base;
212
213         /* Initialize all descriptors */
214         for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
215              cur_tx_desc++, i++) {
216                 cur_tx_desc->td0 = 0x00;
217                 cur_tx_desc->td1 = 0x00;
218                 cur_tx_desc->td2 = 0x00;
219         }
220
221         /* Mark the end of the descriptors */
222         cur_tx_desc--;
223         cur_tx_desc->td0 |= TD_TDLE;
224
225         /*
226          * Point the controller to the tx descriptor list. Must use physical
227          * addresses
228          */
229         sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
230 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
231         sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
232         sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
233         sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
234 #endif
235
236 err:
237         return ret;
238 }
239
240 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
241 {
242         int port = eth->port, i, ret = 0;
243         u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
244         struct sh_eth_info *port_info = &eth->port_info[port];
245         struct rx_desc_s *cur_rx_desc;
246         u8 *rx_buf;
247
248         /*
249          * Allocate rx descriptors. They must be aligned to size of struct
250          * rx_desc_s.
251          */
252         port_info->rx_desc_alloc =
253                 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
254         if (!port_info->rx_desc_alloc) {
255                 printf(SHETHER_NAME ": memalign failed\n");
256                 ret = -ENOMEM;
257                 goto err;
258         }
259
260         flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
261
262         /* Make sure we use a P2 address (non-cacheable) */
263         port_info->rx_desc_base =
264                 (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
265
266         port_info->rx_desc_cur = port_info->rx_desc_base;
267
268         /*
269          * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
270          * aligned and in P2 area.
271          */
272         port_info->rx_buf_alloc =
273                 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
274         if (!port_info->rx_buf_alloc) {
275                 printf(SHETHER_NAME ": alloc failed\n");
276                 ret = -ENOMEM;
277                 goto err_buf_alloc;
278         }
279
280         port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
281
282         /* Initialize all descriptors */
283         for (cur_rx_desc = port_info->rx_desc_base,
284              rx_buf = port_info->rx_buf_base, i = 0;
285              i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
286                 cur_rx_desc->rd0 = RD_RACT;
287                 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
288                 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
289         }
290
291         /* Mark the end of the descriptors */
292         cur_rx_desc--;
293         cur_rx_desc->rd0 |= RD_RDLE;
294
295         /* Point the controller to the rx descriptor list */
296         sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
297 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
298         sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
299         sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
300         sh_eth_write(eth, RDFFR_RDLF, RDFFR);
301 #endif
302
303         return ret;
304
305 err_buf_alloc:
306         free(port_info->rx_desc_alloc);
307         port_info->rx_desc_alloc = NULL;
308
309 err:
310         return ret;
311 }
312
313 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
314 {
315         int port = eth->port;
316         struct sh_eth_info *port_info = &eth->port_info[port];
317
318         if (port_info->tx_desc_alloc) {
319                 free(port_info->tx_desc_alloc);
320                 port_info->tx_desc_alloc = NULL;
321         }
322 }
323
324 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
325 {
326         int port = eth->port;
327         struct sh_eth_info *port_info = &eth->port_info[port];
328
329         if (port_info->rx_desc_alloc) {
330                 free(port_info->rx_desc_alloc);
331                 port_info->rx_desc_alloc = NULL;
332         }
333
334         if (port_info->rx_buf_alloc) {
335                 free(port_info->rx_buf_alloc);
336                 port_info->rx_buf_alloc = NULL;
337         }
338 }
339
340 static int sh_eth_desc_init(struct sh_eth_dev *eth)
341 {
342         int ret = 0;
343
344         ret = sh_eth_tx_desc_init(eth);
345         if (ret)
346                 goto err_tx_init;
347
348         ret = sh_eth_rx_desc_init(eth);
349         if (ret)
350                 goto err_rx_init;
351
352         return ret;
353 err_rx_init:
354         sh_eth_tx_desc_free(eth);
355
356 err_tx_init:
357         return ret;
358 }
359
360 static int sh_eth_phy_config(struct sh_eth_dev *eth)
361 {
362         int port = eth->port, ret = 0;
363         struct sh_eth_info *port_info = &eth->port_info[port];
364         struct eth_device *dev = port_info->dev;
365         struct phy_device *phydev;
366
367         phydev = phy_connect(
368                         miiphy_get_dev_by_name(dev->name),
369                         port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
370         port_info->phydev = phydev;
371         phy_config(phydev);
372
373         return ret;
374 }
375
376 static int sh_eth_config(struct sh_eth_dev *eth)
377 {
378         int port = eth->port, ret = 0;
379         u32 val;
380         struct sh_eth_info *port_info = &eth->port_info[port];
381         struct eth_device *dev = port_info->dev;
382         struct phy_device *phy;
383
384         /* Configure e-dmac registers */
385         sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) |
386                         (EMDR_DESC | EDMR_EL), EDMR);
387
388         sh_eth_write(eth, 0, EESIPR);
389         sh_eth_write(eth, 0, TRSCER);
390         sh_eth_write(eth, 0, TFTR);
391         sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
392         sh_eth_write(eth, RMCR_RST, RMCR);
393 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
394         sh_eth_write(eth, 0, RPADIR);
395 #endif
396         sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
397
398         /* Configure e-mac registers */
399         sh_eth_write(eth, 0, ECSIPR);
400
401         /* Set Mac address */
402         val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
403             dev->enetaddr[2] << 8 | dev->enetaddr[3];
404         sh_eth_write(eth, val, MAHR);
405
406         val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
407         sh_eth_write(eth, val, MALR);
408
409         sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
410 #if defined(SH_ETH_TYPE_GETHER)
411         sh_eth_write(eth, 0, PIPR);
412 #endif
413 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
414         sh_eth_write(eth, APR_AP, APR);
415         sh_eth_write(eth, MPR_MP, MPR);
416         sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
417 #endif
418
419 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
420         sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
421 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
422         defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
423         sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
424 #endif
425         /* Configure phy */
426         ret = sh_eth_phy_config(eth);
427         if (ret) {
428                 printf(SHETHER_NAME ": phy config timeout\n");
429                 goto err_phy_cfg;
430         }
431         phy = port_info->phydev;
432         ret = phy_startup(phy);
433         if (ret) {
434                 printf(SHETHER_NAME ": phy startup failure\n");
435                 return ret;
436         }
437
438         val = 0;
439
440         /* Set the transfer speed */
441         if (phy->speed == 100) {
442                 printf(SHETHER_NAME ": 100Base/");
443 #if defined(SH_ETH_TYPE_GETHER)
444                 sh_eth_write(eth, GECMR_100B, GECMR);
445 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
446                 sh_eth_write(eth, 1, RTRATE);
447 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
448                 defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
449                 defined(CONFIG_R8A7794)
450                 val = ECMR_RTM;
451 #endif
452         } else if (phy->speed == 10) {
453                 printf(SHETHER_NAME ": 10Base/");
454 #if defined(SH_ETH_TYPE_GETHER)
455                 sh_eth_write(eth, GECMR_10B, GECMR);
456 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
457                 sh_eth_write(eth, 0, RTRATE);
458 #endif
459         }
460 #if defined(SH_ETH_TYPE_GETHER)
461         else if (phy->speed == 1000) {
462                 printf(SHETHER_NAME ": 1000Base/");
463                 sh_eth_write(eth, GECMR_1000B, GECMR);
464         }
465 #endif
466
467         /* Check if full duplex mode is supported by the phy */
468         if (phy->duplex) {
469                 printf("Full\n");
470                 sh_eth_write(eth,
471                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
472                              ECMR);
473         } else {
474                 printf("Half\n");
475                 sh_eth_write(eth,
476                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
477                              ECMR);
478         }
479
480         return ret;
481
482 err_phy_cfg:
483         return ret;
484 }
485
486 static void sh_eth_start(struct sh_eth_dev *eth)
487 {
488         /*
489          * Enable the e-dmac receiver only. The transmitter will be enabled when
490          * we have something to transmit
491          */
492         sh_eth_write(eth, EDRRR_R, EDRRR);
493 }
494
495 static void sh_eth_stop(struct sh_eth_dev *eth)
496 {
497         sh_eth_write(eth, ~EDRRR_R, EDRRR);
498 }
499
500 int sh_eth_init(struct eth_device *dev, bd_t *bd)
501 {
502         int ret = 0;
503         struct sh_eth_dev *eth = dev->priv;
504
505         ret = sh_eth_reset(eth);
506         if (ret)
507                 goto err;
508
509         ret = sh_eth_desc_init(eth);
510         if (ret)
511                 goto err;
512
513         ret = sh_eth_config(eth);
514         if (ret)
515                 goto err_config;
516
517         sh_eth_start(eth);
518
519         return ret;
520
521 err_config:
522         sh_eth_tx_desc_free(eth);
523         sh_eth_rx_desc_free(eth);
524
525 err:
526         return ret;
527 }
528
529 void sh_eth_halt(struct eth_device *dev)
530 {
531         struct sh_eth_dev *eth = dev->priv;
532
533         sh_eth_stop(eth);
534 }
535
536 int sh_eth_initialize(bd_t *bd)
537 {
538         int ret = 0;
539         struct sh_eth_dev *eth = NULL;
540         struct eth_device *dev = NULL;
541         struct mii_dev *mdiodev;
542
543         eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
544         if (!eth) {
545                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
546                 ret = -ENOMEM;
547                 goto err;
548         }
549
550         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
551         if (!dev) {
552                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
553                 ret = -ENOMEM;
554                 goto err;
555         }
556         memset(dev, 0, sizeof(struct eth_device));
557         memset(eth, 0, sizeof(struct sh_eth_dev));
558
559         eth->port = CONFIG_SH_ETHER_USE_PORT;
560         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
561
562         dev->priv = (void *)eth;
563         dev->iobase = 0;
564         dev->init = sh_eth_init;
565         dev->halt = sh_eth_halt;
566         dev->send = sh_eth_send;
567         dev->recv = sh_eth_recv;
568         eth->port_info[eth->port].dev = dev;
569
570         strcpy(dev->name, SHETHER_NAME);
571
572         /* Register Device to EtherNet subsystem  */
573         eth_register(dev);
574
575         bb_miiphy_buses[0].priv = eth;
576         mdiodev = mdio_alloc();
577         if (!mdiodev)
578                 return -ENOMEM;
579         strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
580         mdiodev->read = bb_miiphy_read;
581         mdiodev->write = bb_miiphy_write;
582
583         ret = mdio_register(mdiodev);
584         if (ret < 0)
585                 return ret;
586
587         if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
588                 puts("Please set MAC address\n");
589
590         return ret;
591
592 err:
593         if (dev)
594                 free(dev);
595
596         if (eth)
597                 free(eth);
598
599         printf(SHETHER_NAME ": Failed\n");
600         return ret;
601 }
602
603 /******* for bb_miiphy *******/
604 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
605 {
606         return 0;
607 }
608
609 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
610 {
611         struct sh_eth_dev *eth = bus->priv;
612
613         sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR);
614
615         return 0;
616 }
617
618 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
619 {
620         struct sh_eth_dev *eth = bus->priv;
621
622         sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);
623
624         return 0;
625 }
626
627 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
628 {
629         struct sh_eth_dev *eth = bus->priv;
630
631         if (v)
632                 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR);
633         else
634                 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);
635
636         return 0;
637 }
638
639 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
640 {
641         struct sh_eth_dev *eth = bus->priv;
642
643         *v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;
644
645         return 0;
646 }
647
648 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
649 {
650         struct sh_eth_dev *eth = bus->priv;
651
652         if (v)
653                 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR);
654         else
655                 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);
656
657         return 0;
658 }
659
660 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
661 {
662         udelay(10);
663
664         return 0;
665 }
666
667 struct bb_miiphy_bus bb_miiphy_buses[] = {
668         {
669                 .name           = "sh_eth",
670                 .init           = sh_eth_bb_init,
671                 .mdio_active    = sh_eth_bb_mdio_active,
672                 .mdio_tristate  = sh_eth_bb_mdio_tristate,
673                 .set_mdio       = sh_eth_bb_set_mdio,
674                 .get_mdio       = sh_eth_bb_get_mdio,
675                 .set_mdc        = sh_eth_bb_set_mdc,
676                 .delay          = sh_eth_bb_delay,
677         }
678 };
679
680 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);