2 * sh_eth.c - Driver for Renesas ethernet controller.
4 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
5 * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
7 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
9 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/errno.h>
24 #include <linux/mii.h>
30 #ifndef CONFIG_SH_ETHER_USE_PORT
31 # error "Please define CONFIG_SH_ETHER_USE_PORT"
33 #ifndef CONFIG_SH_ETHER_PHY_ADDR
34 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
37 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
38 #define flush_cache_wback(addr, len) \
39 flush_dcache_range((u32)addr, \
40 (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
42 #define flush_cache_wback(...)
45 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
46 #define invalidate_cache(addr, len) \
48 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
53 start &= ~(line_size - 1); \
54 end = ((end + line_size - 1) & ~(line_size - 1)); \
56 invalidate_dcache_range(start, end); \
59 #define invalidate_cache(...)
62 #define TIMEOUT_CNT 1000
64 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
66 int port = eth->port, ret = 0, timeout;
67 struct sh_eth_info *port_info = ð->port_info[port];
69 if (!packet || len > 0xffff) {
70 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
75 /* packet must be a 4 byte boundary */
76 if ((int)packet & 3) {
77 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
83 /* Update tx descriptor */
84 flush_cache_wback(packet, len);
85 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
86 port_info->tx_desc_cur->td1 = len << 16;
87 /* Must preserve the end of descriptor list indication */
88 if (port_info->tx_desc_cur->td0 & TD_TDLE)
89 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
91 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
93 flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
95 /* Restart the transmitter if disabled */
96 if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
97 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
99 /* Wait until packet is transmitted */
100 timeout = TIMEOUT_CNT;
102 invalidate_cache(port_info->tx_desc_cur,
103 sizeof(struct tx_desc_s));
105 } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
108 printf(SHETHER_NAME ": transmit timeout\n");
113 port_info->tx_desc_cur++;
114 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
115 port_info->tx_desc_cur = port_info->tx_desc_base;
121 static int sh_eth_recv_start(struct sh_eth_dev *eth)
123 int port = eth->port, len = 0;
124 struct sh_eth_info *port_info = ð->port_info[port];
126 /* Check if the rx descriptor is ready */
127 invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
128 if (port_info->rx_desc_cur->rd0 & RD_RACT)
131 /* Check for errors */
132 if (port_info->rx_desc_cur->rd0 & RD_RFE)
135 len = port_info->rx_desc_cur->rd1 & 0xffff;
140 static void sh_eth_recv_finish(struct sh_eth_dev *eth)
142 struct sh_eth_info *port_info = ð->port_info[eth->port];
144 /* Make current descriptor available again */
145 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
146 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
148 port_info->rx_desc_cur->rd0 = RD_RACT;
150 flush_cache_wback(port_info->rx_desc_cur,
151 sizeof(struct rx_desc_s));
153 /* Point to the next descriptor */
154 port_info->rx_desc_cur++;
155 if (port_info->rx_desc_cur >=
156 port_info->rx_desc_base + NUM_RX_DESC)
157 port_info->rx_desc_cur = port_info->rx_desc_base;
160 static int sh_eth_reset(struct sh_eth_dev *eth)
162 struct sh_eth_info *port_info = ð->port_info[eth->port];
163 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
166 /* Start e-dmac transmitter and receiver */
167 sh_eth_write(port_info, EDSR_ENALL, EDSR);
169 /* Perform a software reset and wait for it to complete */
170 sh_eth_write(port_info, EDMR_SRST, EDMR);
171 for (i = 0; i < TIMEOUT_CNT; i++) {
172 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
177 if (i == TIMEOUT_CNT) {
178 printf(SHETHER_NAME ": Software reset timeout\n");
184 sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
186 sh_eth_write(port_info,
187 sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
193 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
195 int port = eth->port, i, ret = 0;
196 u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
197 struct sh_eth_info *port_info = ð->port_info[port];
198 struct tx_desc_s *cur_tx_desc;
201 * Allocate rx descriptors. They must be aligned to size of struct
204 port_info->tx_desc_alloc =
205 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
206 if (!port_info->tx_desc_alloc) {
207 printf(SHETHER_NAME ": memalign failed\n");
212 flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
214 /* Make sure we use a P2 address (non-cacheable) */
215 port_info->tx_desc_base =
216 (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
217 port_info->tx_desc_cur = port_info->tx_desc_base;
219 /* Initialize all descriptors */
220 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
221 cur_tx_desc++, i++) {
222 cur_tx_desc->td0 = 0x00;
223 cur_tx_desc->td1 = 0x00;
224 cur_tx_desc->td2 = 0x00;
227 /* Mark the end of the descriptors */
229 cur_tx_desc->td0 |= TD_TDLE;
232 * Point the controller to the tx descriptor list. Must use physical
235 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
236 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
237 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
238 sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
239 sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
246 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
248 int port = eth->port, i, ret = 0;
249 u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
250 struct sh_eth_info *port_info = ð->port_info[port];
251 struct rx_desc_s *cur_rx_desc;
255 * Allocate rx descriptors. They must be aligned to size of struct
258 port_info->rx_desc_alloc =
259 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
260 if (!port_info->rx_desc_alloc) {
261 printf(SHETHER_NAME ": memalign failed\n");
266 flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
268 /* Make sure we use a P2 address (non-cacheable) */
269 port_info->rx_desc_base =
270 (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
272 port_info->rx_desc_cur = port_info->rx_desc_base;
275 * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
276 * aligned and in P2 area.
278 port_info->rx_buf_alloc =
279 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
280 if (!port_info->rx_buf_alloc) {
281 printf(SHETHER_NAME ": alloc failed\n");
286 port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
288 /* Initialize all descriptors */
289 for (cur_rx_desc = port_info->rx_desc_base,
290 rx_buf = port_info->rx_buf_base, i = 0;
291 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
292 cur_rx_desc->rd0 = RD_RACT;
293 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
294 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
297 /* Mark the end of the descriptors */
299 cur_rx_desc->rd0 |= RD_RDLE;
301 /* Point the controller to the rx descriptor list */
302 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
303 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
304 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
305 sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
306 sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
312 free(port_info->rx_desc_alloc);
313 port_info->rx_desc_alloc = NULL;
319 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
321 int port = eth->port;
322 struct sh_eth_info *port_info = ð->port_info[port];
324 if (port_info->tx_desc_alloc) {
325 free(port_info->tx_desc_alloc);
326 port_info->tx_desc_alloc = NULL;
330 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
332 int port = eth->port;
333 struct sh_eth_info *port_info = ð->port_info[port];
335 if (port_info->rx_desc_alloc) {
336 free(port_info->rx_desc_alloc);
337 port_info->rx_desc_alloc = NULL;
340 if (port_info->rx_buf_alloc) {
341 free(port_info->rx_buf_alloc);
342 port_info->rx_buf_alloc = NULL;
346 static int sh_eth_desc_init(struct sh_eth_dev *eth)
350 ret = sh_eth_tx_desc_init(eth);
354 ret = sh_eth_rx_desc_init(eth);
360 sh_eth_tx_desc_free(eth);
366 static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
371 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
372 sh_eth_write(port_info, val, MAHR);
374 val = (mac[4] << 8) | mac[5];
375 sh_eth_write(port_info, val, MALR);
378 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
380 struct sh_eth_info *port_info = ð->port_info[eth->port];
382 /* Configure e-dmac registers */
383 sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
384 (EMDR_DESC | EDMR_EL), EDMR);
386 sh_eth_write(port_info, 0, EESIPR);
387 sh_eth_write(port_info, 0, TRSCER);
388 sh_eth_write(port_info, 0, TFTR);
389 sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
390 sh_eth_write(port_info, RMCR_RST, RMCR);
391 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
392 sh_eth_write(port_info, 0, RPADIR);
394 sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
396 /* Configure e-mac registers */
397 sh_eth_write(port_info, 0, ECSIPR);
399 /* Set Mac address */
400 sh_eth_write_hwaddr(port_info, mac);
402 sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
403 #if defined(SH_ETH_TYPE_GETHER)
404 sh_eth_write(port_info, 0, PIPR);
406 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
407 sh_eth_write(port_info, APR_AP, APR);
408 sh_eth_write(port_info, MPR_MP, MPR);
409 sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
412 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
413 sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
414 #elif defined(CONFIG_RCAR_GEN2)
415 sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
419 static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
421 struct sh_eth_info *port_info = ð->port_info[eth->port];
422 struct phy_device *phy = port_info->phydev;
426 /* Set the transfer speed */
427 if (phy->speed == 100) {
428 printf(SHETHER_NAME ": 100Base/");
429 #if defined(SH_ETH_TYPE_GETHER)
430 sh_eth_write(port_info, GECMR_100B, GECMR);
431 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
432 sh_eth_write(port_info, 1, RTRATE);
433 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2)
436 } else if (phy->speed == 10) {
437 printf(SHETHER_NAME ": 10Base/");
438 #if defined(SH_ETH_TYPE_GETHER)
439 sh_eth_write(port_info, GECMR_10B, GECMR);
440 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
441 sh_eth_write(port_info, 0, RTRATE);
444 #if defined(SH_ETH_TYPE_GETHER)
445 else if (phy->speed == 1000) {
446 printf(SHETHER_NAME ": 1000Base/");
447 sh_eth_write(port_info, GECMR_1000B, GECMR);
451 /* Check if full duplex mode is supported by the phy */
454 sh_eth_write(port_info,
455 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
459 sh_eth_write(port_info,
460 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
467 static void sh_eth_start(struct sh_eth_dev *eth)
469 struct sh_eth_info *port_info = ð->port_info[eth->port];
472 * Enable the e-dmac receiver only. The transmitter will be enabled when
473 * we have something to transmit
475 sh_eth_write(port_info, EDRRR_R, EDRRR);
478 static void sh_eth_stop(struct sh_eth_dev *eth)
480 struct sh_eth_info *port_info = ð->port_info[eth->port];
482 sh_eth_write(port_info, ~EDRRR_R, EDRRR);
485 static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
489 ret = sh_eth_reset(eth);
493 ret = sh_eth_desc_init(eth);
497 sh_eth_mac_regs_config(eth, mac);
502 static int sh_eth_start_common(struct sh_eth_dev *eth)
504 struct sh_eth_info *port_info = ð->port_info[eth->port];
507 ret = phy_startup(port_info->phydev);
509 printf(SHETHER_NAME ": phy startup failure\n");
513 ret = sh_eth_phy_regs_config(eth);
522 #ifndef CONFIG_DM_ETH
523 static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
525 int port = eth->port, ret = 0;
526 struct sh_eth_info *port_info = ð->port_info[port];
527 struct eth_device *dev = port_info->dev;
528 struct phy_device *phydev;
530 phydev = phy_connect(
531 miiphy_get_dev_by_name(dev->name),
532 port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
533 port_info->phydev = phydev;
539 static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
541 struct sh_eth_dev *eth = dev->priv;
543 return sh_eth_send_common(eth, packet, len);
546 static int sh_eth_recv_common(struct sh_eth_dev *eth)
548 int port = eth->port, len = 0;
549 struct sh_eth_info *port_info = ð->port_info[port];
550 uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
552 len = sh_eth_recv_start(eth);
554 invalidate_cache(packet, len);
555 net_process_received_packet(packet, len);
556 sh_eth_recv_finish(eth);
560 /* Restart the receiver if disabled */
561 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
562 sh_eth_write(port_info, EDRRR_R, EDRRR);
567 static int sh_eth_recv_legacy(struct eth_device *dev)
569 struct sh_eth_dev *eth = dev->priv;
571 return sh_eth_recv_common(eth);
574 static int sh_eth_init_legacy(struct eth_device *dev, bd_t *bd)
576 struct sh_eth_dev *eth = dev->priv;
579 ret = sh_eth_init_common(eth, dev->enetaddr);
583 ret = sh_eth_phy_config_legacy(eth);
585 printf(SHETHER_NAME ": phy config timeout\n");
589 ret = sh_eth_start_common(eth);
596 sh_eth_tx_desc_free(eth);
597 sh_eth_rx_desc_free(eth);
601 void sh_eth_halt_legacy(struct eth_device *dev)
603 struct sh_eth_dev *eth = dev->priv;
608 int sh_eth_initialize(bd_t *bd)
611 struct sh_eth_dev *eth = NULL;
612 struct eth_device *dev = NULL;
613 struct mii_dev *mdiodev;
615 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
617 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
622 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
624 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
628 memset(dev, 0, sizeof(struct eth_device));
629 memset(eth, 0, sizeof(struct sh_eth_dev));
631 eth->port = CONFIG_SH_ETHER_USE_PORT;
632 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
633 eth->port_info[eth->port].iobase =
634 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
636 dev->priv = (void *)eth;
638 dev->init = sh_eth_init_legacy;
639 dev->halt = sh_eth_halt_legacy;
640 dev->send = sh_eth_send_legacy;
641 dev->recv = sh_eth_recv_legacy;
642 eth->port_info[eth->port].dev = dev;
644 strcpy(dev->name, SHETHER_NAME);
646 /* Register Device to EtherNet subsystem */
649 bb_miiphy_buses[0].priv = eth;
650 mdiodev = mdio_alloc();
653 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
654 mdiodev->read = bb_miiphy_read;
655 mdiodev->write = bb_miiphy_write;
657 ret = mdio_register(mdiodev);
661 if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
662 puts("Please set MAC address\n");
673 printf(SHETHER_NAME ": Failed\n");
677 #else /* CONFIG_DM_ETH */
679 struct sh_ether_priv {
680 struct sh_eth_dev shdev;
683 void __iomem *iobase;
685 struct gpio_desc reset_gpio;
688 static int sh_ether_send(struct udevice *dev, void *packet, int len)
690 struct sh_ether_priv *priv = dev_get_priv(dev);
691 struct sh_eth_dev *eth = &priv->shdev;
693 return sh_eth_send_common(eth, packet, len);
696 static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
698 struct sh_ether_priv *priv = dev_get_priv(dev);
699 struct sh_eth_dev *eth = &priv->shdev;
700 struct sh_eth_info *port_info = ð->port_info[eth->port];
701 uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
704 len = sh_eth_recv_start(eth);
706 invalidate_cache(packet, len);
713 /* Restart the receiver if disabled */
714 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
715 sh_eth_write(port_info, EDRRR_R, EDRRR);
721 static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
723 struct sh_ether_priv *priv = dev_get_priv(dev);
724 struct sh_eth_dev *eth = &priv->shdev;
725 struct sh_eth_info *port_info = ð->port_info[eth->port];
727 sh_eth_recv_finish(eth);
729 /* Restart the receiver if disabled */
730 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
731 sh_eth_write(port_info, EDRRR_R, EDRRR);
736 static int sh_ether_write_hwaddr(struct udevice *dev)
738 struct sh_ether_priv *priv = dev_get_priv(dev);
739 struct sh_eth_dev *eth = &priv->shdev;
740 struct sh_eth_info *port_info = ð->port_info[eth->port];
741 struct eth_pdata *pdata = dev_get_platdata(dev);
743 sh_eth_write_hwaddr(port_info, pdata->enetaddr);
748 static int sh_eth_phy_config(struct udevice *dev)
750 struct sh_ether_priv *priv = dev_get_priv(dev);
751 struct eth_pdata *pdata = dev_get_platdata(dev);
752 struct sh_eth_dev *eth = &priv->shdev;
753 int port = eth->port, ret = 0;
754 struct sh_eth_info *port_info = ð->port_info[port];
755 struct phy_device *phydev;
756 int mask = 0xffffffff;
758 phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface);
762 phy_connect_dev(phydev, dev);
764 port_info->phydev = phydev;
770 static int sh_ether_start(struct udevice *dev)
772 struct sh_ether_priv *priv = dev_get_priv(dev);
773 struct eth_pdata *pdata = dev_get_platdata(dev);
774 struct sh_eth_dev *eth = &priv->shdev;
777 ret = clk_enable(&priv->clk);
781 ret = sh_eth_init_common(eth, pdata->enetaddr);
785 ret = sh_eth_phy_config(dev);
787 printf(SHETHER_NAME ": phy config timeout\n");
791 ret = sh_eth_start_common(eth);
798 sh_eth_tx_desc_free(eth);
799 sh_eth_rx_desc_free(eth);
801 clk_disable(&priv->clk);
805 static void sh_ether_stop(struct udevice *dev)
807 struct sh_ether_priv *priv = dev_get_priv(dev);
809 sh_eth_stop(&priv->shdev);
810 clk_disable(&priv->clk);
813 static int sh_ether_probe(struct udevice *udev)
815 struct eth_pdata *pdata = dev_get_platdata(udev);
816 struct sh_ether_priv *priv = dev_get_priv(udev);
817 struct sh_eth_dev *eth = &priv->shdev;
818 struct mii_dev *mdiodev;
819 void __iomem *iobase;
822 iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
823 priv->iobase = iobase;
825 ret = clk_get_by_index(udev, 0, &priv->clk);
829 gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
832 mdiodev = mdio_alloc();
838 mdiodev->read = bb_miiphy_read;
839 mdiodev->write = bb_miiphy_write;
840 bb_miiphy_buses[0].priv = eth;
841 snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
843 ret = mdio_register(mdiodev);
845 goto err_mdio_register;
847 priv->bus = miiphy_get_dev_by_name(udev->name);
849 eth->port = CONFIG_SH_ETHER_USE_PORT;
850 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
851 eth->port_info[eth->port].iobase =
852 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
859 unmap_physmem(priv->iobase, MAP_NOCACHE);
863 static int sh_ether_remove(struct udevice *udev)
865 struct sh_ether_priv *priv = dev_get_priv(udev);
866 struct sh_eth_dev *eth = &priv->shdev;
867 struct sh_eth_info *port_info = ð->port_info[eth->port];
869 free(port_info->phydev);
870 mdio_unregister(priv->bus);
871 mdio_free(priv->bus);
873 if (dm_gpio_is_valid(&priv->reset_gpio))
874 dm_gpio_free(udev, &priv->reset_gpio);
876 unmap_physmem(priv->iobase, MAP_NOCACHE);
881 static const struct eth_ops sh_ether_ops = {
882 .start = sh_ether_start,
883 .send = sh_ether_send,
884 .recv = sh_ether_recv,
885 .free_pkt = sh_ether_free_pkt,
886 .stop = sh_ether_stop,
887 .write_hwaddr = sh_ether_write_hwaddr,
890 int sh_ether_ofdata_to_platdata(struct udevice *dev)
892 struct eth_pdata *pdata = dev_get_platdata(dev);
893 const char *phy_mode;
897 pdata->iobase = devfdt_get_addr(dev);
898 pdata->phy_interface = -1;
899 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
902 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
903 if (pdata->phy_interface == -1) {
904 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
908 pdata->max_speed = 1000;
909 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
911 pdata->max_speed = fdt32_to_cpu(*cell);
913 sprintf(bb_miiphy_buses[0].name, dev->name);
918 static const struct udevice_id sh_ether_ids[] = {
919 { .compatible = "renesas,ether-r8a7791" },
923 U_BOOT_DRIVER(eth_sh_ether) = {
926 .of_match = sh_ether_ids,
927 .ofdata_to_platdata = sh_ether_ofdata_to_platdata,
928 .probe = sh_ether_probe,
929 .remove = sh_ether_remove,
930 .ops = &sh_ether_ops,
931 .priv_auto_alloc_size = sizeof(struct sh_ether_priv),
932 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
933 .flags = DM_FLAG_ALLOC_PRIV_DMA,
937 /******* for bb_miiphy *******/
938 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
943 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
945 struct sh_eth_dev *eth = bus->priv;
946 struct sh_eth_info *port_info = ð->port_info[eth->port];
948 sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
953 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
955 struct sh_eth_dev *eth = bus->priv;
956 struct sh_eth_info *port_info = ð->port_info[eth->port];
958 sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
963 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
965 struct sh_eth_dev *eth = bus->priv;
966 struct sh_eth_info *port_info = ð->port_info[eth->port];
969 sh_eth_write(port_info,
970 sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
972 sh_eth_write(port_info,
973 sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
978 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
980 struct sh_eth_dev *eth = bus->priv;
981 struct sh_eth_info *port_info = ð->port_info[eth->port];
983 *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
988 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
990 struct sh_eth_dev *eth = bus->priv;
991 struct sh_eth_info *port_info = ð->port_info[eth->port];
994 sh_eth_write(port_info,
995 sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
997 sh_eth_write(port_info,
998 sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
1003 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
1010 struct bb_miiphy_bus bb_miiphy_buses[] = {
1013 .init = sh_eth_bb_init,
1014 .mdio_active = sh_eth_bb_mdio_active,
1015 .mdio_tristate = sh_eth_bb_mdio_tristate,
1016 .set_mdio = sh_eth_bb_set_mdio,
1017 .get_mdio = sh_eth_bb_get_mdio,
1018 .set_mdc = sh_eth_bb_set_mdc,
1019 .delay = sh_eth_bb_delay,
1023 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);