2 * sh_eth.c - Driver for Renesas ethernet controller.
4 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
5 * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
7 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
9 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/errno.h>
23 #ifndef CONFIG_SH_ETHER_USE_PORT
24 # error "Please define CONFIG_SH_ETHER_USE_PORT"
26 #ifndef CONFIG_SH_ETHER_PHY_ADDR
27 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
30 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
31 #define flush_cache_wback(addr, len) \
32 flush_dcache_range((u32)addr, \
33 (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
35 #define flush_cache_wback(...)
38 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
39 #define invalidate_cache(addr, len) \
41 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
46 start &= ~(line_size - 1); \
47 end = ((end + line_size - 1) & ~(line_size - 1)); \
49 invalidate_dcache_range(start, end); \
52 #define invalidate_cache(...)
55 #define TIMEOUT_CNT 1000
57 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
59 int port = eth->port, ret = 0, timeout;
60 struct sh_eth_info *port_info = ð->port_info[port];
62 if (!packet || len > 0xffff) {
63 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
68 /* packet must be a 4 byte boundary */
69 if ((int)packet & 3) {
70 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
76 /* Update tx descriptor */
77 flush_cache_wback(packet, len);
78 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
79 port_info->tx_desc_cur->td1 = len << 16;
80 /* Must preserve the end of descriptor list indication */
81 if (port_info->tx_desc_cur->td0 & TD_TDLE)
82 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
84 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
86 flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
88 /* Restart the transmitter if disabled */
89 if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
90 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
92 /* Wait until packet is transmitted */
93 timeout = TIMEOUT_CNT;
95 invalidate_cache(port_info->tx_desc_cur,
96 sizeof(struct tx_desc_s));
98 } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
101 printf(SHETHER_NAME ": transmit timeout\n");
106 port_info->tx_desc_cur++;
107 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
108 port_info->tx_desc_cur = port_info->tx_desc_base;
114 static int sh_eth_recv_start(struct sh_eth_dev *eth)
116 int port = eth->port, len = 0;
117 struct sh_eth_info *port_info = ð->port_info[port];
119 /* Check if the rx descriptor is ready */
120 invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
121 if (port_info->rx_desc_cur->rd0 & RD_RACT)
124 /* Check for errors */
125 if (port_info->rx_desc_cur->rd0 & RD_RFE)
128 len = port_info->rx_desc_cur->rd1 & 0xffff;
133 static void sh_eth_recv_finish(struct sh_eth_dev *eth)
135 struct sh_eth_info *port_info = ð->port_info[eth->port];
137 /* Make current descriptor available again */
138 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
139 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
141 port_info->rx_desc_cur->rd0 = RD_RACT;
143 flush_cache_wback(port_info->rx_desc_cur,
144 sizeof(struct rx_desc_s));
146 /* Point to the next descriptor */
147 port_info->rx_desc_cur++;
148 if (port_info->rx_desc_cur >=
149 port_info->rx_desc_base + NUM_RX_DESC)
150 port_info->rx_desc_cur = port_info->rx_desc_base;
153 static int sh_eth_reset(struct sh_eth_dev *eth)
155 struct sh_eth_info *port_info = ð->port_info[eth->port];
156 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
159 /* Start e-dmac transmitter and receiver */
160 sh_eth_write(port_info, EDSR_ENALL, EDSR);
162 /* Perform a software reset and wait for it to complete */
163 sh_eth_write(port_info, EDMR_SRST, EDMR);
164 for (i = 0; i < TIMEOUT_CNT; i++) {
165 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
170 if (i == TIMEOUT_CNT) {
171 printf(SHETHER_NAME ": Software reset timeout\n");
177 sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
179 sh_eth_write(port_info,
180 sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
186 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
188 int port = eth->port, i, ret = 0;
189 u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
190 struct sh_eth_info *port_info = ð->port_info[port];
191 struct tx_desc_s *cur_tx_desc;
194 * Allocate rx descriptors. They must be aligned to size of struct
197 port_info->tx_desc_alloc =
198 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
199 if (!port_info->tx_desc_alloc) {
200 printf(SHETHER_NAME ": memalign failed\n");
205 flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
207 /* Make sure we use a P2 address (non-cacheable) */
208 port_info->tx_desc_base =
209 (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
210 port_info->tx_desc_cur = port_info->tx_desc_base;
212 /* Initialize all descriptors */
213 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
214 cur_tx_desc++, i++) {
215 cur_tx_desc->td0 = 0x00;
216 cur_tx_desc->td1 = 0x00;
217 cur_tx_desc->td2 = 0x00;
220 /* Mark the end of the descriptors */
222 cur_tx_desc->td0 |= TD_TDLE;
225 * Point the controller to the tx descriptor list. Must use physical
228 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
229 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
230 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
231 sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
232 sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
239 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
241 int port = eth->port, i, ret = 0;
242 u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
243 struct sh_eth_info *port_info = ð->port_info[port];
244 struct rx_desc_s *cur_rx_desc;
248 * Allocate rx descriptors. They must be aligned to size of struct
251 port_info->rx_desc_alloc =
252 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
253 if (!port_info->rx_desc_alloc) {
254 printf(SHETHER_NAME ": memalign failed\n");
259 flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
261 /* Make sure we use a P2 address (non-cacheable) */
262 port_info->rx_desc_base =
263 (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
265 port_info->rx_desc_cur = port_info->rx_desc_base;
268 * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
269 * aligned and in P2 area.
271 port_info->rx_buf_alloc =
272 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
273 if (!port_info->rx_buf_alloc) {
274 printf(SHETHER_NAME ": alloc failed\n");
279 port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
281 /* Initialize all descriptors */
282 for (cur_rx_desc = port_info->rx_desc_base,
283 rx_buf = port_info->rx_buf_base, i = 0;
284 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
285 cur_rx_desc->rd0 = RD_RACT;
286 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
287 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
290 /* Mark the end of the descriptors */
292 cur_rx_desc->rd0 |= RD_RDLE;
294 /* Point the controller to the rx descriptor list */
295 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
296 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
297 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
298 sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
299 sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
305 free(port_info->rx_desc_alloc);
306 port_info->rx_desc_alloc = NULL;
312 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
314 int port = eth->port;
315 struct sh_eth_info *port_info = ð->port_info[port];
317 if (port_info->tx_desc_alloc) {
318 free(port_info->tx_desc_alloc);
319 port_info->tx_desc_alloc = NULL;
323 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
325 int port = eth->port;
326 struct sh_eth_info *port_info = ð->port_info[port];
328 if (port_info->rx_desc_alloc) {
329 free(port_info->rx_desc_alloc);
330 port_info->rx_desc_alloc = NULL;
333 if (port_info->rx_buf_alloc) {
334 free(port_info->rx_buf_alloc);
335 port_info->rx_buf_alloc = NULL;
339 static int sh_eth_desc_init(struct sh_eth_dev *eth)
343 ret = sh_eth_tx_desc_init(eth);
347 ret = sh_eth_rx_desc_init(eth);
353 sh_eth_tx_desc_free(eth);
359 static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
364 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
365 sh_eth_write(port_info, val, MAHR);
367 val = (mac[4] << 8) | mac[5];
368 sh_eth_write(port_info, val, MALR);
371 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
373 struct sh_eth_info *port_info = ð->port_info[eth->port];
375 /* Configure e-dmac registers */
376 sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
377 (EMDR_DESC | EDMR_EL), EDMR);
379 sh_eth_write(port_info, 0, EESIPR);
380 sh_eth_write(port_info, 0, TRSCER);
381 sh_eth_write(port_info, 0, TFTR);
382 sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
383 sh_eth_write(port_info, RMCR_RST, RMCR);
384 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
385 sh_eth_write(port_info, 0, RPADIR);
387 sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
389 /* Configure e-mac registers */
390 sh_eth_write(port_info, 0, ECSIPR);
392 /* Set Mac address */
393 sh_eth_write_hwaddr(port_info, mac);
395 sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
396 #if defined(SH_ETH_TYPE_GETHER)
397 sh_eth_write(port_info, 0, PIPR);
399 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
400 sh_eth_write(port_info, APR_AP, APR);
401 sh_eth_write(port_info, MPR_MP, MPR);
402 sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
405 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
406 sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
407 #elif defined(CONFIG_RCAR_GEN2)
408 sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
412 static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
414 struct sh_eth_info *port_info = ð->port_info[eth->port];
415 struct phy_device *phy = port_info->phydev;
419 /* Set the transfer speed */
420 if (phy->speed == 100) {
421 printf(SHETHER_NAME ": 100Base/");
422 #if defined(SH_ETH_TYPE_GETHER)
423 sh_eth_write(port_info, GECMR_100B, GECMR);
424 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
425 sh_eth_write(port_info, 1, RTRATE);
426 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2)
429 } else if (phy->speed == 10) {
430 printf(SHETHER_NAME ": 10Base/");
431 #if defined(SH_ETH_TYPE_GETHER)
432 sh_eth_write(port_info, GECMR_10B, GECMR);
433 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
434 sh_eth_write(port_info, 0, RTRATE);
437 #if defined(SH_ETH_TYPE_GETHER)
438 else if (phy->speed == 1000) {
439 printf(SHETHER_NAME ": 1000Base/");
440 sh_eth_write(port_info, GECMR_1000B, GECMR);
444 /* Check if full duplex mode is supported by the phy */
447 sh_eth_write(port_info,
448 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
452 sh_eth_write(port_info,
453 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
460 static void sh_eth_start(struct sh_eth_dev *eth)
462 struct sh_eth_info *port_info = ð->port_info[eth->port];
465 * Enable the e-dmac receiver only. The transmitter will be enabled when
466 * we have something to transmit
468 sh_eth_write(port_info, EDRRR_R, EDRRR);
471 static void sh_eth_stop(struct sh_eth_dev *eth)
473 struct sh_eth_info *port_info = ð->port_info[eth->port];
475 sh_eth_write(port_info, ~EDRRR_R, EDRRR);
478 static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
482 ret = sh_eth_reset(eth);
486 ret = sh_eth_desc_init(eth);
490 sh_eth_mac_regs_config(eth, mac);
495 static int sh_eth_start_common(struct sh_eth_dev *eth)
497 struct sh_eth_info *port_info = ð->port_info[eth->port];
500 ret = phy_startup(port_info->phydev);
502 printf(SHETHER_NAME ": phy startup failure\n");
506 ret = sh_eth_phy_regs_config(eth);
515 static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
517 int port = eth->port, ret = 0;
518 struct sh_eth_info *port_info = ð->port_info[port];
519 struct eth_device *dev = port_info->dev;
520 struct phy_device *phydev;
522 phydev = phy_connect(
523 miiphy_get_dev_by_name(dev->name),
524 port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
525 port_info->phydev = phydev;
531 static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
533 struct sh_eth_dev *eth = dev->priv;
535 return sh_eth_send_common(eth, packet, len);
538 static int sh_eth_recv_common(struct sh_eth_dev *eth)
540 int port = eth->port, len = 0;
541 struct sh_eth_info *port_info = ð->port_info[port];
542 uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
544 len = sh_eth_recv_start(eth);
546 invalidate_cache(packet, len);
547 net_process_received_packet(packet, len);
548 sh_eth_recv_finish(eth);
552 /* Restart the receiver if disabled */
553 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
554 sh_eth_write(port_info, EDRRR_R, EDRRR);
559 static int sh_eth_recv_legacy(struct eth_device *dev)
561 struct sh_eth_dev *eth = dev->priv;
563 return sh_eth_recv_common(eth);
566 static int sh_eth_init_legacy(struct eth_device *dev, bd_t *bd)
568 struct sh_eth_dev *eth = dev->priv;
571 ret = sh_eth_init_common(eth, dev->enetaddr);
575 ret = sh_eth_phy_config_legacy(eth);
577 printf(SHETHER_NAME ": phy config timeout\n");
581 ret = sh_eth_start_common(eth);
588 sh_eth_tx_desc_free(eth);
589 sh_eth_rx_desc_free(eth);
593 void sh_eth_halt_legacy(struct eth_device *dev)
595 struct sh_eth_dev *eth = dev->priv;
600 int sh_eth_initialize(bd_t *bd)
603 struct sh_eth_dev *eth = NULL;
604 struct eth_device *dev = NULL;
605 struct mii_dev *mdiodev;
607 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
609 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
614 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
616 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
620 memset(dev, 0, sizeof(struct eth_device));
621 memset(eth, 0, sizeof(struct sh_eth_dev));
623 eth->port = CONFIG_SH_ETHER_USE_PORT;
624 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
625 eth->port_info[eth->port].iobase =
626 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
628 dev->priv = (void *)eth;
630 dev->init = sh_eth_init_legacy;
631 dev->halt = sh_eth_halt_legacy;
632 dev->send = sh_eth_send_legacy;
633 dev->recv = sh_eth_recv_legacy;
634 eth->port_info[eth->port].dev = dev;
636 strcpy(dev->name, SHETHER_NAME);
638 /* Register Device to EtherNet subsystem */
641 bb_miiphy_buses[0].priv = eth;
642 mdiodev = mdio_alloc();
645 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
646 mdiodev->read = bb_miiphy_read;
647 mdiodev->write = bb_miiphy_write;
649 ret = mdio_register(mdiodev);
653 if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
654 puts("Please set MAC address\n");
665 printf(SHETHER_NAME ": Failed\n");
669 /******* for bb_miiphy *******/
670 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
675 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
677 struct sh_eth_dev *eth = bus->priv;
678 struct sh_eth_info *port_info = ð->port_info[eth->port];
680 sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
685 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
687 struct sh_eth_dev *eth = bus->priv;
688 struct sh_eth_info *port_info = ð->port_info[eth->port];
690 sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
695 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
697 struct sh_eth_dev *eth = bus->priv;
698 struct sh_eth_info *port_info = ð->port_info[eth->port];
701 sh_eth_write(port_info,
702 sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
704 sh_eth_write(port_info,
705 sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
710 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
712 struct sh_eth_dev *eth = bus->priv;
713 struct sh_eth_info *port_info = ð->port_info[eth->port];
715 *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
720 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
722 struct sh_eth_dev *eth = bus->priv;
723 struct sh_eth_info *port_info = ð->port_info[eth->port];
726 sh_eth_write(port_info,
727 sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
729 sh_eth_write(port_info,
730 sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
735 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
742 struct bb_miiphy_bus bb_miiphy_buses[] = {
745 .init = sh_eth_bb_init,
746 .mdio_active = sh_eth_bb_mdio_active,
747 .mdio_tristate = sh_eth_bb_mdio_tristate,
748 .set_mdio = sh_eth_bb_set_mdio,
749 .get_mdio = sh_eth_bb_get_mdio,
750 .set_mdc = sh_eth_bb_set_mdc,
751 .delay = sh_eth_bb_delay,
755 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);