git.sur5r.net Git - u-boot/blob - drivers/net/sh_eth.c

   1 /*
   2  * sh_eth.c - Driver for Renesas ethernet controller.
   3  *
   4  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
   5  * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
   6  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   7  * Copyright (C) 2013, 2014 Renesas Electronics Corporation
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <config.h>
  13 #include <common.h>
  14 #include <malloc.h>
  15 #include <net.h>
  16 #include <netdev.h>
  17 #include <miiphy.h>
  18 #include <linux/errno.h>
  19 #include <asm/io.h>
  20
  21 #include "sh_eth.h"
  22
  23 #ifndef CONFIG_SH_ETHER_USE_PORT
  24 # error "Please define CONFIG_SH_ETHER_USE_PORT"
  25 #endif
  26 #ifndef CONFIG_SH_ETHER_PHY_ADDR
  27 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
  28 #endif
  29
  30 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
  31 #define flush_cache_wback(addr, len)    \
  32                 flush_dcache_range((u32)addr, \
  33                 (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
  34 #else
  35 #define flush_cache_wback(...)
  36 #endif
  37
  38 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
  39 #define invalidate_cache(addr, len)             \
  40         {       \
  41                 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;    \
  42                 u32 start, end; \
  43                 \
  44                 start = (u32)addr;      \
  45                 end = start + len;      \
  46                 start &= ~(line_size - 1);      \
  47                 end = ((end + line_size - 1) & ~(line_size - 1));       \
  48                 \
  49                 invalidate_dcache_range(start, end);    \
  50         }
  51 #else
  52 #define invalidate_cache(...)
  53 #endif
  54
  55 #define TIMEOUT_CNT 1000
  56
  57 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
  58 {
  59         int port = eth->port, ret = 0, timeout;
  60         struct sh_eth_info *port_info = &eth->port_info[port];
  61
  62         if (!packet || len > 0xffff) {
  63                 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
  64                 ret = -EINVAL;
  65                 goto err;
  66         }
  67
  68         /* packet must be a 4 byte boundary */
  69         if ((int)packet & 3) {
  70                 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
  71                                 , __func__);
  72                 ret = -EFAULT;
  73                 goto err;
  74         }
  75
  76         /* Update tx descriptor */
  77         flush_cache_wback(packet, len);
  78         port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
  79         port_info->tx_desc_cur->td1 = len << 16;
  80         /* Must preserve the end of descriptor list indication */
  81         if (port_info->tx_desc_cur->td0 & TD_TDLE)
  82                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
  83         else
  84                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
  85
  86         flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
  87
  88         /* Restart the transmitter if disabled */
  89         if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
  90                 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
  91
  92         /* Wait until packet is transmitted */
  93         timeout = TIMEOUT_CNT;
  94         do {
  95                 invalidate_cache(port_info->tx_desc_cur,
  96                                  sizeof(struct tx_desc_s));
  97                 udelay(100);
  98         } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
  99
 100         if (timeout < 0) {
 101                 printf(SHETHER_NAME ": transmit timeout\n");
 102                 ret = -ETIMEDOUT;
 103                 goto err;
 104         }
 105
 106         port_info->tx_desc_cur++;
 107         if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
 108                 port_info->tx_desc_cur = port_info->tx_desc_base;
 109
 110 err:
 111         return ret;
 112 }
 113
 114 static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
 115 {
 116         struct sh_eth_dev *eth = dev->priv;
 117
 118         return sh_eth_send_common(eth, packet, len);
 119 }
 120
 121 static int sh_eth_recv_start(struct sh_eth_dev *eth)
 122 {
 123         int port = eth->port, len = 0;
 124         struct sh_eth_info *port_info = &eth->port_info[port];
 125
 126         /* Check if the rx descriptor is ready */
 127         invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
 128         if (port_info->rx_desc_cur->rd0 & RD_RACT)
 129                 return -EINVAL;
 130
 131         /* Check for errors */
 132         if (port_info->rx_desc_cur->rd0 & RD_RFE)
 133                 return -EINVAL;
 134
 135         len = port_info->rx_desc_cur->rd1 & 0xffff;
 136
 137         return len;
 138 }
 139
 140 static void sh_eth_recv_finish(struct sh_eth_dev *eth)
 141 {
 142         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 143
 144         /* Make current descriptor available again */
 145         if (port_info->rx_desc_cur->rd0 & RD_RDLE)
 146                 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
 147         else
 148                 port_info->rx_desc_cur->rd0 = RD_RACT;
 149
 150         flush_cache_wback(port_info->rx_desc_cur,
 151                           sizeof(struct rx_desc_s));
 152
 153         /* Point to the next descriptor */
 154         port_info->rx_desc_cur++;
 155         if (port_info->rx_desc_cur >=
 156             port_info->rx_desc_base + NUM_RX_DESC)
 157                 port_info->rx_desc_cur = port_info->rx_desc_base;
 158 }
 159
 160 static int sh_eth_recv_common(struct sh_eth_dev *eth)
 161 {
 162         int port = eth->port, len = 0;
 163         struct sh_eth_info *port_info = &eth->port_info[port];
 164         uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
 165
 166         len = sh_eth_recv_start(eth);
 167         if (len > 0) {
 168                 invalidate_cache(packet, len);
 169                 net_process_received_packet(packet, len);
 170                 sh_eth_recv_finish(eth);
 171         } else
 172                 len = 0;
 173
 174         /* Restart the receiver if disabled */
 175         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 176                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 177
 178         return len;
 179 }
 180
 181 static int sh_eth_recv_legacy(struct eth_device *dev)
 182 {
 183         struct sh_eth_dev *eth = dev->priv;
 184
 185         return sh_eth_recv_common(eth);
 186 }
 187
 188 static int sh_eth_reset(struct sh_eth_dev *eth)
 189 {
 190         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 191 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 192         int ret = 0, i;
 193
 194         /* Start e-dmac transmitter and receiver */
 195         sh_eth_write(port_info, EDSR_ENALL, EDSR);
 196
 197         /* Perform a software reset and wait for it to complete */
 198         sh_eth_write(port_info, EDMR_SRST, EDMR);
 199         for (i = 0; i < TIMEOUT_CNT; i++) {
 200                 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
 201                         break;
 202                 udelay(1000);
 203         }
 204
 205         if (i == TIMEOUT_CNT) {
 206                 printf(SHETHER_NAME  ": Software reset timeout\n");
 207                 ret = -EIO;
 208         }
 209
 210         return ret;
 211 #else
 212         sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
 213         udelay(3000);
 214         sh_eth_write(port_info,
 215                      sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
 216
 217         return 0;
 218 #endif
 219 }
 220
 221 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 222 {
 223         int port = eth->port, i, ret = 0;
 224         u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
 225         struct sh_eth_info *port_info = &eth->port_info[port];
 226         struct tx_desc_s *cur_tx_desc;
 227
 228         /*
 229          * Allocate rx descriptors. They must be aligned to size of struct
 230          * tx_desc_s.
 231          */
 232         port_info->tx_desc_alloc =
 233                 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
 234         if (!port_info->tx_desc_alloc) {
 235                 printf(SHETHER_NAME ": memalign failed\n");
 236                 ret = -ENOMEM;
 237                 goto err;
 238         }
 239
 240         flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
 241
 242         /* Make sure we use a P2 address (non-cacheable) */
 243         port_info->tx_desc_base =
 244                 (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
 245         port_info->tx_desc_cur = port_info->tx_desc_base;
 246
 247         /* Initialize all descriptors */
 248         for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
 249              cur_tx_desc++, i++) {
 250                 cur_tx_desc->td0 = 0x00;
 251                 cur_tx_desc->td1 = 0x00;
 252                 cur_tx_desc->td2 = 0x00;
 253         }
 254
 255         /* Mark the end of the descriptors */
 256         cur_tx_desc--;
 257         cur_tx_desc->td0 |= TD_TDLE;
 258
 259         /*
 260          * Point the controller to the tx descriptor list. Must use physical
 261          * addresses
 262          */
 263         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
 264 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 265         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
 266         sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
 267         sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
 268 #endif
 269
 270 err:
 271         return ret;
 272 }
 273
 274 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 275 {
 276         int port = eth->port, i, ret = 0;
 277         u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
 278         struct sh_eth_info *port_info = &eth->port_info[port];
 279         struct rx_desc_s *cur_rx_desc;
 280         u8 *rx_buf;
 281
 282         /*
 283          * Allocate rx descriptors. They must be aligned to size of struct
 284          * rx_desc_s.
 285          */
 286         port_info->rx_desc_alloc =
 287                 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
 288         if (!port_info->rx_desc_alloc) {
 289                 printf(SHETHER_NAME ": memalign failed\n");
 290                 ret = -ENOMEM;
 291                 goto err;
 292         }
 293
 294         flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
 295
 296         /* Make sure we use a P2 address (non-cacheable) */
 297         port_info->rx_desc_base =
 298                 (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
 299
 300         port_info->rx_desc_cur = port_info->rx_desc_base;
 301
 302         /*
 303          * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
 304          * aligned and in P2 area.
 305          */
 306         port_info->rx_buf_alloc =
 307                 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
 308         if (!port_info->rx_buf_alloc) {
 309                 printf(SHETHER_NAME ": alloc failed\n");
 310                 ret = -ENOMEM;
 311                 goto err_buf_alloc;
 312         }
 313
 314         port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
 315
 316         /* Initialize all descriptors */
 317         for (cur_rx_desc = port_info->rx_desc_base,
 318              rx_buf = port_info->rx_buf_base, i = 0;
 319              i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
 320                 cur_rx_desc->rd0 = RD_RACT;
 321                 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
 322                 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
 323         }
 324
 325         /* Mark the end of the descriptors */
 326         cur_rx_desc--;
 327         cur_rx_desc->rd0 |= RD_RDLE;
 328
 329         /* Point the controller to the rx descriptor list */
 330         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
 331 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 332         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
 333         sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
 334         sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
 335 #endif
 336
 337         return ret;
 338
 339 err_buf_alloc:
 340         free(port_info->rx_desc_alloc);
 341         port_info->rx_desc_alloc = NULL;
 342
 343 err:
 344         return ret;
 345 }
 346
 347 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
 348 {
 349         int port = eth->port;
 350         struct sh_eth_info *port_info = &eth->port_info[port];
 351
 352         if (port_info->tx_desc_alloc) {
 353                 free(port_info->tx_desc_alloc);
 354                 port_info->tx_desc_alloc = NULL;
 355         }
 356 }
 357
 358 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
 359 {
 360         int port = eth->port;
 361         struct sh_eth_info *port_info = &eth->port_info[port];
 362
 363         if (port_info->rx_desc_alloc) {
 364                 free(port_info->rx_desc_alloc);
 365                 port_info->rx_desc_alloc = NULL;
 366         }
 367
 368         if (port_info->rx_buf_alloc) {
 369                 free(port_info->rx_buf_alloc);
 370                 port_info->rx_buf_alloc = NULL;
 371         }
 372 }
 373
 374 static int sh_eth_desc_init(struct sh_eth_dev *eth)
 375 {
 376         int ret = 0;
 377
 378         ret = sh_eth_tx_desc_init(eth);
 379         if (ret)
 380                 goto err_tx_init;
 381
 382         ret = sh_eth_rx_desc_init(eth);
 383         if (ret)
 384                 goto err_rx_init;
 385
 386         return ret;
 387 err_rx_init:
 388         sh_eth_tx_desc_free(eth);
 389
 390 err_tx_init:
 391         return ret;
 392 }
 393
 394 static int sh_eth_phy_config(struct sh_eth_dev *eth)
 395 {
 396         int port = eth->port, ret = 0;
 397         struct sh_eth_info *port_info = &eth->port_info[port];
 398         struct eth_device *dev = port_info->dev;
 399         struct phy_device *phydev;
 400
 401         phydev = phy_connect(
 402                         miiphy_get_dev_by_name(dev->name),
 403                         port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
 404         port_info->phydev = phydev;
 405         phy_config(phydev);
 406
 407         return ret;
 408 }
 409
 410 static int sh_eth_config(struct sh_eth_dev *eth)
 411 {
 412         int port = eth->port, ret = 0;
 413         u32 val;
 414         struct sh_eth_info *port_info = &eth->port_info[port];
 415         struct eth_device *dev = port_info->dev;
 416         struct phy_device *phy;
 417
 418         /* Configure e-dmac registers */
 419         sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
 420                         (EMDR_DESC | EDMR_EL), EDMR);
 421
 422         sh_eth_write(port_info, 0, EESIPR);
 423         sh_eth_write(port_info, 0, TRSCER);
 424         sh_eth_write(port_info, 0, TFTR);
 425         sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
 426         sh_eth_write(port_info, RMCR_RST, RMCR);
 427 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 428         sh_eth_write(port_info, 0, RPADIR);
 429 #endif
 430         sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
 431
 432         /* Configure e-mac registers */
 433         sh_eth_write(port_info, 0, ECSIPR);
 434
 435         /* Set Mac address */
 436         val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
 437             dev->enetaddr[2] << 8 | dev->enetaddr[3];
 438         sh_eth_write(port_info, val, MAHR);
 439
 440         val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
 441         sh_eth_write(port_info, val, MALR);
 442
 443         sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
 444 #if defined(SH_ETH_TYPE_GETHER)
 445         sh_eth_write(port_info, 0, PIPR);
 446 #endif
 447 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 448         sh_eth_write(port_info, APR_AP, APR);
 449         sh_eth_write(port_info, MPR_MP, MPR);
 450         sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
 451 #endif
 452
 453 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 454         sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 455 #elif defined(CONFIG_RCAR_GEN2)
 456         sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
 457 #endif
 458         /* Configure phy */
 459         ret = sh_eth_phy_config(eth);
 460         if (ret) {
 461                 printf(SHETHER_NAME ": phy config timeout\n");
 462                 goto err_phy_cfg;
 463         }
 464         phy = port_info->phydev;
 465         ret = phy_startup(phy);
 466         if (ret) {
 467                 printf(SHETHER_NAME ": phy startup failure\n");
 468                 return ret;
 469         }
 470
 471         val = 0;
 472
 473         /* Set the transfer speed */
 474         if (phy->speed == 100) {
 475                 printf(SHETHER_NAME ": 100Base/");
 476 #if defined(SH_ETH_TYPE_GETHER)
 477                 sh_eth_write(port_info, GECMR_100B, GECMR);
 478 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 479                 sh_eth_write(port_info, 1, RTRATE);
 480 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2)
 481                 val = ECMR_RTM;
 482 #endif
 483         } else if (phy->speed == 10) {
 484                 printf(SHETHER_NAME ": 10Base/");
 485 #if defined(SH_ETH_TYPE_GETHER)
 486                 sh_eth_write(port_info, GECMR_10B, GECMR);
 487 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 488                 sh_eth_write(port_info, 0, RTRATE);
 489 #endif
 490         }
 491 #if defined(SH_ETH_TYPE_GETHER)
 492         else if (phy->speed == 1000) {
 493                 printf(SHETHER_NAME ": 1000Base/");
 494                 sh_eth_write(port_info, GECMR_1000B, GECMR);
 495         }
 496 #endif
 497
 498         /* Check if full duplex mode is supported by the phy */
 499         if (phy->duplex) {
 500                 printf("Full\n");
 501                 sh_eth_write(port_info,
 502                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
 503                              ECMR);
 504         } else {
 505                 printf("Half\n");
 506                 sh_eth_write(port_info,
 507                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
 508                              ECMR);
 509         }
 510
 511         return ret;
 512
 513 err_phy_cfg:
 514         return ret;
 515 }
 516
 517 static void sh_eth_start(struct sh_eth_dev *eth)
 518 {
 519         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 520
 521         /*
 522          * Enable the e-dmac receiver only. The transmitter will be enabled when
 523          * we have something to transmit
 524          */
 525         sh_eth_write(port_info, EDRRR_R, EDRRR);
 526 }
 527
 528 static void sh_eth_stop(struct sh_eth_dev *eth)
 529 {
 530         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 531
 532         sh_eth_write(port_info, ~EDRRR_R, EDRRR);
 533 }
 534
 535 int sh_eth_init(struct eth_device *dev, bd_t *bd)
 536 {
 537         int ret = 0;
 538         struct sh_eth_dev *eth = dev->priv;
 539
 540         ret = sh_eth_reset(eth);
 541         if (ret)
 542                 goto err;
 543
 544         ret = sh_eth_desc_init(eth);
 545         if (ret)
 546                 goto err;
 547
 548         ret = sh_eth_config(eth);
 549         if (ret)
 550                 goto err_config;
 551
 552         sh_eth_start(eth);
 553
 554         return ret;
 555
 556 err_config:
 557         sh_eth_tx_desc_free(eth);
 558         sh_eth_rx_desc_free(eth);
 559
 560 err:
 561         return ret;
 562 }
 563
 564 void sh_eth_halt(struct eth_device *dev)
 565 {
 566         struct sh_eth_dev *eth = dev->priv;
 567
 568         sh_eth_stop(eth);
 569 }
 570
 571 int sh_eth_initialize(bd_t *bd)
 572 {
 573         int ret = 0;
 574         struct sh_eth_dev *eth = NULL;
 575         struct eth_device *dev = NULL;
 576         struct mii_dev *mdiodev;
 577
 578         eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
 579         if (!eth) {
 580                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 581                 ret = -ENOMEM;
 582                 goto err;
 583         }
 584
 585         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
 586         if (!dev) {
 587                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 588                 ret = -ENOMEM;
 589                 goto err;
 590         }
 591         memset(dev, 0, sizeof(struct eth_device));
 592         memset(eth, 0, sizeof(struct sh_eth_dev));
 593
 594         eth->port = CONFIG_SH_ETHER_USE_PORT;
 595         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 596         eth->port_info[eth->port].iobase =
 597                 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
 598
 599         dev->priv = (void *)eth;
 600         dev->iobase = 0;
 601         dev->init = sh_eth_init;
 602         dev->halt = sh_eth_halt;
 603         dev->send = sh_eth_send_legacy;
 604         dev->recv = sh_eth_recv_legacy;
 605         eth->port_info[eth->port].dev = dev;
 606
 607         strcpy(dev->name, SHETHER_NAME);
 608
 609         /* Register Device to EtherNet subsystem  */
 610         eth_register(dev);
 611
 612         bb_miiphy_buses[0].priv = eth;
 613         mdiodev = mdio_alloc();
 614         if (!mdiodev)
 615                 return -ENOMEM;
 616         strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 617         mdiodev->read = bb_miiphy_read;
 618         mdiodev->write = bb_miiphy_write;
 619
 620         ret = mdio_register(mdiodev);
 621         if (ret < 0)
 622                 return ret;
 623
 624         if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
 625                 puts("Please set MAC address\n");
 626
 627         return ret;
 628
 629 err:
 630         if (dev)
 631                 free(dev);
 632
 633         if (eth)
 634                 free(eth);
 635
 636         printf(SHETHER_NAME ": Failed\n");
 637         return ret;
 638 }
 639
 640 /******* for bb_miiphy *******/
 641 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
 642 {
 643         return 0;
 644 }
 645
 646 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 647 {
 648         struct sh_eth_dev *eth = bus->priv;
 649         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 650
 651         sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
 652
 653         return 0;
 654 }
 655
 656 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 657 {
 658         struct sh_eth_dev *eth = bus->priv;
 659         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 660
 661         sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
 662
 663         return 0;
 664 }
 665
 666 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 667 {
 668         struct sh_eth_dev *eth = bus->priv;
 669         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 670
 671         if (v)
 672                 sh_eth_write(port_info,
 673                              sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
 674         else
 675                 sh_eth_write(port_info,
 676                              sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
 677
 678         return 0;
 679 }
 680
 681 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
 682 {
 683         struct sh_eth_dev *eth = bus->priv;
 684         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 685
 686         *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
 687
 688         return 0;
 689 }
 690
 691 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
 692 {
 693         struct sh_eth_dev *eth = bus->priv;
 694         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 695
 696         if (v)
 697                 sh_eth_write(port_info,
 698                              sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
 699         else
 700                 sh_eth_write(port_info,
 701                              sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
 702
 703         return 0;
 704 }
 705
 706 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
 707 {
 708         udelay(10);
 709
 710         return 0;
 711 }
 712
 713 struct bb_miiphy_bus bb_miiphy_buses[] = {
 714         {
 715                 .name           = "sh_eth",
 716                 .init           = sh_eth_bb_init,
 717                 .mdio_active    = sh_eth_bb_mdio_active,
 718                 .mdio_tristate  = sh_eth_bb_mdio_tristate,
 719                 .set_mdio       = sh_eth_bb_set_mdio,
 720                 .get_mdio       = sh_eth_bb_get_mdio,
 721                 .set_mdc        = sh_eth_bb_set_mdc,
 722                 .delay          = sh_eth_bb_delay,
 723         }
 724 };
 725
 726 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);