2 * sh_eth.h - Driver for Renesas SuperH ethernet controler.
4 * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
5 * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/types.h>
14 #define SHETHER_NAME "sh_eth"
16 #if defined(CONFIG_SH)
17 /* Malloc returns addresses in the P1 area (cacheable). However we need to
18 use area P2 (non-cacheable) */
19 #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000))
21 /* The ethernet controller needs to use physical addresses */
22 #if defined(CONFIG_SH_32BIT)
23 #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000))
25 #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
27 #elif defined(CONFIG_ARM)
30 #define ADDR_TO_PHY(addr) ((int)(addr))
31 #define ADDR_TO_P2(addr) (addr)
32 #endif /* defined(CONFIG_SH) */
34 /* base padding size is 16 */
35 #ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
36 #define CONFIG_SH_ETHER_ALIGNE_SIZE 16
39 /* Number of supported ports */
40 #define MAX_PORT_NUM 2
42 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx
43 buffers must be a multiple of 32 bytes */
44 #define MAX_BUF_SIZE (48 * 32)
46 /* The number of tx descriptors must be large enough to point to 5 or more
47 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
48 We use one descriptor per frame */
51 /* The size of the tx descriptor is determined by how much padding is used.
52 4, 20, or 52 bytes of padding can be used */
53 #define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
54 /* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
55 #define TX_DESC_SIZE (12 + TX_DESC_PADDING)
57 /* Tx descriptor. We always use 3 bytes of padding */
61 u32 td2; /* Buffer start */
62 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
65 /* There is no limitation in the number of rx descriptors */
68 /* The size of the rx descriptor is determined by how much padding is used.
69 4, 20, or 52 bytes of padding can be used */
70 #define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
71 /* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
72 #define RX_DESC_SIZE (12 + RX_DESC_PADDING)
73 /* aligned cache line size */
74 #define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
76 /* Rx descriptor. We always use 4 bytes of padding */
80 u32 rd2; /* Buffer start */
81 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
85 struct tx_desc_s *tx_desc_malloc;
86 struct tx_desc_s *tx_desc_base;
87 struct tx_desc_s *tx_desc_cur;
88 struct rx_desc_s *rx_desc_malloc;
89 struct rx_desc_s *rx_desc_base;
90 struct rx_desc_s *rx_desc_cur;
95 struct eth_device *dev;
96 struct phy_device *phydev;
101 struct sh_eth_info port_info[MAX_PORT_NUM];
104 /* from linux/drivers/net/ethernet/renesas/sh_eth.h */
106 /* E-DMAC registers */
135 /* Ether registers */
169 RMIIMR, /* R8A7790 */
175 /* This value must be written at last. */
176 SH_ETH_MAX_REGISTER_OFFSET,
179 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
233 #if defined(SH_ETH_TYPE_RZ)
234 static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
288 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
341 /* Register Address */
342 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
343 #define SH_ETH_TYPE_GETHER
344 #define BASE_IO_ADDR 0xfee00000
345 #elif defined(CONFIG_CPU_SH7757) || \
346 defined(CONFIG_CPU_SH7752) || \
347 defined(CONFIG_CPU_SH7753)
348 #if defined(CONFIG_SH_ETHER_USE_GETHER)
349 #define SH_ETH_TYPE_GETHER
350 #define BASE_IO_ADDR 0xfee00000
352 #define SH_ETH_TYPE_ETHER
353 #define BASE_IO_ADDR 0xfef00000
355 #elif defined(CONFIG_CPU_SH7724)
356 #define SH_ETH_TYPE_ETHER
357 #define BASE_IO_ADDR 0xA4600000
358 #elif defined(CONFIG_R8A7740)
359 #define SH_ETH_TYPE_GETHER
360 #define BASE_IO_ADDR 0xE9A00000
361 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
362 defined(CONFIG_R8A7794)
363 #define SH_ETH_TYPE_ETHER
364 #define BASE_IO_ADDR 0xEE700200
365 #elif defined(CONFIG_R7S72100)
366 #define SH_ETH_TYPE_RZ
367 #define BASE_IO_ADDR 0xE8203000
372 * Copy from Linux driver source code
374 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
377 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
379 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
384 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
385 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
386 EDMR_SRST = 0x03, /* Receive/Send reset */
387 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
388 EDMR_EL = 0x40, /* Litte endian */
389 #elif defined(SH_ETH_TYPE_ETHER)
391 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
392 EDMR_EL = 0x40, /* Litte endian */
398 #if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
399 # define EMDR_DESC EDMR_DL1
400 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
401 # define EMDR_DESC EDMR_DL0
402 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
407 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
411 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
420 #if defined(CONFIG_CPU_SH7757) || \
421 defined(CONFIG_CPU_SH7752) || \
422 defined(CONFIG_CPU_SH7753)
423 GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
425 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
436 TPAUSER_TPAUSE = 0x0000ffff,
437 TPAUSER_UNLIMITED = 0,
442 BCFR_RPAUSE = 0x0000ffff,
448 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
452 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
456 #if defined(SH_ETH_TYPE_ETHER)
457 EESR_TWB = 0x40000000,
459 EESR_TWB = 0xC0000000,
460 EESR_TC1 = 0x20000000,
461 EESR_TUC = 0x10000000,
462 EESR_ROC = 0x80000000,
464 EESR_TABT = 0x04000000,
465 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
466 #if defined(SH_ETH_TYPE_ETHER)
467 EESR_ADE = 0x00800000,
469 EESR_ECI = 0x00400000,
470 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
471 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
472 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
473 #if defined(SH_ETH_TYPE_ETHER)
474 EESR_CND = 0x00000800,
476 EESR_DLC = 0x00000400,
477 EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
478 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
479 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
480 EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
481 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
485 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
486 # define TX_CHECK (EESR_TC1 | EESR_FTC)
487 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
488 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
489 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
492 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
493 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
494 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
495 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
500 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
501 DMAC_M_RABT = 0x02000000,
502 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
503 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
504 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
505 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
506 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
507 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
508 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
509 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
510 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
511 DMAC_M_RINT1 = 0x00000001,
514 /* Receive descriptor bit */
516 RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
517 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
518 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
519 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
520 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
521 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
522 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
523 RD_RFS1 = 0x00000001,
525 #define RDF1ST RD_RFP1
526 #define RDFEND RD_RFP0
527 #define RD_RFP (RD_RFP1|RD_RFP0)
536 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
537 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
538 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
540 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
541 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
543 /* Transfer descriptor bit */
545 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \
546 defined(SH_ETH_TYPE_RZ)
547 TD_TACT = 0x80000000,
549 TD_TACT = 0x7fffffff,
551 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
552 TD_TFP0 = 0x10000000,
554 #define TDF1ST TD_TFP1
555 #define TDFEND TD_TFP0
556 #define TD_TFP (TD_TFP1|TD_TFP0)
559 enum RECV_RST_BIT { RMCR_RST = 0x01, };
561 enum FELIC_MODE_BIT {
562 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
563 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
564 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
566 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
567 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
568 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
569 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
570 ECMR_PRM = 0x00000001,
571 #ifdef CONFIG_CPU_SH7724
572 ECMR_RTM = 0x00000010,
573 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
574 defined(CONFIG_R8A7794)
575 ECMR_RTM = 0x00000004,
580 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
581 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
582 ECMR_RXF | ECMR_TXF | ECMR_MCT)
583 #elif defined(SH_ETH_TYPE_ETHER)
584 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
586 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
590 enum ECSR_STATUS_BIT {
591 #if defined(SH_ETH_TYPE_ETHER)
592 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
595 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
598 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
599 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
601 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
602 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
606 enum ECSIPR_STATUS_MASK_BIT {
607 #if defined(SH_ETH_TYPE_ETHER)
608 ECSIPR_BRCRXIP = 0x20,
609 ECSIPR_PSRTOIP = 0x10,
610 #elif defined(SH_ETY_TYPE_GETHER)
611 ECSIPR_PSRTOIP = 0x10,
614 ECSIPR_LCHNGIP = 0x04,
619 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
620 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
622 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
623 ECSIPR_ICDIP | ECSIPR_MPDIP)
638 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
639 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
640 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
641 DESC_I_RINT1 = 0x0001,
646 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
647 RPADIR_PADR = 0x0003f,
650 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
651 # define RPADIR_INIT (0x00)
653 # define RPADIR_INIT (RPADIR_PADS1)
658 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
661 static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth,
664 #if defined(SH_ETH_TYPE_GETHER)
665 const u16 *reg_offset = sh_eth_offset_gigabit;
666 #elif defined(SH_ETH_TYPE_ETHER)
667 const u16 *reg_offset = sh_eth_offset_fast_sh4;
668 #elif defined(SH_ETH_TYPE_RZ)
669 const u16 *reg_offset = sh_eth_offset_rz;
673 return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port;
676 static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data,
679 outl(data, sh_eth_reg_addr(eth, enum_index));
682 static inline unsigned long sh_eth_read(struct sh_eth_dev *eth,
685 return inl(sh_eth_reg_addr(eth, enum_index));