git.sur5r.net Git - u-boot/blob - drivers/net/sh_eth.h

   1 /*
   2  * sh_eth.h - Driver for Renesas SuperH ethernet controller.
   3  *
   4  * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
   5  * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
   6  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <netdev.h>
  12 #include <asm/types.h>
  13
  14 #define SHETHER_NAME "sh_eth"
  15
  16 #if defined(CONFIG_SH)
  17 /* Malloc returns addresses in the P1 area (cacheable). However we need to
  18    use area P2 (non-cacheable) */
  19 #define ADDR_TO_P2(addr)        ((((int)(addr) & ~0xe0000000) | 0xa0000000))
  20
  21 /* The ethernet controller needs to use physical addresses */
  22 #if defined(CONFIG_SH_32BIT)
  23 #define ADDR_TO_PHY(addr)       ((((int)(addr) & ~0xe0000000) | 0x40000000))
  24 #else
  25 #define ADDR_TO_PHY(addr)       ((int)(addr) & ~0xe0000000)
  26 #endif
  27 #elif defined(CONFIG_ARM)
  28 #ifndef inl
  29 #define inl     readl
  30 #define outl    writel
  31 #endif
  32 #define ADDR_TO_PHY(addr)       ((int)(addr))
  33 #define ADDR_TO_P2(addr)        (addr)
  34 #endif /* defined(CONFIG_SH) */
  35
  36 /* base padding size is 16 */
  37 #ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
  38 #define CONFIG_SH_ETHER_ALIGNE_SIZE 16
  39 #endif
  40
  41 /* Number of supported ports */
  42 #define MAX_PORT_NUM    2
  43
  44 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx
  45    buffers must be a multiple of 32 bytes */
  46 #define MAX_BUF_SIZE    (48 * 32)
  47
  48 /* The number of tx descriptors must be large enough to point to 5 or more
  49    frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
  50    We use one descriptor per frame */
  51 #define NUM_TX_DESC             8
  52
  53 /* The size of the tx descriptor is determined by how much padding is used.
  54    4, 20, or 52 bytes of padding can be used */
  55 #define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
  56
  57 /* Tx descriptor. We always use 3 bytes of padding */
  58 struct tx_desc_s {
  59         volatile u32 td0;
  60         u32 td1;
  61         u32 td2;                /* Buffer start */
  62         u8 padding[TX_DESC_PADDING];    /* aligned cache line size */
  63 };
  64
  65 /* There is no limitation in the number of rx descriptors */
  66 #define NUM_RX_DESC     8
  67
  68 /* The size of the rx descriptor is determined by how much padding is used.
  69    4, 20, or 52 bytes of padding can be used */
  70 #define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
  71 /* aligned cache line size */
  72 #define RX_BUF_ALIGNE_SIZE      (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
  73
  74 /* Rx descriptor. We always use 4 bytes of padding */
  75 struct rx_desc_s {
  76         volatile u32 rd0;
  77         volatile u32 rd1;
  78         u32 rd2;                /* Buffer start */
  79         u8 padding[TX_DESC_PADDING];    /* aligned cache line size */
  80 };
  81
  82 struct sh_eth_info {
  83         struct tx_desc_s *tx_desc_alloc;
  84         struct tx_desc_s *tx_desc_base;
  85         struct tx_desc_s *tx_desc_cur;
  86         struct rx_desc_s *rx_desc_alloc;
  87         struct rx_desc_s *rx_desc_base;
  88         struct rx_desc_s *rx_desc_cur;
  89         u8 *rx_buf_alloc;
  90         u8 *rx_buf_base;
  91         u8 mac_addr[6];
  92         u8 phy_addr;
  93         struct eth_device *dev;
  94         struct phy_device *phydev;
  95 };
  96
  97 struct sh_eth_dev {
  98         int port;
  99         struct sh_eth_info port_info[MAX_PORT_NUM];
 100 };
 101
 102 /* from linux/drivers/net/ethernet/renesas/sh_eth.h */
 103 enum {
 104         /* E-DMAC registers */
 105         EDSR = 0,
 106         EDMR,
 107         EDTRR,
 108         EDRRR,
 109         EESR,
 110         EESIPR,
 111         TDLAR,
 112         TDFAR,
 113         TDFXR,
 114         TDFFR,
 115         RDLAR,
 116         RDFAR,
 117         RDFXR,
 118         RDFFR,
 119         TRSCER,
 120         RMFCR,
 121         TFTR,
 122         FDR,
 123         RMCR,
 124         EDOCR,
 125         TFUCR,
 126         RFOCR,
 127         FCFTR,
 128         RPADIR,
 129         TRIMD,
 130         RBWAR,
 131         TBRAR,
 132
 133         /* Ether registers */
 134         ECMR,
 135         ECSR,
 136         ECSIPR,
 137         PIR,
 138         PSR,
 139         RDMLR,
 140         PIPR,
 141         RFLR,
 142         IPGR,
 143         APR,
 144         MPR,
 145         PFTCR,
 146         PFRCR,
 147         RFCR,
 148         RFCF,
 149         TPAUSER,
 150         TPAUSECR,
 151         BCFR,
 152         BCFRR,
 153         GECMR,
 154         BCULR,
 155         MAHR,
 156         MALR,
 157         TROCR,
 158         CDCR,
 159         LCCR,
 160         CNDCR,
 161         CEFCR,
 162         FRECR,
 163         TSFRCR,
 164         TLFRCR,
 165         CERCR,
 166         CEECR,
 167         RMIIMR, /* R8A7790 */
 168         MAFCR,
 169         RTRATE,
 170         CSMR,
 171         RMII_MII,
 172
 173         /* This value must be written at last. */
 174         SH_ETH_MAX_REGISTER_OFFSET,
 175 };
 176
 177 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
 178         [EDSR]  = 0x0000,
 179         [EDMR]  = 0x0400,
 180         [EDTRR] = 0x0408,
 181         [EDRRR] = 0x0410,
 182         [EESR]  = 0x0428,
 183         [EESIPR]        = 0x0430,
 184         [TDLAR] = 0x0010,
 185         [TDFAR] = 0x0014,
 186         [TDFXR] = 0x0018,
 187         [TDFFR] = 0x001c,
 188         [RDLAR] = 0x0030,
 189         [RDFAR] = 0x0034,
 190         [RDFXR] = 0x0038,
 191         [RDFFR] = 0x003c,
 192         [TRSCER]        = 0x0438,
 193         [RMFCR] = 0x0440,
 194         [TFTR]  = 0x0448,
 195         [FDR]   = 0x0450,
 196         [RMCR]  = 0x0458,
 197         [RPADIR]        = 0x0460,
 198         [FCFTR] = 0x0468,
 199         [CSMR] = 0x04E4,
 200
 201         [ECMR]  = 0x0500,
 202         [ECSR]  = 0x0510,
 203         [ECSIPR]        = 0x0518,
 204         [PIR]   = 0x0520,
 205         [PSR]   = 0x0528,
 206         [PIPR]  = 0x052c,
 207         [RFLR]  = 0x0508,
 208         [APR]   = 0x0554,
 209         [MPR]   = 0x0558,
 210         [PFTCR] = 0x055c,
 211         [PFRCR] = 0x0560,
 212         [TPAUSER]       = 0x0564,
 213         [GECMR] = 0x05b0,
 214         [BCULR] = 0x05b4,
 215         [MAHR]  = 0x05c0,
 216         [MALR]  = 0x05c8,
 217         [TROCR] = 0x0700,
 218         [CDCR]  = 0x0708,
 219         [LCCR]  = 0x0710,
 220         [CEFCR] = 0x0740,
 221         [FRECR] = 0x0748,
 222         [TSFRCR]        = 0x0750,
 223         [TLFRCR]        = 0x0758,
 224         [RFCR]  = 0x0760,
 225         [CERCR] = 0x0768,
 226         [CEECR] = 0x0770,
 227         [MAFCR] = 0x0778,
 228         [RMII_MII] =  0x0790,
 229 };
 230
 231 #if defined(SH_ETH_TYPE_RZ)
 232 static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 233         [EDSR]  = 0x0000,
 234         [EDMR]  = 0x0400,
 235         [EDTRR] = 0x0408,
 236         [EDRRR] = 0x0410,
 237         [EESR]  = 0x0428,
 238         [EESIPR]        = 0x0430,
 239         [TDLAR] = 0x0010,
 240         [TDFAR] = 0x0014,
 241         [TDFXR] = 0x0018,
 242         [TDFFR] = 0x001c,
 243         [RDLAR] = 0x0030,
 244         [RDFAR] = 0x0034,
 245         [RDFXR] = 0x0038,
 246         [RDFFR] = 0x003c,
 247         [TRSCER]        = 0x0438,
 248         [RMFCR] = 0x0440,
 249         [TFTR]  = 0x0448,
 250         [FDR]   = 0x0450,
 251         [RMCR]  = 0x0458,
 252         [RPADIR]        = 0x0460,
 253         [FCFTR] = 0x0468,
 254         [CSMR] = 0x04E4,
 255
 256         [ECMR]  = 0x0500,
 257         [ECSR]  = 0x0510,
 258         [ECSIPR]        = 0x0518,
 259         [PSR]   = 0x0528,
 260         [PIPR]  = 0x052c,
 261         [RFLR]  = 0x0508,
 262         [APR]   = 0x0554,
 263         [MPR]   = 0x0558,
 264         [PFTCR] = 0x055c,
 265         [PFRCR] = 0x0560,
 266         [TPAUSER]       = 0x0564,
 267         [GECMR] = 0x05b0,
 268         [BCULR] = 0x05b4,
 269         [MAHR]  = 0x05c0,
 270         [MALR]  = 0x05c8,
 271         [TROCR] = 0x0700,
 272         [CDCR]  = 0x0708,
 273         [LCCR]  = 0x0710,
 274         [CEFCR] = 0x0740,
 275         [FRECR] = 0x0748,
 276         [TSFRCR]        = 0x0750,
 277         [TLFRCR]        = 0x0758,
 278         [RFCR]  = 0x0760,
 279         [CERCR] = 0x0768,
 280         [CEECR] = 0x0770,
 281         [MAFCR] = 0x0778,
 282         [RMII_MII] =  0x0790,
 283 };
 284 #endif
 285
 286 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 287         [ECMR]  = 0x0100,
 288         [RFLR]  = 0x0108,
 289         [ECSR]  = 0x0110,
 290         [ECSIPR]        = 0x0118,
 291         [PIR]   = 0x0120,
 292         [PSR]   = 0x0128,
 293         [RDMLR] = 0x0140,
 294         [IPGR]  = 0x0150,
 295         [APR]   = 0x0154,
 296         [MPR]   = 0x0158,
 297         [TPAUSER]       = 0x0164,
 298         [RFCF]  = 0x0160,
 299         [TPAUSECR]      = 0x0168,
 300         [BCFRR] = 0x016c,
 301         [MAHR]  = 0x01c0,
 302         [MALR]  = 0x01c8,
 303         [TROCR] = 0x01d0,
 304         [CDCR]  = 0x01d4,
 305         [LCCR]  = 0x01d8,
 306         [CNDCR] = 0x01dc,
 307         [CEFCR] = 0x01e4,
 308         [FRECR] = 0x01e8,
 309         [TSFRCR]        = 0x01ec,
 310         [TLFRCR]        = 0x01f0,
 311         [RFCR]  = 0x01f4,
 312         [MAFCR] = 0x01f8,
 313         [RTRATE]        = 0x01fc,
 314
 315         [EDMR]  = 0x0000,
 316         [EDTRR] = 0x0008,
 317         [EDRRR] = 0x0010,
 318         [TDLAR] = 0x0018,
 319         [RDLAR] = 0x0020,
 320         [EESR]  = 0x0028,
 321         [EESIPR]        = 0x0030,
 322         [TRSCER]        = 0x0038,
 323         [RMFCR] = 0x0040,
 324         [TFTR]  = 0x0048,
 325         [FDR]   = 0x0050,
 326         [RMCR]  = 0x0058,
 327         [TFUCR] = 0x0064,
 328         [RFOCR] = 0x0068,
 329         [RMIIMR] = 0x006C,
 330         [FCFTR] = 0x0070,
 331         [RPADIR]        = 0x0078,
 332         [TRIMD] = 0x007c,
 333         [RBWAR] = 0x00c8,
 334         [RDFAR] = 0x00cc,
 335         [TBRAR] = 0x00d4,
 336         [TDFAR] = 0x00d8,
 337 };
 338
 339 /* Register Address */
 340 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 341 #define SH_ETH_TYPE_GETHER
 342 #define BASE_IO_ADDR    0xfee00000
 343 #elif defined(CONFIG_CPU_SH7757) || \
 344         defined(CONFIG_CPU_SH7752) || \
 345         defined(CONFIG_CPU_SH7753)
 346 #if defined(CONFIG_SH_ETHER_USE_GETHER)
 347 #define SH_ETH_TYPE_GETHER
 348 #define BASE_IO_ADDR    0xfee00000
 349 #else
 350 #define SH_ETH_TYPE_ETHER
 351 #define BASE_IO_ADDR    0xfef00000
 352 #endif
 353 #elif defined(CONFIG_CPU_SH7724)
 354 #define SH_ETH_TYPE_ETHER
 355 #define BASE_IO_ADDR    0xA4600000
 356 #elif defined(CONFIG_R8A7740)
 357 #define SH_ETH_TYPE_GETHER
 358 #define BASE_IO_ADDR    0xE9A00000
 359 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
 360         defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 361 #define SH_ETH_TYPE_ETHER
 362 #define BASE_IO_ADDR    0xEE700200
 363 #elif defined(CONFIG_R7S72100)
 364 #define SH_ETH_TYPE_RZ
 365 #define BASE_IO_ADDR    0xE8203000
 366 #endif
 367
 368 /*
 369  * Register's bits
 370  * Copy from Linux driver source code
 371  */
 372 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 373 /* EDSR */
 374 enum EDSR_BIT {
 375         EDSR_ENT = 0x01, EDSR_ENR = 0x02,
 376 };
 377 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
 378 #endif
 379
 380 /* EDMR */
 381 enum DMAC_M_BIT {
 382         EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
 383 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 384         EDMR_SRST       = 0x03, /* Receive/Send reset */
 385         EMDR_DESC_R     = 0x30, /* Descriptor reserve size */
 386         EDMR_EL         = 0x40, /* Litte endian */
 387 #elif defined(SH_ETH_TYPE_ETHER)
 388         EDMR_SRST       = 0x01,
 389         EMDR_DESC_R     = 0x30, /* Descriptor reserve size */
 390         EDMR_EL         = 0x40, /* Litte endian */
 391 #else
 392         EDMR_SRST = 0x01,
 393 #endif
 394 };
 395
 396 #if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
 397 # define EMDR_DESC EDMR_DL1
 398 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
 399 # define EMDR_DESC EDMR_DL0
 400 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
 401 # define EMDR_DESC 0
 402 #endif
 403
 404 /* RFLR */
 405 #define RFLR_RFL_MIN    0x05EE  /* Recv Frame length 1518 byte */
 406
 407 /* EDTRR */
 408 enum DMAC_T_BIT {
 409 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 410         EDTRR_TRNS = 0x03,
 411 #else
 412         EDTRR_TRNS = 0x01,
 413 #endif
 414 };
 415
 416 /* GECMR */
 417 enum GECMR_BIT {
 418 #if defined(CONFIG_CPU_SH7757) || \
 419         defined(CONFIG_CPU_SH7752) || \
 420         defined(CONFIG_CPU_SH7753)
 421         GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
 422 #else
 423         GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
 424 #endif
 425 };
 426
 427 /* EDRRR*/
 428 enum EDRRR_R_BIT {
 429         EDRRR_R = 0x01,
 430 };
 431
 432 /* TPAUSER */
 433 enum TPAUSER_BIT {
 434         TPAUSER_TPAUSE = 0x0000ffff,
 435         TPAUSER_UNLIMITED = 0,
 436 };
 437
 438 /* BCFR */
 439 enum BCFR_BIT {
 440         BCFR_RPAUSE = 0x0000ffff,
 441         BCFR_UNLIMITED = 0,
 442 };
 443
 444 /* PIR */
 445 enum PIR_BIT {
 446         PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
 447 };
 448
 449 /* PSR */
 450 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 451
 452 /* EESR */
 453 enum EESR_BIT {
 454 #if defined(SH_ETH_TYPE_ETHER)
 455         EESR_TWB  = 0x40000000,
 456 #else
 457         EESR_TWB  = 0xC0000000,
 458         EESR_TC1  = 0x20000000,
 459         EESR_TUC  = 0x10000000,
 460         EESR_ROC  = 0x80000000,
 461 #endif
 462         EESR_TABT = 0x04000000,
 463         EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
 464 #if defined(SH_ETH_TYPE_ETHER)
 465         EESR_ADE  = 0x00800000,
 466 #endif
 467         EESR_ECI  = 0x00400000,
 468         EESR_FTC  = 0x00200000, EESR_TDE  = 0x00100000,
 469         EESR_TFE  = 0x00080000, EESR_FRC  = 0x00040000,
 470         EESR_RDE  = 0x00020000, EESR_RFE  = 0x00010000,
 471 #if defined(SH_ETH_TYPE_ETHER)
 472         EESR_CND  = 0x00000800,
 473 #endif
 474         EESR_DLC  = 0x00000400,
 475         EESR_CD   = 0x00000200, EESR_RTO  = 0x00000100,
 476         EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
 477         EESR_CELF = 0x00000020, EESR_RRF  = 0x00000010,
 478         EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
 479         EESR_PRE  = 0x00000002, EESR_CERF = 0x00000001,
 480 };
 481
 482
 483 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 484 # define TX_CHECK (EESR_TC1 | EESR_FTC)
 485 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
 486                 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
 487 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
 488
 489 #else
 490 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
 491 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
 492                 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
 493 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
 494 #endif
 495
 496 /* EESIPR */
 497 enum DMAC_IM_BIT {
 498         DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
 499         DMAC_M_RABT = 0x02000000,
 500         DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
 501         DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
 502         DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
 503         DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
 504         DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
 505         DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
 506         DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
 507         DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
 508         DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
 509         DMAC_M_RINT1 = 0x00000001,
 510 };
 511
 512 /* Receive descriptor bit */
 513 enum RD_STS_BIT {
 514         RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
 515         RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
 516         RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
 517         RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
 518         RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
 519         RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
 520         RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
 521         RD_RFS1 = 0x00000001,
 522 };
 523 #define RDF1ST  RD_RFP1
 524 #define RDFEND  RD_RFP0
 525 #define RD_RFP  (RD_RFP1|RD_RFP0)
 526
 527 /* RDFFR*/
 528 enum RDFFR_BIT {
 529         RDFFR_RDLF = 0x01,
 530 };
 531
 532 /* FCFTR */
 533 enum FCFTR_BIT {
 534         FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
 535         FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
 536         FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
 537 };
 538 #define FIFO_F_D_RFF    (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
 539 #define FIFO_F_D_RFD    (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
 540
 541 /* Transfer descriptor bit */
 542 enum TD_STS_BIT {
 543 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \
 544         defined(SH_ETH_TYPE_RZ)
 545         TD_TACT = 0x80000000,
 546 #else
 547         TD_TACT = 0x7fffffff,
 548 #endif
 549         TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
 550         TD_TFP0 = 0x10000000,
 551 };
 552 #define TDF1ST  TD_TFP1
 553 #define TDFEND  TD_TFP0
 554 #define TD_TFP  (TD_TFP1|TD_TFP0)
 555
 556 /* RMCR */
 557 enum RECV_RST_BIT { RMCR_RST = 0x01, };
 558 /* ECMR */
 559 enum FELIC_MODE_BIT {
 560 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 561         ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
 562         ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
 563 #endif
 564         ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
 565         ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
 566         ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
 567         ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
 568         ECMR_PRM = 0x00000001,
 569 #ifdef CONFIG_CPU_SH7724
 570         ECMR_RTM = 0x00000010,
 571 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
 572         defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 573         ECMR_RTM = 0x00000004,
 574 #endif
 575
 576 };
 577
 578 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 579 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
 580                         ECMR_RXF | ECMR_TXF | ECMR_MCT)
 581 #elif defined(SH_ETH_TYPE_ETHER)
 582 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
 583 #else
 584 #define ECMR_CHG_DM     (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
 585 #endif
 586
 587 /* ECSR */
 588 enum ECSR_STATUS_BIT {
 589 #if defined(SH_ETH_TYPE_ETHER)
 590         ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
 591 #endif
 592         ECSR_LCHNG = 0x04,
 593         ECSR_MPD = 0x02, ECSR_ICD = 0x01,
 594 };
 595
 596 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 597 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
 598 #else
 599 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
 600                         ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
 601 #endif
 602
 603 /* ECSIPR */
 604 enum ECSIPR_STATUS_MASK_BIT {
 605 #if defined(SH_ETH_TYPE_ETHER)
 606         ECSIPR_BRCRXIP = 0x20,
 607         ECSIPR_PSRTOIP = 0x10,
 608 #elif defined(SH_ETY_TYPE_GETHER)
 609         ECSIPR_PSRTOIP = 0x10,
 610         ECSIPR_PHYIP = 0x08,
 611 #endif
 612         ECSIPR_LCHNGIP = 0x04,
 613         ECSIPR_MPDIP = 0x02,
 614         ECSIPR_ICDIP = 0x01,
 615 };
 616
 617 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 618 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
 619 #else
 620 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
 621                                 ECSIPR_ICDIP | ECSIPR_MPDIP)
 622 #endif
 623
 624 /* APR */
 625 enum APR_BIT {
 626         APR_AP = 0x00000004,
 627 };
 628
 629 /* MPR */
 630 enum MPR_BIT {
 631         MPR_MP = 0x00000006,
 632 };
 633
 634 /* TRSCER */
 635 enum DESC_I_BIT {
 636         DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
 637         DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
 638         DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
 639         DESC_I_RINT1 = 0x0001,
 640 };
 641
 642 /* RPADIR */
 643 enum RPADIR_BIT {
 644         RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
 645         RPADIR_PADR = 0x0003f,
 646 };
 647
 648 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 649 # define RPADIR_INIT (0x00)
 650 #else
 651 # define RPADIR_INIT (RPADIR_PADS1)
 652 #endif
 653
 654 /* FDR */
 655 enum FIFO_SIZE_BIT {
 656         FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
 657 };
 658
 659 static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth,
 660                                             int enum_index)
 661 {
 662 #if defined(SH_ETH_TYPE_GETHER)
 663         const u16 *reg_offset = sh_eth_offset_gigabit;
 664 #elif defined(SH_ETH_TYPE_ETHER)
 665         const u16 *reg_offset = sh_eth_offset_fast_sh4;
 666 #elif defined(SH_ETH_TYPE_RZ)
 667         const u16 *reg_offset = sh_eth_offset_rz;
 668 #else
 669 #error
 670 #endif
 671         return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port;
 672 }
 673
 674 static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data,
 675                                 int enum_index)
 676 {
 677         outl(data, sh_eth_reg_addr(eth, enum_index));
 678 }
 679
 680 static inline unsigned long sh_eth_read(struct sh_eth_dev *eth,
 681                                         int enum_index)
 682 {
 683         return inl(sh_eth_reg_addr(eth, enum_index));
 684 }