1 /******************************************************************************
4 * Project: GEnesis, PCI Gigabit Ethernet Adapter
5 * Version: $Revision: 1.46 $
6 * Date: $Date: 2003/01/28 09:47:45 $
7 * Purpose: Defines and Macros for Gigabit Ethernet Controller
9 ******************************************************************************/
11 /******************************************************************************
13 * (C)Copyright 1998-2003 SysKonnect GmbH.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * The information in this file is provided "AS IS" without warranty.
22 ******************************************************************************/
24 /******************************************************************************
29 * Revision 1.46 2003/01/28 09:47:45 rschmidt
30 * Added defines for copper MDI/MDIX configuration
31 * Added defines for LED Control Register
34 * Revision 1.45 2002/12/10 14:35:13 rschmidt
35 * Corrected defines for Extended PHY Specific Control
36 * Added defines for Ext. PHY Specific Ctrl 2 Reg. (Fiber specific)
38 * Revision 1.44 2002/12/09 14:58:41 rschmidt
39 * Added defines for Ext. PHY Specific Ctrl Reg. (downshift feature)
40 * Added 'GMR_FS_UN_SIZE'-Bit to Rx GMAC FIFO Flush Mask
42 * Revision 1.43 2002/12/05 10:14:45 rschmidt
43 * Added define for GMAC's Half Duplex Burst Mode
44 * Added define for Rx GMAC FIFO Flush Mask (default)
46 * Revision 1.42 2002/11/12 16:48:19 rschmidt
47 * Added defines for Cable Diagnostic Register (GPHY)
50 * Revision 1.41 2002/10/21 11:20:22 rschmidt
51 * Added bit GMR_FS_GOOD_FC to GMR_FS_ANY_ERR
54 * Revision 1.40 2002/10/14 14:54:14 rschmidt
55 * Added defines for GPHY Specific Status and GPHY Interrupt Status
56 * Added bits PHY_M_IS_AN_ERROR and PHY_M_IS_FIFO_ERROR to PHY_M_DEF_MSK
59 * Revision 1.39 2002/10/10 15:53:44 mkarl
60 * added some bit definitions for link speed status and LED's
62 * Revision 1.38 2002/08/21 16:23:46 rschmidt
63 * Added defines for PHY Specific Ctrl Reg
66 * Revision 1.37 2002/08/16 14:50:33 rschmidt
67 * Added defines for Auto-Neg. Advertisement YUKON Fiber (88E1011S only)
68 * Changed define PHY_M_DEF_MSK for GPHY IRQ Mask
71 * Revision 1.36 2002/08/12 13:21:10 rschmidt
72 * Added defines for different Broadcom PHY Ids
74 * Revision 1.35 2002/08/08 15:58:01 rschmidt
75 * Added defines for Manual LED Override register (YUKON)
78 * Revision 1.34 2002/07/31 17:23:36 rwahl
79 * Added define GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR).
81 * Revision 1.33 2002/07/23 16:03:37 rschmidt
82 * Added defines for GPHY registers
85 * Revision 1.32 2002/07/15 18:14:37 rwahl
86 * Added GMAC MIB counters definitions.
89 * Revision 1.31 2002/07/15 15:42:50 rschmidt
90 * Removed defines from PHY specific reg. which are
92 * Added defines for GMAC MIB Counters
95 * Revision 1.30 2002/06/05 08:22:12 rschmidt
96 * Changed defines for GMAC Rx Control Register and Rx Status
99 * Revision 1.29 2002/04/25 11:43:56 rschmidt
100 * Added define PHY_B_AS_PAUSE_MSK for BCom Pause Res.
101 * Added new registers and defines for YUKON (GMAC, GPHY)
102 * Added Receive Frame Status Encoding for YUKON
105 * Revision 1.28 2000/11/09 12:32:49 rassmann
108 * Revision 1.27 2000/05/17 11:00:46 malthoff
109 * Add bit for enable/disable power management in BCOM chip.
111 * Revision 1.26 1999/11/22 14:03:00 cgoos
112 * Changed license header to GPL.
114 * Revision 1.25 1999/08/12 19:19:38 malthoff
115 * Add PHY_B_AC_TX_TST bit according to BCOM A1 errata sheet.
117 * Revision 1.24 1999/07/30 11:27:21 cgoos
118 * Fixed a missing end-of-comment.
120 * Revision 1.23 1999/07/30 07:03:31 malthoff
121 * Cut some long comments.
122 * Correct the XMAC PHY ID definitions.
124 * Revision 1.22 1999/05/19 07:33:18 cgoos
125 * Changes for 1000Base-T.
127 * Revision 1.21 1999/03/25 07:46:11 malthoff
128 * Add XM_HW_CFG, XM_TS_READ, and XM_TS_LOAD registers.
130 * Revision 1.20 1999/03/12 13:36:09 malthoff
133 * Revision 1.19 1998/12/10 12:22:54 gklug
134 * fix: RX_PAGE must be in interrupt mask
136 * Revision 1.18 1998/12/10 10:36:36 gklug
137 * fix: swap of pause bits
139 * Revision 1.17 1998/11/18 13:21:45 gklug
140 * fix: Default interrupt mask
142 * Revision 1.16 1998/10/29 15:53:21 gklug
143 * fix: Default mask uses ASS (GP0) signal
145 * Revision 1.15 1998/10/28 13:52:52 malthoff
146 * Add new bits in RX_CMD register.
148 * Revision 1.14 1998/10/19 15:34:53 gklug
151 * Revision 1.13 1998/10/14 07:19:03 malthoff
152 * bug fix: Every define which describes bit 31
153 * must be declared as unsigned long 'UL'.
154 * fix bit definitions of PHY_AN_RFB and PHY_AN_PAUSE.
155 * Remove ANP defines. Rework the RFB defines.
157 * Revision 1.12 1998/10/14 06:22:44 cgoos
158 * Changed shifted constant to ULONG.
160 * Revision 1.11 1998/10/14 05:43:26 gklug
161 * add: shift pause coding
162 * fix: PAUSE bits definition
164 * Revision 1.10 1998/10/13 09:19:21 malthoff
165 * Again change XMR_FS_ANY_ERR because of new info from XaQti.
167 * Revision 1.9 1998/10/09 07:58:30 malthoff
168 * Add XMR_FS_FCS_ERR to XMR_FS_ANY_ERR.
170 * Revision 1.8 1998/10/09 07:18:17 malthoff
171 * bug fix of a bug fix: XM_PAUSE_MODE and XM_DEF_MODE
172 * are not inverted! Bug XM_DEF_MSK is inverted.
174 * Revision 1.7 1998/10/05 08:04:32 malthoff
175 * bug fix: XM_PAUSE_MODE and XM_DEF_MODE
176 * must be inverted declarations.
178 * Revision 1.6 1998/09/28 13:38:18 malthoff
179 * Add default modes and masks XM_DEF_MSK,
180 * XM_PAUSE_MODE and XM_DEF_MODE
182 * Revision 1.5 1998/09/16 14:42:04 malthoff
183 * Bug Fix: XM_GP_PORT is a 32 bit (not a 16 bit) register.
185 * Revision 1.4 1998/08/20 14:59:47 malthoff
186 * Rework this file after reading the XaQti data sheet
187 * "Differences between Rev. B2 & Rev. C XMAC II".
188 * This file is now 100% XMAC II Rev. C complained.
190 * Revision 1.3 1998/06/29 12:18:23 malthoff
191 * Correct XMR_FS_ANY_ERR definition.
193 * Revision 1.2 1998/06/29 12:10:56 malthoff
194 * Add define XMR_FS_ANY_ERR.
196 * Revision 1.1 1998/06/19 13:37:17 malthoff
200 ******************************************************************************/
207 #endif /* __cplusplus */
209 /* defines ********************************************************************/
214 * The XMAC registers are 16 or 32 bits wide.
215 * The XMACs host processor interface is set to 16 bit mode,
216 * therefore ALL registers will be addressed with 16 bit accesses.
218 * The following macros are provided to access the XMAC registers
219 * XM_IN16(), XM_OUT16, XM_IN32(), XM_OUT32(), XM_INADR(), XM_OUTADR(),
220 * XM_INHASH(), and XM_OUTHASH().
221 * The macros are defined in SkGeHw.h.
223 * Note: NA reg = Network Address e.g DA, SA etc.
226 #define XM_MMU_CMD 0x0000 /* 16 bit r/w MMU Command Register */
227 /* 0x0004: reserved */
228 #define XM_POFF 0x0008 /* 32 bit r/w Packet Offset Register */
229 #define XM_BURST 0x000c /* 32 bit r/w Burst Register for half duplex*/
230 #define XM_1L_VLAN_TAG 0x0010 /* 16 bit r/w One Level VLAN Tag ID */
231 #define XM_2L_VLAN_TAG 0x0014 /* 16 bit r/w Two Level VLAN Tag ID */
232 /* 0x0018 - 0x001e: reserved */
233 #define XM_TX_CMD 0x0020 /* 16 bit r/w Transmit Command Register */
234 #define XM_TX_RT_LIM 0x0024 /* 16 bit r/w Transmit Retry Limit Register */
235 #define XM_TX_STIME 0x0028 /* 16 bit r/w Transmit Slottime Register */
236 #define XM_TX_IPG 0x002c /* 16 bit r/w Transmit Inter Packet Gap */
237 #define XM_RX_CMD 0x0030 /* 16 bit r/w Receive Command Register */
238 #define XM_PHY_ADDR 0x0034 /* 16 bit r/w PHY Address Register */
239 #define XM_PHY_DATA 0x0038 /* 16 bit r/w PHY Data Register */
240 /* 0x003c: reserved */
241 #define XM_GP_PORT 0x0040 /* 32 bit r/w General Purpose Port Register */
242 #define XM_IMSK 0x0044 /* 16 bit r/w Interrupt Mask Register */
243 #define XM_ISRC 0x0048 /* 16 bit r/o Interrupt Status Register */
244 #define XM_HW_CFG 0x004c /* 16 bit r/w Hardware Config Register */
245 /* 0x0050 - 0x005e: reserved */
246 #define XM_TX_LO_WM 0x0060 /* 16 bit r/w Tx FIFO Low Water Mark */
247 #define XM_TX_HI_WM 0x0062 /* 16 bit r/w Tx FIFO High Water Mark */
248 #define XM_TX_THR 0x0064 /* 16 bit r/w Tx Request Threshold */
249 #define XM_HT_THR 0x0066 /* 16 bit r/w Host Request Threshold */
250 #define XM_PAUSE_DA 0x0068 /* NA reg r/w Pause Destination Address */
251 /* 0x006e: reserved */
252 #define XM_CTL_PARA 0x0070 /* 32 bit r/w Control Parameter Register */
253 #define XM_MAC_OPCODE 0x0074 /* 16 bit r/w Opcode for MAC control frames */
254 #define XM_MAC_PTIME 0x0076 /* 16 bit r/w Pause time for MAC ctrl frames*/
255 #define XM_TX_STAT 0x0078 /* 32 bit r/o Tx Status LIFO Register */
257 /* 0x0080 - 0x00fc: 16 NA reg r/w Exact Match Address Registers */
258 /* use the XM_EXM() macro to address */
259 #define XM_EXM_START 0x0080 /* r/w Start Address of the EXM Regs */
264 * returns the XMAC address offset of specified Exact Match Addr Reg
266 * para: Reg EXM register to addr (0 .. 15)
268 * usage: XM_INADDR(IoC, MAC_1, XM_EXM(i), &val[i]);
270 #define XM_EXM(Reg) (XM_EXM_START + ((Reg) << 3))
272 #define XM_SRC_CHK 0x0100 /* NA reg r/w Source Check Address Register */
273 #define XM_SA 0x0108 /* NA reg r/w Station Address Register */
274 #define XM_HSM 0x0110 /* 64 bit r/w Hash Match Address Registers */
275 #define XM_RX_LO_WM 0x0118 /* 16 bit r/w Receive Low Water Mark */
276 #define XM_RX_HI_WM 0x011a /* 16 bit r/w Receive High Water Mark */
277 #define XM_RX_THR 0x011c /* 32 bit r/w Receive Request Threshold */
278 #define XM_DEV_ID 0x0120 /* 32 bit r/o Device ID Register */
279 #define XM_MODE 0x0124 /* 32 bit r/w Mode Register */
280 #define XM_LSA 0x0128 /* NA reg r/o Last Source Register */
281 /* 0x012e: reserved */
282 #define XM_TS_READ 0x0130 /* 32 bit r/o Time Stamp Read Register */
283 #define XM_TS_LOAD 0x0134 /* 32 bit r/o Time Stamp Load Value */
284 /* 0x0138 - 0x01fe: reserved */
285 #define XM_STAT_CMD 0x0200 /* 16 bit r/w Statistics Command Register */
286 #define XM_RX_CNT_EV 0x0204 /* 32 bit r/o Rx Counter Event Register */
287 #define XM_TX_CNT_EV 0x0208 /* 32 bit r/o Tx Counter Event Register */
288 #define XM_RX_EV_MSK 0x020c /* 32 bit r/w Rx Counter Event Mask */
289 #define XM_TX_EV_MSK 0x0210 /* 32 bit r/w Tx Counter Event Mask */
290 /* 0x0204 - 0x027e: reserved */
291 #define XM_TXF_OK 0x0280 /* 32 bit r/o Frames Transmitted OK Conuter */
292 #define XM_TXO_OK_HI 0x0284 /* 32 bit r/o Octets Transmitted OK High Cnt*/
293 #define XM_TXO_OK_LO 0x0288 /* 32 bit r/o Octets Transmitted OK Low Cnt */
294 #define XM_TXF_BC_OK 0x028c /* 32 bit r/o Broadcast Frames Xmitted OK */
295 #define XM_TXF_MC_OK 0x0290 /* 32 bit r/o Multicast Frames Xmitted OK */
296 #define XM_TXF_UC_OK 0x0294 /* 32 bit r/o Unicast Frames Xmitted OK */
297 #define XM_TXF_LONG 0x0298 /* 32 bit r/o Tx Long Frame Counter */
298 #define XM_TXE_BURST 0x029c /* 32 bit r/o Tx Burst Event Counter */
299 #define XM_TXF_MPAUSE 0x02a0 /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
300 #define XM_TXF_MCTRL 0x02a4 /* 32 bit r/o Tx MAC Ctrl Frame Counter */
301 #define XM_TXF_SNG_COL 0x02a8 /* 32 bit r/o Tx Single Collision Counter */
302 #define XM_TXF_MUL_COL 0x02ac /* 32 bit r/o Tx Multiple Collision Counter */
303 #define XM_TXF_ABO_COL 0x02b0 /* 32 bit r/o Tx aborted due to Exces. Col. */
304 #define XM_TXF_LAT_COL 0x02b4 /* 32 bit r/o Tx Late Collision Counter */
305 #define XM_TXF_DEF 0x02b8 /* 32 bit r/o Tx Deferred Frame Counter */
306 #define XM_TXF_EX_DEF 0x02bc /* 32 bit r/o Tx Excessive Deferall Counter */
307 #define XM_TXE_FIFO_UR 0x02c0 /* 32 bit r/o Tx FIFO Underrun Event Cnt */
308 #define XM_TXE_CS_ERR 0x02c4 /* 32 bit r/o Tx Carrier Sense Error Cnt */
309 #define XM_TXP_UTIL 0x02c8 /* 32 bit r/o Tx Utilization in % */
310 /* 0x02cc - 0x02ce: reserved */
311 #define XM_TXF_64B 0x02d0 /* 32 bit r/o 64 Byte Tx Frame Counter */
312 #define XM_TXF_127B 0x02d4 /* 32 bit r/o 65-127 Byte Tx Frame Counter */
313 #define XM_TXF_255B 0x02d8 /* 32 bit r/o 128-255 Byte Tx Frame Counter */
314 #define XM_TXF_511B 0x02dc /* 32 bit r/o 256-511 Byte Tx Frame Counter */
315 #define XM_TXF_1023B 0x02e0 /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
316 #define XM_TXF_MAX_SZ 0x02e4 /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
317 /* 0x02e8 - 0x02fe: reserved */
318 #define XM_RXF_OK 0x0300 /* 32 bit r/o Frames Received OK */
319 #define XM_RXO_OK_HI 0x0304 /* 32 bit r/o Octets Received OK High Cnt */
320 #define XM_RXO_OK_LO 0x0308 /* 32 bit r/o Octets Received OK Low Counter*/
321 #define XM_RXF_BC_OK 0x030c /* 32 bit r/o Broadcast Frames Received OK */
322 #define XM_RXF_MC_OK 0x0310 /* 32 bit r/o Multicast Frames Received OK */
323 #define XM_RXF_UC_OK 0x0314 /* 32 bit r/o Unicast Frames Received OK */
324 #define XM_RXF_MPAUSE 0x0318 /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
325 #define XM_RXF_MCTRL 0x031c /* 32 bit r/o Rx MAC Ctrl Frame Counter */
326 #define XM_RXF_INV_MP 0x0320 /* 32 bit r/o Rx invalid Pause Frame Cnt */
327 #define XM_RXF_INV_MOC 0x0324 /* 32 bit r/o Rx Frames with inv. MAC Opcode*/
328 #define XM_RXE_BURST 0x0328 /* 32 bit r/o Rx Burst Event Counter */
329 #define XM_RXE_FMISS 0x032c /* 32 bit r/o Rx Missed Frames Event Cnt */
330 #define XM_RXF_FRA_ERR 0x0330 /* 32 bit r/o Rx Framing Error Counter */
331 #define XM_RXE_FIFO_OV 0x0334 /* 32 bit r/o Rx FIFO overflow Event Cnt */
332 #define XM_RXF_JAB_PKT 0x0338 /* 32 bit r/o Rx Jabber Packet Frame Cnt */
333 #define XM_RXE_CAR_ERR 0x033c /* 32 bit r/o Rx Carrier Event Error Cnt */
334 #define XM_RXF_LEN_ERR 0x0340 /* 32 bit r/o Rx in Range Length Error */
335 #define XM_RXE_SYM_ERR 0x0344 /* 32 bit r/o Rx Symbol Error Counter */
336 #define XM_RXE_SHT_ERR 0x0348 /* 32 bit r/o Rx Short Event Error Cnt */
337 #define XM_RXE_RUNT 0x034c /* 32 bit r/o Rx Runt Event Counter */
338 #define XM_RXF_LNG_ERR 0x0350 /* 32 bit r/o Rx Frame too Long Error Cnt */
339 #define XM_RXF_FCS_ERR 0x0354 /* 32 bit r/o Rx Frame Check Seq. Error Cnt */
340 /* 0x0358 - 0x035a: reserved */
341 #define XM_RXF_CEX_ERR 0x035c /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/
342 #define XM_RXP_UTIL 0x0360 /* 32 bit r/o Rx Utilization in % */
343 /* 0x0364 - 0x0366: reserved */
344 #define XM_RXF_64B 0x0368 /* 32 bit r/o 64 Byte Rx Frame Counter */
345 #define XM_RXF_127B 0x036c /* 32 bit r/o 65-127 Byte Rx Frame Counter */
346 #define XM_RXF_255B 0x0370 /* 32 bit r/o 128-255 Byte Rx Frame Counter */
347 #define XM_RXF_511B 0x0374 /* 32 bit r/o 256-511 Byte Rx Frame Counter */
348 #define XM_RXF_1023B 0x0378 /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
349 #define XM_RXF_MAX_SZ 0x037c /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
350 /* 0x02e8 - 0x02fe: reserved */
353 /*----------------------------------------------------------------------------*/
355 * XMAC Bit Definitions
357 * If the bit access behaviour differs from the register access behaviour
358 * (r/w, r/o) this is documented after the bit number.
359 * The following bit access behaviours are used:
364 /* XM_MMU_CMD 16 bit r/w MMU Command Register */
365 /* Bit 15..13: reserved */
366 #define XM_MMU_PHY_RDY (1<<12) /* Bit 12: PHY Read Ready */
367 #define XM_MMU_PHY_BUSY (1<<11) /* Bit 11: PHY Busy */
368 #define XM_MMU_IGN_PF (1<<10) /* Bit 10: Ignore Pause Frame */
369 #define XM_MMU_MAC_LB (1<<9) /* Bit 9: Enable MAC Loopback */
370 /* Bit 8: reserved */
371 #define XM_MMU_FRC_COL (1<<7) /* Bit 7: Force Collision */
372 #define XM_MMU_SIM_COL (1<<6) /* Bit 6: Simulate Collision */
373 #define XM_MMU_NO_PRE (1<<5) /* Bit 5: No MDIO Preamble */
374 #define XM_MMU_GMII_FD (1<<4) /* Bit 4: GMII uses Full Duplex */
375 #define XM_MMU_RAT_CTRL (1<<3) /* Bit 3: Enable Rate Control */
376 #define XM_MMU_GMII_LOOP (1<<2) /* Bit 2: PHY is in Loopback Mode */
377 #define XM_MMU_ENA_RX (1<<1) /* Bit 1: Enable Receiver */
378 #define XM_MMU_ENA_TX (1<<0) /* Bit 0: Enable Transmitter */
381 /* XM_TX_CMD 16 bit r/w Transmit Command Register */
382 /* Bit 15..7: reserved */
383 #define XM_TX_BK2BK (1<<6) /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/
384 #define XM_TX_ENC_BYP (1<<5) /* Bit 5: Set Encoder in Bypass Mode */
385 #define XM_TX_SAM_LINE (1<<4) /* Bit 4: (sc) Start utilization calculation */
386 #define XM_TX_NO_GIG_MD (1<<3) /* Bit 3: Disable Carrier Extension */
387 #define XM_TX_NO_PRE (1<<2) /* Bit 2: Disable Preamble Generation */
388 #define XM_TX_NO_CRC (1<<1) /* Bit 1: Disable CRC Generation */
389 #define XM_TX_AUTO_PAD (1<<0) /* Bit 0: Enable Automatic Padding */
392 /* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */
393 /* Bit 15..5: reserved */
394 #define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */
397 /* XM_TX_STIME 16 bit r/w Transmit Slottime Register */
398 /* Bit 15..7: reserved */
399 #define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */
402 /* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */
403 /* Bit 15..8: reserved */
404 #define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */
407 /* XM_RX_CMD 16 bit r/w Receive Command Register */
408 /* Bit 15..9: reserved */
409 #define XM_RX_LENERR_OK (1<<8) /* Bit 8 don't set Rx Err bit for */
410 /* inrange error packets */
411 #define XM_RX_BIG_PK_OK (1<<7) /* Bit 7 don't set Rx Err bit for */
413 #define XM_RX_IPG_CAP (1<<6) /* Bit 6 repl. type field with IPG */
414 #define XM_RX_TP_MD (1<<5) /* Bit 5: Enable transparent Mode */
415 #define XM_RX_STRIP_FCS (1<<4) /* Bit 4: Enable FCS Stripping */
416 #define XM_RX_SELF_RX (1<<3) /* Bit 3: Enable Rx of own packets */
417 #define XM_RX_SAM_LINE (1<<2) /* Bit 2: (sc) Start utilization calculation */
418 #define XM_RX_STRIP_PAD (1<<1) /* Bit 1: Strip pad bytes of Rx frames */
419 #define XM_RX_DIS_CEXT (1<<0) /* Bit 0: Disable carrier ext. check */
422 /* XM_PHY_ADDR 16 bit r/w PHY Address Register */
423 /* Bit 15..5: reserved */
424 #define XM_PHY_ADDR_SZ 0x1f /* Bit 4..0: PHY Address bits */
427 /* XM_GP_PORT 32 bit r/w General Purpose Port Register */
428 /* Bit 31..7: reserved */
429 #define XM_GP_ANIP (1L<<6) /* Bit 6: (ro) Auto-Neg. in progress */
430 #define XM_GP_FRC_INT (1L<<5) /* Bit 5: (sc) Force Interrupt */
431 /* Bit 4: reserved */
432 #define XM_GP_RES_MAC (1L<<3) /* Bit 3: (sc) Reset MAC and FIFOs */
433 #define XM_GP_RES_STAT (1L<<2) /* Bit 2: (sc) Reset the statistics module */
434 /* Bit 1: reserved */
435 #define XM_GP_INP_ASS (1L<<0) /* Bit 0: (ro) GP Input Pin asserted */
438 /* XM_IMSK 16 bit r/w Interrupt Mask Register */
439 /* XM_ISRC 16 bit r/o Interrupt Status Register */
440 /* Bit 15: reserved */
441 #define XM_IS_LNK_AE (1<<14) /* Bit 14: Link Asynchronous Event */
442 #define XM_IS_TX_ABORT (1<<13) /* Bit 13: Transmit Abort, late Col. etc */
443 #define XM_IS_FRC_INT (1<<12) /* Bit 12: Force INT bit set in GP */
444 #define XM_IS_INP_ASS (1<<11) /* Bit 11: Input Asserted, GP bit 0 set */
445 #define XM_IS_LIPA_RC (1<<10) /* Bit 10: Link Partner requests config */
446 #define XM_IS_RX_PAGE (1<<9) /* Bit 9: Page Received */
447 #define XM_IS_TX_PAGE (1<<8) /* Bit 8: Next Page Loaded for Transmit */
448 #define XM_IS_AND (1<<7) /* Bit 7: Auto-Negotiation Done */
449 #define XM_IS_TSC_OV (1<<6) /* Bit 6: Time Stamp Counter Overflow */
450 #define XM_IS_RXC_OV (1<<5) /* Bit 5: Rx Counter Event Overflow */
451 #define XM_IS_TXC_OV (1<<4) /* Bit 4: Tx Counter Event Overflow */
452 #define XM_IS_RXF_OV (1<<3) /* Bit 3: Receive FIFO Overflow */
453 #define XM_IS_TXF_UR (1<<2) /* Bit 2: Transmit FIFO Underrun */
454 #define XM_IS_TX_COMP (1<<1) /* Bit 1: Frame Tx Complete */
455 #define XM_IS_RX_COMP (1<<0) /* Bit 0: Frame Rx Complete */
457 #define XM_DEF_MSK (~(XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE |\
458 XM_IS_AND | XM_IS_RXC_OV | XM_IS_TXC_OV | XM_IS_TXF_UR))
461 /* XM_HW_CFG 16 bit r/w Hardware Config Register */
462 /* Bit 15.. 4: reserved */
463 #define XM_HW_GEN_EOP (1<<3) /* Bit 3: generate End of Packet pulse */
464 #define XM_HW_COM4SIG (1<<2) /* Bit 2: use Comma Detect for Sig. Det.*/
465 /* Bit 1: reserved */
466 #define XM_HW_GMII_MD (1<<0) /* Bit 0: GMII Interface selected */
469 /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
470 /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
471 /* Bit 15..10 reserved */
472 #define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */
474 /* XM_TX_THR 16 bit r/w Tx Request Threshold */
475 /* XM_HT_THR 16 bit r/w Host Request Threshold */
476 /* XM_RX_THR 16 bit r/w Rx Request Threshold */
477 /* Bit 15..11 reserved */
478 #define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */
481 /* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */
482 #define XM_ST_VALID (1UL<<31) /* Bit 31: Status Valid */
483 #define XM_ST_BYTE_CNT (0x3fffL<<17) /* Bit 30..17: Tx frame Length */
484 #define XM_ST_RETRY_CNT (0x1fL<<12) /* Bit 16..12: Retry Count */
485 #define XM_ST_EX_COL (1L<<11) /* Bit 11: Excessive Collisions */
486 #define XM_ST_EX_DEF (1L<<10) /* Bit 10: Excessive Deferral */
487 #define XM_ST_BURST (1L<<9) /* Bit 9: p. xmitted in burst md*/
488 #define XM_ST_DEFER (1L<<8) /* Bit 8: packet was defered */
489 #define XM_ST_BC (1L<<7) /* Bit 7: Broadcast packet */
490 #define XM_ST_MC (1L<<6) /* Bit 6: Multicast packet */
491 #define XM_ST_UC (1L<<5) /* Bit 5: Unicast packet */
492 #define XM_ST_TX_UR (1L<<4) /* Bit 4: FIFO Underrun occured */
493 #define XM_ST_CS_ERR (1L<<3) /* Bit 3: Carrier Sense Error */
494 #define XM_ST_LAT_COL (1L<<2) /* Bit 2: Late Collision Error */
495 #define XM_ST_MUL_COL (1L<<1) /* Bit 1: Multiple Collisions */
496 #define XM_ST_SGN_COL (1L<<0) /* Bit 0: Single Collision */
498 /* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */
499 /* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */
500 /* Bit 15..11: reserved */
501 #define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */
504 /* XM_DEV_ID 32 bit r/o Device ID Register */
505 #define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */
506 #define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */
509 /* XM_MODE 32 bit r/w Mode Register */
510 /* Bit 31..27: reserved */
511 #define XM_MD_ENA_REJ (1L<<26) /* Bit 26: Enable Frame Reject */
512 #define XM_MD_SPOE_E (1L<<25) /* Bit 25: Send Pause on Edge */
513 /* extern generated */
514 #define XM_MD_TX_REP (1L<<24) /* Bit 24: Transmit Repeater Mode */
515 #define XM_MD_SPOFF_I (1L<<23) /* Bit 23: Send Pause on FIFO full */
516 /* intern generated */
517 #define XM_MD_LE_STW (1L<<22) /* Bit 22: Rx Stat Word in Little Endian */
518 #define XM_MD_TX_CONT (1L<<21) /* Bit 21: Send Continuous */
519 #define XM_MD_TX_PAUSE (1L<<20) /* Bit 20: (sc) Send Pause Frame */
520 #define XM_MD_ATS (1L<<19) /* Bit 19: Append Time Stamp */
521 #define XM_MD_SPOL_I (1L<<18) /* Bit 18: Send Pause on Low */
522 /* intern generated */
523 #define XM_MD_SPOH_I (1L<<17) /* Bit 17: Send Pause on High */
524 /* intern generated */
525 #define XM_MD_CAP (1L<<16) /* Bit 16: Check Address Pair */
526 #define XM_MD_ENA_HASH (1L<<15) /* Bit 15: Enable Hashing */
527 #define XM_MD_CSA (1L<<14) /* Bit 14: Check Station Address */
528 #define XM_MD_CAA (1L<<13) /* Bit 13: Check Address Array */
529 #define XM_MD_RX_MCTRL (1L<<12) /* Bit 12: Rx MAC Control Frame */
530 #define XM_MD_RX_RUNT (1L<<11) /* Bit 11: Rx Runt Frames */
531 #define XM_MD_RX_IRLE (1L<<10) /* Bit 10: Rx in Range Len Err Frame */
532 #define XM_MD_RX_LONG (1L<<9) /* Bit 9: Rx Long Frame */
533 #define XM_MD_RX_CRCE (1L<<8) /* Bit 8: Rx CRC Error Frame */
534 #define XM_MD_RX_ERR (1L<<7) /* Bit 7: Rx Error Frame */
535 #define XM_MD_DIS_UC (1L<<6) /* Bit 6: Disable Rx Unicast */
536 #define XM_MD_DIS_MC (1L<<5) /* Bit 5: Disable Rx Multicast */
537 #define XM_MD_DIS_BC (1L<<4) /* Bit 4: Disable Rx Broadcast */
538 #define XM_MD_ENA_PROM (1L<<3) /* Bit 3: Enable Promiscuous */
539 #define XM_MD_ENA_BE (1L<<2) /* Bit 2: Enable Big Endian */
540 #define XM_MD_FTF (1L<<1) /* Bit 1: (sc) Flush Tx FIFO */
541 #define XM_MD_FRF (1L<<0) /* Bit 0: (sc) Flush Rx FIFO */
543 #define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
544 #define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
545 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA | XM_MD_CAA)
547 /* XM_STAT_CMD 16 bit r/w Statistics Command Register */
548 /* Bit 16..6: reserved */
549 #define XM_SC_SNP_RXC (1<<5) /* Bit 5: (sc) Snap Rx Counters */
550 #define XM_SC_SNP_TXC (1<<4) /* Bit 4: (sc) Snap Tx Counters */
551 #define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */
552 #define XM_SC_CP_TXC (1<<2) /* Bit 2: Copy Tx Counters Continuously */
553 #define XM_SC_CLR_RXC (1<<1) /* Bit 1: (sc) Clear Rx Counters */
554 #define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */
557 /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
558 /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
559 #define XMR_MAX_SZ_OV (1UL<<31) /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
560 #define XMR_1023B_OV (1L<<30) /* Bit 30: 512-1023Byte Rx Cnt Ov*/
561 #define XMR_511B_OV (1L<<29) /* Bit 29: 256-511 Byte Rx Cnt Ov*/
562 #define XMR_255B_OV (1L<<28) /* Bit 28: 128-255 Byte Rx Cnt Ov*/
563 #define XMR_127B_OV (1L<<27) /* Bit 27: 65-127 Byte Rx Cnt Ov */
564 #define XMR_64B_OV (1L<<26) /* Bit 26: 64 Byte Rx Cnt Ov */
565 #define XMR_UTIL_OV (1L<<25) /* Bit 25: Rx Util Cnt Overflow */
566 #define XMR_UTIL_UR (1L<<24) /* Bit 24: Rx Util Cnt Underrun */
567 #define XMR_CEX_ERR_OV (1L<<23) /* Bit 23: CEXT Err Cnt Ov */
568 /* Bit 22: reserved */
569 #define XMR_FCS_ERR_OV (1L<<21) /* Bit 21: Rx FCS Error Cnt Ov */
570 #define XMR_LNG_ERR_OV (1L<<20) /* Bit 20: Rx too Long Err Cnt Ov*/
571 #define XMR_RUNT_OV (1L<<19) /* Bit 19: Runt Event Cnt Ov */
572 #define XMR_SHT_ERR_OV (1L<<18) /* Bit 18: Rx Short Ev Err Cnt Ov*/
573 #define XMR_SYM_ERR_OV (1L<<17) /* Bit 17: Rx Sym Err Cnt Ov */
574 /* Bit 16: reserved */
575 #define XMR_CAR_ERR_OV (1L<<15) /* Bit 15: Rx Carr Ev Err Cnt Ov */
576 #define XMR_JAB_PKT_OV (1L<<14) /* Bit 14: Rx Jabb Packet Cnt Ov */
577 #define XMR_FIFO_OV (1L<<13) /* Bit 13: Rx FIFO Ov Ev Cnt Ov */
578 #define XMR_FRA_ERR_OV (1L<<12) /* Bit 12: Rx Framing Err Cnt Ov */
579 #define XMR_FMISS_OV (1L<<11) /* Bit 11: Rx Missed Ev Cnt Ov */
580 #define XMR_BURST (1L<<10) /* Bit 10: Rx Burst Event Cnt Ov */
581 #define XMR_INV_MOC (1L<<9) /* Bit 9: Rx with inv. MAC OC Ov*/
582 #define XMR_INV_MP (1L<<8) /* Bit 8: Rx inv Pause Frame Ov */
583 #define XMR_MCTRL_OV (1L<<7) /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
584 #define XMR_MPAUSE_OV (1L<<6) /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
585 #define XMR_UC_OK_OV (1L<<5) /* Bit 5: Rx Unicast Frame CntOv*/
586 #define XMR_MC_OK_OV (1L<<4) /* Bit 4: Rx Multicast Cnt Ov */
587 #define XMR_BC_OK_OV (1L<<3) /* Bit 3: Rx Broadcast Cnt Ov */
588 #define XMR_OK_LO_OV (1L<<2) /* Bit 2: Octets Rx OK Low CntOv*/
589 #define XMR_OK_HI_OV (1L<<1) /* Bit 1: Octets Rx OK Hi Cnt Ov*/
590 #define XMR_OK_OV (1L<<0) /* Bit 0: Frames Received Ok Ov */
592 #define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV)
594 /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
595 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
596 /* Bit 31..26: reserved */
597 #define XMT_MAX_SZ_OV (1L<<25) /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
598 #define XMT_1023B_OV (1L<<24) /* Bit 24: 512-1023Byte Tx Cnt Ov*/
599 #define XMT_511B_OV (1L<<23) /* Bit 23: 256-511 Byte Tx Cnt Ov*/
600 #define XMT_255B_OV (1L<<22) /* Bit 22: 128-255 Byte Tx Cnt Ov*/
601 #define XMT_127B_OV (1L<<21) /* Bit 21: 65-127 Byte Tx Cnt Ov */
602 #define XMT_64B_OV (1L<<20) /* Bit 20: 64 Byte Tx Cnt Ov */
603 #define XMT_UTIL_OV (1L<<19) /* Bit 19: Tx Util Cnt Overflow */
604 #define XMT_UTIL_UR (1L<<18) /* Bit 18: Tx Util Cnt Underrun */
605 #define XMT_CS_ERR_OV (1L<<17) /* Bit 17: Tx Carr Sen Err Cnt Ov*/
606 #define XMT_FIFO_UR_OV (1L<<16) /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
607 #define XMT_EX_DEF_OV (1L<<15) /* Bit 15: Tx Ex Deferall Cnt Ov */
608 #define XMT_DEF (1L<<14) /* Bit 14: Tx Deferred Cnt Ov */
609 #define XMT_LAT_COL_OV (1L<<13) /* Bit 13: Tx Late Col Cnt Ov */
610 #define XMT_ABO_COL_OV (1L<<12) /* Bit 12: Tx abo dueto Ex Col Ov*/
611 #define XMT_MUL_COL_OV (1L<<11) /* Bit 11: Tx Mult Col Cnt Ov */
612 #define XMT_SNG_COL (1L<<10) /* Bit 10: Tx Single Col Cnt Ov */
613 #define XMT_MCTRL_OV (1L<<9) /* Bit 9: Tx MAC Ctrl Counter Ov*/
614 #define XMT_MPAUSE (1L<<8) /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
615 #define XMT_BURST (1L<<7) /* Bit 7: Tx Burst Event Cnt Ov */
616 #define XMT_LONG (1L<<6) /* Bit 6: Tx Long Frame Cnt Ov */
617 #define XMT_UC_OK_OV (1L<<5) /* Bit 5: Tx Unicast Cnt Ov */
618 #define XMT_MC_OK_OV (1L<<4) /* Bit 4: Tx Multicast Cnt Ov */
619 #define XMT_BC_OK_OV (1L<<3) /* Bit 3: Tx Broadcast Cnt Ov */
620 #define XMT_OK_LO_OV (1L<<2) /* Bit 2: Octets Tx OK Low CntOv*/
621 #define XMT_OK_HI_OV (1L<<1) /* Bit 1: Octets Tx OK Hi Cnt Ov*/
622 #define XMT_OK_OV (1L<<0) /* Bit 0: Frames Tx Ok Ov */
624 #define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV)
627 * Receive Frame Status Encoding
629 #define XMR_FS_LEN (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */
630 #define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: tagged wh 2Lev VLAN ID*/
631 #define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: tagged wh 1Lev VLAN ID*/
632 #define XMR_FS_BC (1L<<15) /* Bit 15: Broadcast Frame */
633 #define XMR_FS_MC (1L<<14) /* Bit 14: Multicast Frame */
634 #define XMR_FS_UC (1L<<13) /* Bit 13: Unicast Frame */
635 /* Bit 12: reserved */
636 #define XMR_FS_BURST (1L<<11) /* Bit 11: Burst Mode */
637 #define XMR_FS_CEX_ERR (1L<<10) /* Bit 10: Carrier Ext. Error */
638 #define XMR_FS_802_3 (1L<<9) /* Bit 9: 802.3 Frame */
639 #define XMR_FS_COL_ERR (1L<<8) /* Bit 8: Collision Error */
640 #define XMR_FS_CAR_ERR (1L<<7) /* Bit 7: Carrier Event Error */
641 #define XMR_FS_LEN_ERR (1L<<6) /* Bit 6: In-Range Length Error */
642 #define XMR_FS_FRA_ERR (1L<<5) /* Bit 5: Framing Error */
643 #define XMR_FS_RUNT (1L<<4) /* Bit 4: Runt Frame */
644 #define XMR_FS_LNG_ERR (1L<<3) /* Bit 3: Giant (Jumbo) Frame */
645 #define XMR_FS_FCS_ERR (1L<<2) /* Bit 2: Frame Check Sequ Err */
646 #define XMR_FS_ERR (1L<<1) /* Bit 1: Frame Error */
647 #define XMR_FS_MCTRL (1L<<0) /* Bit 0: MAC Control Packet */
650 * XMR_FS_ERR will be set if
651 * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
652 * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
653 * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
654 * XMR_FS_ERR unless the corresponding bit in the Receive Command
657 #define XMR_FS_ANY_ERR XMR_FS_ERR
659 /*----------------------------------------------------------------------------*/
661 * XMAC-PHY Registers, indirect addressed over the XMAC
663 #define PHY_XMAC_CTRL 0x00 /* 16 bit r/w PHY Control Register */
664 #define PHY_XMAC_STAT 0x01 /* 16 bit r/w PHY Status Register */
665 #define PHY_XMAC_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
666 #define PHY_XMAC_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
667 #define PHY_XMAC_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
668 #define PHY_XMAC_AUNE_LP 0x05 /* 16 bit r/o Link Partner Abi Reg */
669 #define PHY_XMAC_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
670 #define PHY_XMAC_NEPG 0x07 /* 16 bit r/w Next Page Register */
671 #define PHY_XMAC_NEPG_LP 0x08 /* 16 bit r/o Next Page Link P Reg */
672 /* 0x09 - 0x0e: reserved */
673 #define PHY_XMAC_EXT_STAT 0x0f /* 16 bit r/o Ext Status Register */
674 #define PHY_XMAC_RES_ABI 0x10 /* 16 bit r/o PHY Resolved Ability */
676 /*----------------------------------------------------------------------------*/
678 * Broadcom-PHY Registers, indirect addressed over XMAC
680 #define PHY_BCOM_CTRL 0x00 /* 16 bit r/w PHY Control Register */
681 #define PHY_BCOM_STAT 0x01 /* 16 bit r/o PHY Status Register */
682 #define PHY_BCOM_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
683 #define PHY_BCOM_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
684 #define PHY_BCOM_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
685 #define PHY_BCOM_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
686 #define PHY_BCOM_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
687 #define PHY_BCOM_NEPG 0x07 /* 16 bit r/w Next Page Register */
688 #define PHY_BCOM_NEPG_LP 0x08 /* 16 bit r/o Next Page Link P Reg */
689 /* Broadcom-specific registers */
690 #define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */
691 #define PHY_BCOM_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
692 /* 0x0b - 0x0e: reserved */
693 #define PHY_BCOM_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
694 #define PHY_BCOM_P_EXT_CTRL 0x10 /* 16 bit r/w PHY Extended Ctrl Reg */
695 #define PHY_BCOM_P_EXT_STAT 0x11 /* 16 bit r/o PHY Extended Stat Reg */
696 #define PHY_BCOM_RE_CTR 0x12 /* 16 bit r/w Receive Error Counter */
697 #define PHY_BCOM_FC_CTR 0x13 /* 16 bit r/w False Carr Sense Cnt */
698 #define PHY_BCOM_RNO_CTR 0x14 /* 16 bit r/w Receiver NOT_OK Cnt */
699 /* 0x15 - 0x17: reserved */
700 #define PHY_BCOM_AUX_CTRL 0x18 /* 16 bit r/w Auxiliary Control Reg */
701 #define PHY_BCOM_AUX_STAT 0x19 /* 16 bit r/o Auxiliary Stat Summary */
702 #define PHY_BCOM_INT_STAT 0x1a /* 16 bit r/o Interrupt Status Reg */
703 #define PHY_BCOM_INT_MASK 0x1b /* 16 bit r/w Interrupt Mask Reg */
705 /* 0x1d - 0x1f: test registers */
707 /*----------------------------------------------------------------------------*/
709 * Marvel-PHY Registers, indirect addressed over GMAC
711 #define PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */
712 #define PHY_MARV_STAT 0x01 /* 16 bit r/o PHY Status Register */
713 #define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
714 #define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
715 #define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
716 #define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
717 #define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
718 #define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */
719 #define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link P Reg */
720 /* Marvel-specific registers */
721 #define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */
722 #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
723 /* 0x0b - 0x0e: reserved */
724 #define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
725 #define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Ctrl Reg */
726 #define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Stat Reg */
727 #define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */
728 #define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */
729 #define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */
730 #define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */
731 #define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */
733 #define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */
734 #define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */
735 #define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */
736 #define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */
737 #define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */
738 /* 0x1d - 0x1f: reserved */
740 /*----------------------------------------------------------------------------*/
742 * Level One-PHY Registers, indirect addressed over XMAC
744 #define PHY_LONE_CTRL 0x00 /* 16 bit r/w PHY Control Register */
745 #define PHY_LONE_STAT 0x01 /* 16 bit r/o PHY Status Register */
746 #define PHY_LONE_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
747 #define PHY_LONE_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
748 #define PHY_LONE_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
749 #define PHY_LONE_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
750 #define PHY_LONE_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
751 #define PHY_LONE_NEPG 0x07 /* 16 bit r/w Next Page Register */
752 #define PHY_LONE_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner*/
753 /* Level One-specific registers */
754 #define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg*/
755 #define PHY_LONE_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
756 /* 0x0b -0x0e: reserved */
757 #define PHY_LONE_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
758 #define PHY_LONE_PORT_CFG 0x10 /* 16 bit r/w Port Configuration Reg*/
759 #define PHY_LONE_Q_STAT 0x11 /* 16 bit r/o Quick Status Reg */
760 #define PHY_LONE_INT_ENAB 0x12 /* 16 bit r/w Interrupt Enable Reg */
761 #define PHY_LONE_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */
762 #define PHY_LONE_LED_CFG 0x14 /* 16 bit r/w LED Configuration Reg */
763 #define PHY_LONE_PORT_CTRL 0x15 /* 16 bit r/w Port Control Reg */
764 #define PHY_LONE_CIM 0x16 /* 16 bit r/o CIM Reg */
765 /* 0x17 -0x1c: reserved */
767 /*----------------------------------------------------------------------------*/
769 * National-PHY Registers, indirect addressed over XMAC
771 #define PHY_NAT_CTRL 0x00 /* 16 bit r/w PHY Control Register */
772 #define PHY_NAT_STAT 0x01 /* 16 bit r/w PHY Status Register */
773 #define PHY_NAT_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
774 #define PHY_NAT_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
775 #define PHY_NAT_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
776 #define PHY_NAT_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */
777 #define PHY_NAT_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
778 #define PHY_NAT_NEPG 0x07 /* 16 bit r/w Next Page Register */
779 #define PHY_NAT_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner Reg */
780 /* National-specific registers */
781 #define PHY_NAT_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
782 #define PHY_NAT_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
783 /* 0x0b -0x0e: reserved */
784 #define PHY_NAT_EXT_STAT 0x0f /* 16 bit r/o Extended Status Register */
785 #define PHY_NAT_EXT_CTRL1 0x10 /* 16 bit r/o Extended Control Reg1 */
786 #define PHY_NAT_Q_STAT1 0x11 /* 16 bit r/o Quick Status Reg1 */
787 #define PHY_NAT_10B_OP 0x12 /* 16 bit r/o 10Base-T Operations Reg */
788 #define PHY_NAT_EXT_CTRL2 0x13 /* 16 bit r/o Extended Control Reg1 */
789 #define PHY_NAT_Q_STAT2 0x14 /* 16 bit r/o Quick Status Reg2 */
790 /* 0x15 -0x18: reserved */
791 #define PHY_NAT_PHY_ADDR 0x19 /* 16 bit r/o PHY Address Register */
794 /*----------------------------------------------------------------------------*/
797 * PHY bit definitions
798 * Bits defined as PHY_X_..., PHY_B_..., PHY_L_... or PHY_N_... are
799 * Xmac/Broadcom/LevelOne/National-specific.
800 * All other are general.
803 /***** PHY_XMAC_CTRL 16 bit r/w PHY Control Register *****/
804 /***** PHY_BCOM_CTRL 16 bit r/w PHY Control Register *****/
805 /***** PHY_LONE_CTRL 16 bit r/w PHY Control Register *****/
806 #define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */
807 #define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */
808 #define PHY_CT_SPS_LSB (1<<13) /* Bit 13: (BC,L1) Speed select, lower bit */
809 #define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */
810 #define PHY_CT_PDOWN (1<<11) /* Bit 11: (BC,L1) Power Down Mode */
811 #define PHY_CT_ISOL (1<<10) /* Bit 10: (BC,L1) Isolate Mode */
812 #define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */
813 #define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */
814 #define PHY_CT_COL_TST (1<<7) /* Bit 7: (BC,L1) Collision Test enabled */
815 #define PHY_CT_SPS_MSB (1<<6) /* Bit 6: (BC,L1) Speed select, upper bit */
816 /* Bit 5..0: reserved */
818 #define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */
819 #define PHY_CT_SP100 PHY_CT_SPS_LSB /* enable speed of 100 Mbps */
820 #define PHY_CT_SP10 (0) /* enable speed of 10 Mbps */
823 /***** PHY_XMAC_STAT 16 bit r/w PHY Status Register *****/
824 /***** PHY_BCOM_STAT 16 bit r/w PHY Status Register *****/
825 /***** PHY_MARV_STAT 16 bit r/w PHY Status Register *****/
826 /***** PHY_LONE_STAT 16 bit r/w PHY Status Register *****/
827 /* Bit 15..9: reserved */
828 /* (BC/L1) 100/10 Mbps cap bits ignored*/
829 #define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */
830 /* Bit 7: reserved */
831 #define PHY_ST_PRE_SUP (1<<6) /* Bit 6: (BC/L1) preamble suppression */
832 #define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */
833 #define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occured */
834 #define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */
835 #define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */
836 #define PHY_ST_JAB_DET (1<<1) /* Bit 1: (BC/L1) Jabber Detected */
837 #define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */
840 /***** PHY_XMAC_ID1 16 bit r/o PHY ID1 Register */
841 /***** PHY_BCOM_ID1 16 bit r/o PHY ID1 Register */
842 /***** PHY_MARV_ID1 16 bit r/o PHY ID1 Register */
843 /***** PHY_LONE_ID1 16 bit r/o PHY ID1 Register */
844 #define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */
845 #define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */
846 #define PHY_I1_REV_MSK 0x0f /* Bit 3.. 0: Revision Number */
848 /* different Broadcom PHY Ids */
849 #define PHY_BCOM_ID1_A1 0x6041
850 #define PHY_BCOM_ID1_B2 0x6043
851 #define PHY_BCOM_ID1_C0 0x6044
852 #define PHY_BCOM_ID1_C5 0x6047
855 /***** PHY_XMAC_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
856 /***** PHY_XMAC_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
857 #define PHY_AN_NXT_PG (1<<15) /* Bit 15: Request Next Page */
858 #define PHY_X_AN_ACK (1<<14) /* Bit 14: (ro) Acknowledge Received */
859 #define PHY_X_AN_RFB (3<<12) /* Bit 13..12: Remote Fault Bits */
860 /* Bit 11.. 9: reserved */
861 #define PHY_X_AN_PAUSE (3<<7) /* Bit 8.. 7: Pause Bits */
862 #define PHY_X_AN_HD (1<<6) /* Bit 6: Half Duplex */
863 #define PHY_X_AN_FD (1<<5) /* Bit 5: Full Duplex */
864 /* Bit 4.. 0: reserved */
866 /***** PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
867 /***** PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
868 /* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */
869 /* Bit 14: reserved */
870 #define PHY_B_AN_RF (1<<13) /* Bit 13: Remote Fault */
871 /* Bit 12: reserved */
872 #define PHY_B_AN_ASP (1<<11) /* Bit 11: Asymmetric Pause */
873 #define PHY_B_AN_PC (1<<10) /* Bit 10: Pause Capable */
874 /* Bit 9..5: 100/10 BT cap bits ingnored */
875 #define PHY_B_AN_SEL 0x1f /* Bit 4..0: Selector Field, 00001=Ethernet*/
877 /***** PHY_LONE_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
878 /***** PHY_LONE_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
879 /* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */
880 /* Bit 14: reserved */
881 #define PHY_L_AN_RF (1<<13) /* Bit 13: Remote Fault */
882 /* Bit 12: reserved */
883 #define PHY_L_AN_ASP (1<<11) /* Bit 11: Asymmetric Pause */
884 #define PHY_L_AN_PC (1<<10) /* Bit 10: Pause Capable */
885 /* Bit 9..5: 100/10 BT cap bits ingnored */
886 #define PHY_L_AN_SEL 0x1f /* Bit 4..0: Selector Field, 00001=Ethernet*/
888 /***** PHY_NAT_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
889 /***** PHY_NAT_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
890 /* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */
891 /* Bit 14: reserved */
892 #define PHY_N_AN_RF (1<<13) /* Bit 13: Remote Fault */
893 /* Bit 12: reserved */
894 #define PHY_N_AN_100F (1<<11) /* Bit 11: 100Base-T2 FD Support */
895 #define PHY_N_AN_100H (1<<10) /* Bit 10: 100Base-T2 HD Support */
896 /* Bit 9..5: 100/10 BT cap bits ingnored */
897 #define PHY_N_AN_SEL 0x1f /* Bit 4..0: Selector Field, 00001=Ethernet*/
899 /* field type definition for PHY_x_AN_SEL */
900 #define PHY_SEL_TYPE 0x01 /* 00001 = Ethernet */
902 /***** PHY_XMAC_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/
903 /* Bit 15..4: reserved */
904 #define PHY_AN_LP_NP (1<<3) /* Bit 3: Link Partner can Next Page */
905 #define PHY_AN_LOC_NP (1<<2) /* Bit 2: Local PHY can Next Page */
906 #define PHY_AN_RX_PG (1<<1) /* Bit 1: Page Received */
907 /* Bit 0: reserved */
909 /***** PHY_BCOM_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/
910 /* Bit 15..5: reserved */
911 #define PHY_B_AN_PDF (1<<4) /* Bit 4: Parallel Detection Fault */
912 /* PHY_AN_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */
913 /* PHY_AN_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */
914 /* PHY_AN_RX_PG (see XMAC) Bit 1: Page Received */
915 #define PHY_B_AN_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Cap. */
917 /***** PHY_LONE_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/
918 #define PHY_L_AN_BP (1<<5) /* Bit 5: Base Page Indication */
919 #define PHY_L_AN_PDF (1<<4) /* Bit 4: Parallel Detection Fault */
920 /* PHY_AN_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */
921 /* PHY_AN_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */
922 /* PHY_AN_RX_PG (see XMAC) Bit 1: Page Received */
923 #define PHY_B_AN_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Cap. */
926 /***** PHY_XMAC_NEPG 16 bit r/w Next Page Register *****/
927 /***** PHY_BCOM_NEPG 16 bit r/w Next Page Register *****/
928 /***** PHY_LONE_NEPG 16 bit r/w Next Page Register *****/
929 /***** PHY_XMAC_NEPG_LP 16 bit r/o Next Page Link Partner *****/
930 /***** PHY_BCOM_NEPG_LP 16 bit r/o Next Page Link Partner *****/
931 /***** PHY_LONE_NEPG_LP 16 bit r/o Next Page Link Partner *****/
932 #define PHY_NP_MORE (1<<15) /* Bit 15: More, Next Pages to follow */
933 #define PHY_NP_ACK1 (1<<14) /* Bit 14: (ro) Ack 1, for receiving a message*/
934 #define PHY_NP_MSG_VAL (1<<13) /* Bit 13: Message Page valid */
935 #define PHY_NP_ACK2 (1<<12) /* Bit 12: Ack 2, comply with msg content*/
936 #define PHY_NP_TOG (1<<11) /* Bit 11: Toggle Bit, ensure sync */
937 #define PHY_NP_MSG 0x07ff /* Bit 10..0: Message from/to Link Partner */
942 /***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/
943 #define PHY_X_EX_FD (1<<15) /* Bit 15: Device Supports Full Duplex */
944 #define PHY_X_EX_HD (1<<14) /* Bit 14: Device Supports Half Duplex */
945 /* Bit 13..0: reserved */
947 /***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/
948 /* Bit 15..9: reserved */
949 #define PHY_X_RS_PAUSE (3<<7) /* Bit 8..7: selected Pause Mode */
950 #define PHY_X_RS_HD (1<<6) /* Bit 6: Half Duplex Mode selected */
951 #define PHY_X_RS_FD (1<<5) /* Bit 5: Full Duplex Mode selected */
952 #define PHY_X_RS_ABLMIS (1<<4) /* Bit 4: duplex or pause cap mismatch */
953 #define PHY_X_RS_PAUMIS (1<<3) /* Bit 3: pause capability missmatch */
954 /* Bit 2..0: reserved */
956 * Remote Fault Bits (PHY_X_AN_RFB) encoding
958 #define X_RFB_OK (0<<12) /* Bit 13..12 No errors, Link OK */
959 #define X_RFB_LF (1<<12) /* Bit 13..12 Link Failure */
960 #define X_RFB_OFF (2<<12) /* Bit 13..12 Offline */
961 #define X_RFB_AN_ERR (3<<12) /* Bit 13..12 Auto-Negotiation Error */
964 * Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding
966 #define PHY_X_P_NO_PAUSE (0<<7) /* Bit 8..7: no Pause Mode */
967 #define PHY_X_P_SYM_MD (1<<7) /* Bit 8..7: symmetric Pause Mode */
968 #define PHY_X_P_ASYM_MD (2<<7) /* Bit 8..7: asymmetric Pause Mode */
969 #define PHY_X_P_BOTH_MD (3<<7) /* Bit 8..7: both Pause Mode */
975 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
976 #define PHY_B_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */
977 #define PHY_B_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */
978 #define PHY_B_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */
979 #define PHY_B_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */
980 #define PHY_B_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */
981 #define PHY_B_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */
982 /* Bit 7..0: reserved */
984 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
985 #define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */
986 #define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */
987 #define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */
988 #define PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */
989 #define PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */
990 #define PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */
991 /* Bit 9..8: reserved */
992 #define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */
994 /***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/
995 #define PHY_B_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */
996 #define PHY_B_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */
997 #define PHY_B_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */
998 #define PHY_B_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */
999 /* Bit 11..0: reserved */
1001 /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
1002 #define PHY_B_PEC_MAC_PHY (1<<15) /* Bit 15: 10BIT/GMI-Interface */
1003 #define PHY_B_PEC_DIS_CROSS (1<<14) /* Bit 14: Disable MDI Crossover */
1004 #define PHY_B_PEC_TX_DIS (1<<13) /* Bit 13: Tx output Disabled */
1005 #define PHY_B_PEC_INT_DIS (1<<12) /* Bit 12: Interrupts Disabled */
1006 #define PHY_B_PEC_F_INT (1<<11) /* Bit 11: Force Interrupt */
1007 #define PHY_B_PEC_BY_45 (1<<10) /* Bit 10: Bypass 4B5B-Decoder */
1008 #define PHY_B_PEC_BY_SCR (1<<9) /* Bit 9: Bypass Scrambler */
1009 #define PHY_B_PEC_BY_MLT3 (1<<8) /* Bit 8: Bypass MLT3 Encoder */
1010 #define PHY_B_PEC_BY_RXA (1<<7) /* Bit 7: Bypass Rx Alignm. */
1011 #define PHY_B_PEC_RES_SCR (1<<6) /* Bit 6: Reset Scrambler */
1012 #define PHY_B_PEC_EN_LTR (1<<5) /* Bit 5: Ena LED Traffic Mode */
1013 #define PHY_B_PEC_LED_ON (1<<4) /* Bit 4: Force LED's on */
1014 #define PHY_B_PEC_LED_OFF (1<<3) /* Bit 3: Force LED's off */
1015 #define PHY_B_PEC_EX_IPG (1<<2) /* Bit 2: Extend Tx IPG Mode */
1016 #define PHY_B_PEC_3_LED (1<<1) /* Bit 1: Three Link LED mode */
1017 #define PHY_B_PEC_HIGH_LA (1<<0) /* Bit 0: GMII FIFO Elasticy */
1019 /***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/
1020 /* Bit 15..14: reserved */
1021 #define PHY_B_PES_CROSS_STAT (1<<13) /* Bit 13: MDI Crossover Status */
1022 #define PHY_B_PES_INT_STAT (1<<12) /* Bit 12: Interrupt Status */
1023 #define PHY_B_PES_RRS (1<<11) /* Bit 11: Remote Receiver Stat. */
1024 #define PHY_B_PES_LRS (1<<10) /* Bit 10: Local Receiver Stat. */
1025 #define PHY_B_PES_LOCKED (1<<9) /* Bit 9: Locked */
1026 #define PHY_B_PES_LS (1<<8) /* Bit 8: Link Status */
1027 #define PHY_B_PES_RF (1<<7) /* Bit 7: Remote Fault */
1028 #define PHY_B_PES_CE_ER (1<<6) /* Bit 6: Carrier Ext Error */
1029 #define PHY_B_PES_BAD_SSD (1<<5) /* Bit 5: Bad SSD */
1030 #define PHY_B_PES_BAD_ESD (1<<4) /* Bit 4: Bad ESD */
1031 #define PHY_B_PES_RX_ER (1<<3) /* Bit 3: Receive Error */
1032 #define PHY_B_PES_TX_ER (1<<2) /* Bit 2: Transmit Error */
1033 #define PHY_B_PES_LOCK_ER (1<<1) /* Bit 1: Lock Error */
1034 #define PHY_B_PES_MLT3_ER (1<<0) /* Bit 0: MLT3 code Error */
1036 /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
1037 /* Bit 15..8: reserved */
1038 #define PHY_B_FC_CTR 0xff /* Bit 7..0: False Carrier Counter */
1040 /***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
1041 #define PHY_B_RC_LOC_MSK 0xff00 /* Bit 15..8: Local Rx NOT_OK cnt */
1042 #define PHY_B_RC_REM_MSK 0x00ff /* Bit 7..0: Remote Rx NOT_OK cnt */
1044 /***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
1045 #define PHY_B_AC_L_SQE (1<<15) /* Bit 15: Low Squelch */
1046 #define PHY_B_AC_LONG_PACK (1<<14) /* Bit 14: Rx Long Packets */
1047 #define PHY_B_AC_ER_CTRL (3<<12) /* Bit 13..12: Edgerate Control */
1048 /* Bit 11: reserved */
1049 #define PHY_B_AC_TX_TST (1<<10) /* Bit 10: Tx test bit, always 1 */
1050 /* Bit 9.. 8: reserved */
1051 #define PHY_B_AC_DIS_PRF (1<<7) /* Bit 7: dis part resp filter */
1052 /* Bit 6: reserved */
1053 #define PHY_B_AC_DIS_PM (1<<5) /* Bit 5: dis power management */
1054 /* Bit 4: reserved */
1055 #define PHY_B_AC_DIAG (1<<3) /* Bit 3: Diagnostic Mode */
1056 /* Bit 2.. 0: reserved */
1058 /***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/
1059 #define PHY_B_AS_AN_C (1<<15) /* Bit 15: AutoNeg complete */
1060 #define PHY_B_AS_AN_CA (1<<14) /* Bit 14: AN Complete Ack */
1061 #define PHY_B_AS_ANACK_D (1<<13) /* Bit 13: AN Ack Detect */
1062 #define PHY_B_AS_ANAB_D (1<<12) /* Bit 12: AN Ability Detect */
1063 #define PHY_B_AS_NPW (1<<11) /* Bit 11: AN Next Page Wait */
1064 #define PHY_B_AS_AN_RES_MSK (7<<8) /* Bit 10..8: AN HDC */
1065 #define PHY_B_AS_PDF (1<<7) /* Bit 7: Parallel Detect. Fault */
1066 #define PHY_B_AS_RF (1<<6) /* Bit 6: Remote Fault */
1067 #define PHY_B_AS_ANP_R (1<<5) /* Bit 5: AN Page Received */
1068 #define PHY_B_AS_LP_ANAB (1<<4) /* Bit 4: LP AN Ability */
1069 #define PHY_B_AS_LP_NPAB (1<<3) /* Bit 3: LP Next Page Ability */
1070 #define PHY_B_AS_LS (1<<2) /* Bit 2: Link Status */
1071 #define PHY_B_AS_PRR (1<<1) /* Bit 1: Pause Resolution-Rx */
1072 #define PHY_B_AS_PRT (1<<0) /* Bit 0: Pause Resolution-Tx */
1074 #define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT)
1076 /***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1077 /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1078 /* Bit 15: reserved */
1079 #define PHY_B_IS_PSE (1<<14) /* Bit 14: Pair Swap Error */
1080 #define PHY_B_IS_MDXI_SC (1<<13) /* Bit 13: MDIX Status Change */
1081 #define PHY_B_IS_HCT (1<<12) /* Bit 12: counter above 32k */
1082 #define PHY_B_IS_LCT (1<<11) /* Bit 11: counter above 128 */
1083 #define PHY_B_IS_AN_PR (1<<10) /* Bit 10: Page Received */
1084 #define PHY_B_IS_NO_HDCL (1<<9) /* Bit 9: No HCD Link */
1085 #define PHY_B_IS_NO_HDC (1<<8) /* Bit 8: No HCD */
1086 #define PHY_B_IS_NEG_USHDC (1<<7) /* Bit 7: Negotiated Unsup. HCD */
1087 #define PHY_B_IS_SCR_S_ER (1<<6) /* Bit 6: Scrambler Sync Error */
1088 #define PHY_B_IS_RRS_CHANGE (1<<5) /* Bit 5: Remote Rx Stat Change */
1089 #define PHY_B_IS_LRS_CHANGE (1<<4) /* Bit 4: Local Rx Stat Change */
1090 #define PHY_B_IS_DUP_CHANGE (1<<3) /* Bit 3: Duplex Mode Change */
1091 #define PHY_B_IS_LSP_CHANGE (1<<2) /* Bit 2: Link Speed Change */
1092 #define PHY_B_IS_LST_CHANGE (1<<1) /* Bit 1: Link Status Changed */
1093 #define PHY_B_IS_CRC_ER (1<<0) /* Bit 0: CRC Error */
1095 #define PHY_B_DEF_MSK (~(PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1097 /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
1098 #define PHY_B_P_NO_PAUSE (0<<10) /* Bit 11..10: no Pause Mode */
1099 #define PHY_B_P_SYM_MD (1<<10) /* Bit 11..10: symmetric Pause Mode */
1100 #define PHY_B_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */
1101 #define PHY_B_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */
1104 * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
1106 #define PHY_B_RES_1000FD (7<<8) /* Bit 10..8: 1000Base-T Full Dup. */
1107 #define PHY_B_RES_1000HD (6<<8) /* Bit 10..8: 1000Base-T Half Dup. */
1108 /* others: 100/10: invalid for us */
1111 * Level One-Specific
1113 /***** PHY_LONE_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1114 #define PHY_L_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */
1115 #define PHY_L_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */
1116 #define PHY_L_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */
1117 #define PHY_L_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */
1118 #define PHY_L_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */
1119 #define PHY_L_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */
1120 /* Bit 7..0: reserved */
1122 /***** PHY_LONE_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1123 #define PHY_L_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */
1124 #define PHY_L_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */
1125 #define PHY_L_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */
1126 #define PHY_L_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status*/
1127 #define PHY_L_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */
1128 #define PHY_L_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */
1129 /* Bit 9..8: reserved */
1130 #define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */
1132 /***** PHY_LONE_EXT_STAT 16 bit r/o Extended Status Register *****/
1133 #define PHY_L_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */
1134 #define PHY_L_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */
1135 #define PHY_L_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */
1136 #define PHY_L_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */
1137 /* Bit 11..0: reserved */
1139 /***** PHY_LONE_PORT_CFG 16 bit r/w Port Configuration Reg *****/
1140 #define PHY_L_PC_REP_MODE (1<<15) /* Bit 15: Repeater Mode */
1141 /* Bit 14: reserved */
1142 #define PHY_L_PC_TX_DIS (1<<13) /* Bit 13: Tx output Disabled */
1143 #define PHY_L_PC_BY_SCR (1<<12) /* Bit 12: Bypass Scrambler */
1144 #define PHY_L_PC_BY_45 (1<<11) /* Bit 11: Bypass 4B5B-Decoder */
1145 #define PHY_L_PC_JAB_DIS (1<<10) /* Bit 10: Jabber Disabled */
1146 #define PHY_L_PC_SQE (1<<9) /* Bit 9: Enable Heartbeat */
1147 #define PHY_L_PC_TP_LOOP (1<<8) /* Bit 8: TP Loopback */
1148 #define PHY_L_PC_SSS (1<<7) /* Bit 7: Smart Speed Selection */
1149 #define PHY_L_PC_FIFO_SIZE (1<<6) /* Bit 6: FIFO Size */
1150 #define PHY_L_PC_PRE_EN (1<<5) /* Bit 5: Preamble Enable */
1151 #define PHY_L_PC_CIM (1<<4) /* Bit 4: Carrier Integrity Mon */
1152 #define PHY_L_PC_10_SER (1<<3) /* Bit 3: Use Serial Output */
1153 #define PHY_L_PC_ANISOL (1<<2) /* Bit 2: Unisolate Port */
1154 #define PHY_L_PC_TEN_BIT (1<<1) /* Bit 1: 10bit iface mode on */
1155 #define PHY_L_PC_ALTCLOCK (1<<0) /* Bit 0: (ro) ALTCLOCK Mode on */
1157 /***** PHY_LONE_Q_STAT 16 bit r/o Quick Status Reg *****/
1158 #define PHY_L_QS_D_RATE (3<<14) /* Bit 15..14: Data Rate */
1159 #define PHY_L_QS_TX_STAT (1<<13) /* Bit 13: Transmitting */
1160 #define PHY_L_QS_RX_STAT (1<<12) /* Bit 12: Receiving */
1161 #define PHY_L_QS_COL_STAT (1<<11) /* Bit 11: Collision */
1162 #define PHY_L_QS_L_STAT (1<<10) /* Bit 10: Link is up */
1163 #define PHY_L_QS_DUP_MOD (1<<9) /* Bit 9: Full/Half Duplex */
1164 #define PHY_L_QS_AN (1<<8) /* Bit 8: AutoNeg is On */
1165 #define PHY_L_QS_AN_C (1<<7) /* Bit 7: AN is Complete */
1166 #define PHY_L_QS_LLE (7<<4) /* Bit 6: Line Length Estim. */
1167 #define PHY_L_QS_PAUSE (1<<3) /* Bit 3: LP advertised Pause */
1168 #define PHY_L_QS_AS_PAUSE (1<<2) /* Bit 2: LP adv. asym. Pause */
1169 #define PHY_L_QS_ISOLATE (1<<1) /* Bit 1: CIM Isolated */
1170 #define PHY_L_QS_EVENT (1<<0) /* Bit 0: Event has occurred */
1172 /***** PHY_LONE_INT_ENAB 16 bit r/w Interrupt Enable Reg *****/
1173 /***** PHY_LONE_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1174 /* Bit 15..14: reserved */
1175 #define PHY_L_IS_AN_F (1<<13) /* Bit 13: Auto-Negotiation fault */
1176 /* Bit 12: not described */
1177 #define PHY_L_IS_CROSS (1<<11) /* Bit 11: Crossover used */
1178 #define PHY_L_IS_POL (1<<10) /* Bit 10: Polarity correct. used*/
1179 #define PHY_L_IS_SS (1<<9) /* Bit 9: Smart Speed Downgrade*/
1180 #define PHY_L_IS_CFULL (1<<8) /* Bit 8: Counter Full */
1181 #define PHY_L_IS_AN_C (1<<7) /* Bit 7: AutoNeg Complete */
1182 #define PHY_L_IS_SPEED (1<<6) /* Bit 6: Speed Changed */
1183 #define PHY_L_IS_DUP (1<<5) /* Bit 5: Duplex Changed */
1184 #define PHY_L_IS_LS (1<<4) /* Bit 4: Link Status Changed */
1185 #define PHY_L_IS_ISOL (1<<3) /* Bit 3: Isolate Occured */
1186 #define PHY_L_IS_MDINT (1<<2) /* Bit 2: (ro) STAT: MII Int Pending */
1187 #define PHY_L_IS_INTEN (1<<1) /* Bit 1: ENAB: Enable IRQs */
1188 #define PHY_L_IS_FORCE (1<<0) /* Bit 0: ENAB: Force Interrupt */
1191 #define PHY_L_DEF_MSK (PHY_L_IS_LS | PHY_L_IS_ISOL | PHY_L_IS_INTEN)
1193 /***** PHY_LONE_LED_CFG 16 bit r/w LED Configuration Reg *****/
1194 #define PHY_L_LC_LEDC (3<<14) /* Bit 15..14: Col/Blink/On/Off */
1195 #define PHY_L_LC_LEDR (3<<12) /* Bit 13..12: Rx/Blink/On/Off */
1196 #define PHY_L_LC_LEDT (3<<10) /* Bit 11..10: Tx/Blink/On/Off */
1197 #define PHY_L_LC_LEDG (3<<8) /* Bit 9..8: Giga/Blink/On/Off */
1198 #define PHY_L_LC_LEDS (3<<6) /* Bit 7..6: 10-100/Blink/On/Off */
1199 #define PHY_L_LC_LEDL (3<<4) /* Bit 5..4: Link/Blink/On/Off */
1200 #define PHY_L_LC_LEDF (3<<2) /* Bit 3..2: Duplex/Blink/On/Off */
1201 #define PHY_L_LC_PSTRECH (1<<1) /* Bit 1: Strech LED Pulses */
1202 #define PHY_L_LC_FREQ (1<<0) /* Bit 0: 30/100 ms */
1204 /***** PHY_LONE_PORT_CTRL 16 bit r/w Port Control Reg *****/
1205 #define PHY_L_PC_TX_TCLK (1<<15) /* Bit 15: Enable TX_TCLK */
1206 /* Bit 14: reserved */
1207 #define PHY_L_PC_ALT_NP (1<<13) /* Bit 14: Alternate Next Page */
1208 #define PHY_L_PC_GMII_ALT (1<<12) /* Bit 13: Alternate GMII driver */
1209 /* Bit 11: reserved */
1210 #define PHY_L_PC_TEN_CRS (1<<10) /* Bit 10: Extend CRS*/
1211 /* Bit 9..0: not described */
1213 /***** PHY_LONE_CIM 16 bit r/o CIM Reg *****/
1214 #define PHY_L_CIM_ISOL (255<<8)/* Bit 15..8: Isolate Count */
1215 #define PHY_L_CIM_FALSE_CAR (255<<0)/* Bit 7..0: False Carrier Count */
1219 * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding
1221 #define PHY_L_P_NO_PAUSE (0<<10) /* Bit 11..10: no Pause Mode */
1222 #define PHY_L_P_SYM_MD (1<<10) /* Bit 11..10: symmetric Pause Mode */
1223 #define PHY_L_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */
1224 #define PHY_L_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */
1230 /***** PHY_NAT_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1231 #define PHY_N_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */
1232 #define PHY_N_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */
1233 #define PHY_N_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */
1234 #define PHY_N_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */
1235 #define PHY_N_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */
1236 #define PHY_N_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */
1237 #define PHY_N_1000C_APC (1<<7) /* Bit 7: Asymmetric Pause Cap. */
1238 /* Bit 6..0: reserved */
1240 /***** PHY_NAT_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1241 #define PHY_N_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */
1242 #define PHY_N_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */
1243 #define PHY_N_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */
1244 #define PHY_N_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status*/
1245 #define PHY_N_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */
1246 #define PHY_N_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */
1247 #define PHY_N_1000C_LP_APC (1<<9) /* Bit 9: LP Asym. Pause Cap. */
1248 /* Bit 8: reserved */
1249 #define PHY_N_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */
1251 /***** PHY_NAT_EXT_STAT 16 bit r/o Extended Status Register *****/
1252 #define PHY_N_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */
1253 #define PHY_N_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */
1254 #define PHY_N_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */
1255 #define PHY_N_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */
1256 /* Bit 11..0: reserved */
1258 /* todo: those are still missing */
1259 /***** PHY_NAT_EXT_CTRL1 16 bit r/o Extended Control Reg1 *****/
1260 /***** PHY_NAT_Q_STAT1 16 bit r/o Quick Status Reg1 *****/
1261 /***** PHY_NAT_10B_OP 16 bit r/o 10Base-T Operations Reg *****/
1262 /***** PHY_NAT_EXT_CTRL2 16 bit r/o Extended Control Reg1 *****/
1263 /***** PHY_NAT_Q_STAT2 16 bit r/o Quick Status Reg2 *****/
1264 /***** PHY_NAT_PHY_ADDR 16 bit r/o PHY Address Register *****/
1269 /***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1270 /***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/
1271 #define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */
1272 #define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */
1273 #define PHY_M_AN_RF BIT_13 /* Remote Fault */
1274 /* Bit 12: reserved */
1275 #define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */
1276 #define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */
1277 #define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */
1278 #define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */
1279 #define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */
1280 #define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */
1282 /* special defines for FIBER (88E1011S only) */
1283 #define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */
1284 #define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */
1285 #define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */
1286 #define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */
1288 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1289 #define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */
1290 #define PHY_M_P_SYM_MD_X (1<<7) /* Bit 8.. 7: symmetric Pause Mode */
1291 #define PHY_M_P_ASYM_MD_X (2<<7) /* Bit 8.. 7: asymmetric Pause Mode */
1292 #define PHY_M_P_BOTH_MD_X (3<<7) /* Bit 8.. 7: both Pause Mode */
1294 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1295 #define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */
1296 #define PHY_M_1000C_MSE (1<<12) /* Bit 12: Manual Master/Slave Enable */
1297 #define PHY_M_1000C_MSC (1<<11) /* Bit 11: M/S Configuration (1=Master) */
1298 #define PHY_M_1000C_MPD (1<<10) /* Bit 10: Multi-Port Device */
1299 #define PHY_M_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */
1300 #define PHY_M_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */
1301 /* Bit 7..0: reserved */
1303 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1305 #define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */
1306 #define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */
1307 #define PHY_M_PC_ASS_CRS_TX (1<<11) /* Bit 11: Assert CRS on Transmit */
1308 #define PHY_M_PC_FL_GOOD (1<<10) /* Bit 10: Force Link Good */
1309 #define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */
1310 #define PHY_M_PC_ENA_EXT_D (1<<7) /* Bit 7: Enable Ext. Distance (10BT) */
1311 #define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */
1312 #define PHY_M_PC_DIS_125CLK (1<<4) /* Bit 4: Disable 125 CLK */
1313 #define PHY_M_PC_MAC_POW_UP (1<<3) /* Bit 3: MAC Power up */
1314 #define PHY_M_PC_SQE_T_ENA (1<<2) /* Bit 2: SQE Test Enabled */
1315 #define PHY_M_PC_POL_R_DIS (1<<1) /* Bit 1: Polarity Reversal Disabled */
1316 #define PHY_M_PC_DIS_JABBER (1<<0) /* Bit 0: Disable Jabber */
1318 #define PHY_M_PC_MDI_XMODE(x) SHIFT5(x)
1319 #define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */
1320 #define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */
1321 #define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */
1323 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1324 #define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */
1325 #define PHY_M_PS_SPEED_1000 (1<<15) /* 10 = 1000 Mbps */
1326 #define PHY_M_PS_SPEED_100 (1<<14) /* 01 = 100 Mbps */
1327 #define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */
1328 #define PHY_M_PS_FULL_DUP (1<<13) /* Bit 13: Full Duplex */
1329 #define PHY_M_PS_PAGE_REC (1<<12) /* Bit 12: Page Received */
1330 #define PHY_M_PS_SPDUP_RES (1<<11) /* Bit 11: Speed & Duplex Resolved */
1331 #define PHY_M_PS_LINK_UP (1<<10) /* Bit 10: Link Up */
1332 #define PHY_M_PS_CABLE_MSK (3<<7) /* Bit 9.. 7: Cable Length Mask */
1333 #define PHY_M_PS_MDI_X_STAT (1<<6) /* Bit 6: MDI Crossover Stat (1=MDIX) */
1334 #define PHY_M_PS_DOWNS_STAT (1<<5) /* Bit 5: Downshift Status (1=downsh.) */
1335 #define PHY_M_PS_ENDET_STAT (1<<4) /* Bit 4: Energy Detect Status (1=act) */
1336 #define PHY_M_PS_TX_P_EN (1<<3) /* Bit 3: Tx Pause Enabled */
1337 #define PHY_M_PS_RX_P_EN (1<<2) /* Bit 2: Rx Pause Enabled */
1338 #define PHY_M_PS_POL_REV (1<<1) /* Bit 1: Polarity Reversed */
1339 #define PHY_M_PC_JABBER (1<<0) /* Bit 0: Jabber */
1341 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1343 /***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1344 /***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1345 #define PHY_M_IS_AN_ERROR (1<<15) /* Bit 15: Auto-Negotiation Error */
1346 #define PHY_M_IS_LSP_CHANGE (1<<14) /* Bit 14: Link Speed Changed */
1347 #define PHY_M_IS_DUP_CHANGE (1<<13) /* Bit 13: Duplex Mode Changed */
1348 #define PHY_M_IS_AN_PR (1<<12) /* Bit 12: Page Received */
1349 #define PHY_M_IS_AN_COMPL (1<<11) /* Bit 11: Auto-Negotiation Completed */
1350 #define PHY_M_IS_LST_CHANGE (1<<10) /* Bit 10: Link Status Changed */
1351 #define PHY_M_IS_SYMB_ERROR (1<<9) /* Bit 9: Symbol Error */
1352 #define PHY_M_IS_FALSE_CARR (1<<8) /* Bit 8: False Carrier */
1353 #define PHY_M_IS_FIFO_ERROR (1<<7) /* Bit 7: FIFO Overflow/Underrun Error */
1354 #define PHY_M_IS_MDI_CHANGE (1<<6) /* Bit 6: MDI Crossover Changed */
1355 #define PHY_M_IS_DOWNSH_DET (1<<5) /* Bit 5: Downshift Detected */
1356 #define PHY_M_IS_END_CHANGE (1<<4) /* Bit 4: Energy Detect Changed */
1357 /* Bit 3..2: reserved */
1358 #define PHY_M_IS_POL_CHANGE (1<<1) /* Bit 1: Polarity Changed */
1359 #define PHY_M_IS_JABBER (1<<0) /* Bit 0: Jabber */
1361 #define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \
1362 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)
1364 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1365 #define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master downshift counter */
1366 #define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave downshift counter */
1367 #define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */
1369 #define PHY_M_EC_M_DSC(x) SHIFT10(x) /* 00=1x; 01=2x; 10=3x; 11=4x */
1370 #define PHY_M_EC_S_DSC(x) SHIFT8(x) /* 00=dis; 01=1x; 10=2x; 11=3x */
1371 #define PHY_M_EC_MAC_S(x) SHIFT4(x) /* 01X=0; 110=2.5; 111=25 (MHz) */
1373 #define MAC_TX_CLK_0_MHZ 2
1374 #define MAC_TX_CLK_2_5_MHZ 6
1375 #define MAC_TX_CLK_25_MHZ 7
1377 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1378 #define PHY_M_LEDC_DIS_LED (1<<15) /* Bit 15: Disable LED */
1379 #define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */
1380 #define PHY_M_LEDC_F_INT (1<<11) /* Bit 11: Force Interrupt */
1381 #define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */
1382 /* Bit 7.. 5: reserved */
1383 #define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */
1384 #define PHY_M_LEDC_DP_CTRL (1<<2) /* Bit 2: Duplex Control */
1385 #define PHY_M_LEDC_RX_CTRL (1<<1) /* Bit 1: Rx activity / Link */
1386 #define PHY_M_LEDC_TX_CTRL (1<<0) /* Bit 0: Tx activity / Link */
1388 #define PHY_M_LED_PULS_DUR(x) SHIFT12(x) /* Pulse Stretch Duration */
1390 #define PULS_NO_STR 0 /* no pulse stretching */
1391 #define PULS_21MS 1 /* 21 ms to 42 ms */
1392 #define PULS_42MS 2 /* 42 ms to 84 ms */
1393 #define PULS_84MS 3 /* 84 ms to 170 ms */
1394 #define PULS_170MS 4 /* 170 ms to 340 ms */
1395 #define PULS_340MS 5 /* 340 ms to 670 ms */
1396 #define PULS_670MS 6 /* 670 ms to 1.3 s */
1397 #define PULS_1300MS 7 /* 1.3 s to 2.7 s */
1399 #define PHY_M_LED_BLINK_RT(x) SHIFT8(x) /* Blink Rate */
1401 #define BLINK_42MS 0 /* 42 ms */
1402 #define BLINK_84MS 1 /* 84 ms */
1403 #define BLINK_170MS 2 /* 170 ms */
1404 #define BLINK_340MS 3 /* 340 ms */
1405 #define BLINK_670MS 4 /* 670 ms */
1406 /* values 5 - 7: reserved */
1408 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1409 #define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */
1410 #define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */
1411 #define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */
1412 #define PHY_M_LED_MO_1000(x) SHIFT4(x) /* Bit 5.. 4: Link 1000 */
1413 #define PHY_M_LED_MO_RX(x) SHIFT2(x) /* Bit 3.. 2: Rx */
1414 #define PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */
1416 #define MO_LED_NORM 0
1417 #define MO_LED_BLINK 1
1418 #define MO_LED_OFF 2
1421 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1422 /* Bit 15.. 7: reserved */
1423 #define PHY_M_EC2_FI_IMPED (1<<6) /* Bit 6: Fiber Input Impedance */
1424 #define PHY_M_EC2_FO_IMPED (1<<5) /* Bit 5: Fiber Output Impedance */
1425 #define PHY_M_EC2_FO_M_CLK (1<<4) /* Bit 4: Fiber Mode Clock Enable */
1426 #define PHY_M_EC2_FO_BOOST (1<<3) /* Bit 3: Fiber Output Boost */
1427 #define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */
1429 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
1430 #define PHY_M_CABD_ENA_TEST (1<<15) /* Bit 15: Enable Test */
1431 #define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status */
1432 /* Bit 12.. 8: reserved */
1433 #define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance */
1435 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
1436 #define CABD_STAT_NORMAL 0
1437 #define CABD_STAT_SHORT 1
1438 #define CABD_STAT_OPEN 2
1439 #define CABD_STAT_FAIL 3
1445 * The GMAC registers are 16 or 32 bits wide.
1446 * The GMACs host processor interface is 16 bits wide,
1447 * therefore ALL registers will be addressed with 16 bit accesses.
1449 * The following macros are provided to access the GMAC registers
1450 * GM_IN16(), GM_OUT16, GM_IN32(), GM_OUT32(), GM_INADR(), GM_OUTADR(),
1451 * GM_INHASH(), and GM_OUTHASH().
1452 * The macros are defined in SkGeHw.h.
1454 * Note: NA reg = Network Address e.g DA, SA etc.
1458 /* Port Registers */
1459 #define GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */
1460 #define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */
1461 #define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */
1462 #define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */
1463 #define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow Control */
1464 #define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */
1465 #define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */
1467 /* Source Address Registers */
1468 #define GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */
1469 #define GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */
1470 #define GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */
1471 #define GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */
1472 #define GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */
1473 #define GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */
1475 /* Multicast Address Hash Registers */
1476 #define GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */
1477 #define GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */
1478 #define GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */
1479 #define GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */
1481 /* Interrupt Source Registers */
1482 #define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */
1483 #define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */
1484 #define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */
1486 /* Interrupt Mask Registers */
1487 #define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */
1488 #define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */
1489 #define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1491 /* Serial Management Interface (SMI) Registers */
1492 #define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */
1493 #define GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */
1494 #define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */
1497 #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
1498 #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
1501 * MIB Counters base address definitions (low word) -
1502 * use offset 4 for access to high word (32 bit r/o)
1504 #define GM_RXF_UC_OK \
1505 (GM_MIB_CNT_BASE + 0) /* Unicast Frames Received OK */
1506 #define GM_RXF_BC_OK \
1507 (GM_MIB_CNT_BASE + 8) /* Broadcast Frames Received OK */
1508 #define GM_RXF_MPAUSE \
1509 (GM_MIB_CNT_BASE + 16) /* Pause MAC Ctrl Frames Received */
1510 #define GM_RXF_MC_OK \
1511 (GM_MIB_CNT_BASE + 24) /* Multicast Frames Received OK */
1512 #define GM_RXF_FCS_ERR \
1513 (GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */
1514 /* GM_MIB_CNT_BASE + 40: reserved */
1515 #define GM_RXO_OK_LO \
1516 (GM_MIB_CNT_BASE + 48) /* Octets Received OK Low */
1517 #define GM_RXO_OK_HI \
1518 (GM_MIB_CNT_BASE + 56) /* Octets Received OK High */
1519 #define GM_RXO_ERR_LO \
1520 (GM_MIB_CNT_BASE + 64) /* Octets Received Invalid Low */
1521 #define GM_RXO_ERR_HI \
1522 (GM_MIB_CNT_BASE + 72) /* Octets Received Invalid High */
1523 #define GM_RXF_SHT \
1524 (GM_MIB_CNT_BASE + 80) /* Frames <64 Byte Received OK */
1525 #define GM_RXE_FRAG \
1526 (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte Receeived with FCS Err */
1527 #define GM_RXF_64B \
1528 (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */
1529 #define GM_RXF_127B \
1530 (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */
1531 #define GM_RXF_255B \
1532 (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */
1533 #define GM_RXF_511B \
1534 (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */
1535 #define GM_RXF_1023B \
1536 (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */
1537 #define GM_RXF_1518B \
1538 (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */
1539 #define GM_RXF_MAX_SZ \
1540 (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */
1541 #define GM_RXF_LNG_ERR \
1542 (GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */
1543 #define GM_RXF_JAB_PKT \
1544 (GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */
1545 /* GM_MIB_CNT_BASE + 168: reserved */
1546 #define GM_RXE_FIFO_OV \
1547 (GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */
1548 /* GM_MIB_CNT_BASE + 184: reserved */
1549 #define GM_TXF_UC_OK \
1550 (GM_MIB_CNT_BASE + 192) /* Unicast Frames Xmitted OK */
1551 #define GM_TXF_BC_OK \
1552 (GM_MIB_CNT_BASE + 200) /* Broadcast Frames Xmitted OK */
1553 #define GM_TXF_MPAUSE \
1554 (GM_MIB_CNT_BASE + 208) /* Pause MAC Ctrl Frames Xmitted */
1555 #define GM_TXF_MC_OK \
1556 (GM_MIB_CNT_BASE + 216) /* Multicast Frames Xmitted OK */
1557 #define GM_TXO_OK_LO \
1558 (GM_MIB_CNT_BASE + 224) /* Octets Transmitted OK Low */
1559 #define GM_TXO_OK_HI \
1560 (GM_MIB_CNT_BASE + 232) /* Octets Transmitted OK High */
1561 #define GM_TXF_64B \
1562 (GM_MIB_CNT_BASE + 240) /* 64 Byte Tx Frame */
1563 #define GM_TXF_127B \
1564 (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */
1565 #define GM_TXF_255B \
1566 (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */
1567 #define GM_TXF_511B \
1568 (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */
1569 #define GM_TXF_1023B \
1570 (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */
1571 #define GM_TXF_1518B \
1572 (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */
1573 #define GM_TXF_MAX_SZ \
1574 (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */
1575 /* GM_MIB_CNT_BASE + 296: reserved */
1576 #define GM_TXF_COL \
1577 (GM_MIB_CNT_BASE + 304) /* Tx Collision */
1578 #define GM_TXF_LAT_COL \
1579 (GM_MIB_CNT_BASE + 312) /* Tx Late Collision */
1580 #define GM_TXF_ABO_COL \
1581 (GM_MIB_CNT_BASE + 320) /* Tx aborted due to Exces. Col. */
1582 #define GM_TXF_MUL_COL \
1583 (GM_MIB_CNT_BASE + 328) /* Tx Multiple Collision */
1584 #define GM_TXF_SNG_COL \
1585 (GM_MIB_CNT_BASE + 336) /* Tx Single Collision */
1586 #define GM_TXE_FIFO_UR \
1587 (GM_MIB_CNT_BASE + 344) /* Tx FIFO Underrun Event */
1589 /*----------------------------------------------------------------------------*/
1591 * GMAC Bit Definitions
1593 * If the bit access behaviour differs from the register access behaviour
1594 * (r/w, r/o) this is documented after the bit number.
1595 * The following bit access behaviours are used:
1596 * (sc) self clearing
1600 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1602 #define GM_GPSR_SPEED (1<<15) /* Bit 15: Port Speed (1 = 100 Mbps) */
1603 #define GM_GPSR_DUPLEX (1<<14) /* Bit 14: Duplex Mode (1 = Full) */
1604 #define GM_GPSR_FC_TX_DIS (1<<13) /* Bit 13: Tx Flow Control Mode Disabled */
1605 #define GM_GPSR_LINK_UP (1<<12) /* Bit 12: Link Up Status */
1606 #define GM_GPSR_PAUSE (1<<11) /* Bit 11: Pause State */
1607 #define GM_GPSR_TX_ACTIVE (1<<10) /* Bit 10: Tx in Progress */
1608 #define GM_GPSR_EXC_COL (1<<9) /* Bit 9: Excessive Collisions Occured */
1609 #define GM_GPSR_LAT_COL (1<<8) /* Bit 8: Late Collisions Occured */
1610 /* Bit 7..6: reserved */
1611 #define GM_GPSR_PHY_ST_CH (1<<5) /* Bit 5: PHY Status Change */
1612 #define GM_GPSR_GIG_SPEED (1<<4) /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1613 #define GM_GPSR_PART_MODE (1<<3) /* Bit 3: Partition mode */
1614 #define GM_GPSR_FC_RX_DIS (1<<2) /* Bit 2: Rx Flow Control Mode Disabled */
1615 #define GM_GPSR_PROM_EN (1<<1) /* Bit 1: Promiscuous Mode Enabled */
1616 /* Bit 0: reserved */
1618 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1619 /* Bit 15: reserved */
1620 #define GM_GPCR_PROM_ENA (1<<14) /* Bit 14: Enable Promiscuous Mode */
1621 #define GM_GPCR_FC_TX_DIS (1<<13) /* Bit 13: Disable Tx Flow Control Mode */
1622 #define GM_GPCR_TX_ENA (1<<12) /* Bit 12: Enable Transmit */
1623 #define GM_GPCR_RX_ENA (1<<11) /* Bit 11: Enable Receive */
1624 #define GM_GPCR_BURST_ENA (1<<10) /* Bit 10: Enable Burst Mode */
1625 #define GM_GPCR_LOOP_ENA (1<<9) /* Bit 9: Enable MAC Loopback Mode */
1626 #define GM_GPCR_PART_ENA (1<<8) /* Bit 8: Enable Partition Mode */
1627 #define GM_GPCR_GIGS_ENA (1<<7) /* Bit 7: Gigabit Speed (1000 Mbps) */
1628 #define GM_GPCR_FL_PASS (1<<6) /* Bit 6: Force Link Pass */
1629 #define GM_GPCR_DUP_FULL (1<<5) /* Bit 5: Full Duplex Mode */
1630 #define GM_GPCR_FC_RX_DIS (1<<4) /* Bit 4: Disable Rx Flow Control Mode */
1631 #define GM_GPCR_SPEED_100 (1<<3) /* Bit 3: Port Speed 100 Mbps */
1632 #define GM_GPCR_AU_DUP_DIS (1<<2) /* Bit 2: Disable Auto-Update for Duplex */
1633 #define GM_GPCR_AU_FCT_DIS (1<<1) /* Bit 1: Disable Auto-Update for Flow-c. */
1634 #define GM_GPCR_AU_SPD_DIS (1<<0) /* Bit 0: Disable Auto-Update for Speed */
1636 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1637 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\
1640 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1642 #define GM_TXCR_FORCE_JAM (1<<15) /* Bit 15: Force Jam / Flow-Control */
1643 #define GM_TXCR_CRC_DIS (1<<14) /* Bit 14: Disable insertion of CRC */
1644 #define GM_TXCR_PAD_DIS (1<<13) /* Bit 13: Disable padding of packets */
1645 #define GM_TXCR_COL_THR (4<<10) /* Bit 12..10: Collision Threshold */
1647 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1648 #define GM_RXCR_UCF_ENA (1<<15) /* Bit 15: Enable Unicast filtering */
1649 #define GM_RXCR_MCF_ENA (1<<14) /* Bit 14: Enable Multicast filtering */
1650 #define GM_RXCR_CRC_DIS (1<<13) /* Bit 13: Remove 4-byte CRC */
1651 #define GM_RXCR_PASS_FC (1<<12) /* Bit 12: Pass FC packets to FIFO */
1653 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1654 #define GM_TXPA_JAMLEN_MSK (0x03<<14) /* Bit 15..14: Jam Length */
1655 #define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13..9: Jam IPG */
1656 #define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8..4: IPG Jam to Data */
1657 /* Bit 3..0: reserved */
1658 #define JAM_LEN_VAL(x) SHIFT14(x)
1659 #define JAM_IPG_VAL(x) SHIFT9(x)
1660 #define IPG_JAM_DATA(x) SHIFT4(x)
1662 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1663 #define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */
1664 #define GM_SMOD_LIMIT_4 (1<<10) /* Bit 10: 4 consecutive transmit trials */
1665 #define GM_SMOD_VLAN_ENA (1<<9) /* Bit 9: Enable VLAN (Max. Frame Length) */
1666 #define GM_SMOD_JUMBO_ENA (1<<8) /* Bit 8: Enable Jumbo (Max. Frame Length) */
1667 /* Bit 7..5: reserved */
1668 #define GM_SMOD_IPG_MSK 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1670 #define DATA_BLIND_VAL(x) SHIFT11(x)
1671 #define DATA_BLIND_FAST_ETH 0x1c
1672 #define DATA_BLIND_GIGABIT 4
1674 #define IPG_VAL_FAST_ETH 0x1e
1675 #define IPG_VAL_GIGABIT 6
1677 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1679 #define GM_SMI_CT_PHY_AD(x) SHIFT11(x)
1680 #define GM_SMI_CT_REG_AD(x) SHIFT6(x)
1681 #define GM_SMI_CT_OP_RD (1<<5) /* Bit 5: OpCode Read (0=Write)*/
1682 #define GM_SMI_CT_RD_VAL (1<<4) /* Bit 4: Read Valid (Read completed) */
1683 #define GM_SMI_CT_BUSY (1<<3) /* Bit 3: Busy (Operation in progress) */
1684 /* Bit 2..0: reserved */
1686 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1687 /* Bit 15..6: reserved */
1688 #define GM_PAR_MIB_CLR (1<<5) /* Bit 5: Set MIB Clear Counter Mode */
1689 #define GM_PAR_MIB_TST (1<<4) /* Bit 4: MIB Load Counter (Test Mode) */
1690 /* Bit 3..0: reserved */
1692 /* Receive Frame Status Encoding */
1693 #define GMR_FS_LEN (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */
1694 /* Bit 15..14: reserved */
1695 #define GMR_FS_VLAN (1L<<13) /* Bit 13: VLAN Packet */
1696 #define GMR_FS_JABBER (1L<<12) /* Bit 12: Jabber Packet */
1697 #define GMR_FS_UN_SIZE (1L<<11) /* Bit 11: Undersize Packet */
1698 #define GMR_FS_MC (1L<<10) /* Bit 10: Multicast Packet */
1699 #define GMR_FS_BC (1L<<9) /* Bit 9: Broadcast Packet */
1700 #define GMR_FS_RX_OK (1L<<8) /* Bit 8: Receive OK (Good Packet) */
1701 #define GMR_FS_GOOD_FC (1L<<7) /* Bit 7: Good Flow-Control Packet */
1702 #define GMR_FS_BAD_FC (1L<<6) /* Bit 6: Bad Flow-Control Packet */
1703 #define GMR_FS_MII_ERR (1L<<5) /* Bit 5: MII Error */
1704 #define GMR_FS_LONG_ERR (1L<<4) /* Bit 4: Too Long Packet */
1705 #define GMR_FS_FRAGMENT (1L<<3) /* Bit 3: Fragment */
1706 /* Bit 2: reserved */
1707 #define GMR_FS_CRC_ERR (1L<<1) /* Bit 1: CRC Error */
1708 #define GMR_FS_RX_FF_OV (1L<<0) /* Bit 0: Rx FIFO Overflow */
1711 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
1713 #define GMR_FS_ANY_ERR (GMR_FS_CRC_ERR | \
1720 /* Rx GMAC FIFO Flush Mask (default) */
1721 #define RX_FF_FL_DEF_MSK (GMR_FS_CRC_ERR | \
1729 /* typedefs *******************************************************************/
1732 /* function prototypes ********************************************************/
1736 #endif /* __cplusplus */
1738 #endif /* __INC_XMAC_H */