3 * Author: Amit Singh Tomar, amittomer25@gmail.com
5 * SPDX-License-Identifier: GPL-2.0+
7 * Ethernet driver for H3/A64/A83T based SoC's
9 * It is derived from the work done by
10 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
15 #include <asm/arch/clock.h>
16 #include <asm/arch/gpio.h>
19 #include <fdt_support.h>
20 #include <linux/err.h>
25 #define MDIO_CMD_MII_BUSY BIT(0)
26 #define MDIO_CMD_MII_WRITE BIT(1)
28 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
29 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
30 #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
31 #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
33 #define CONFIG_TX_DESCR_NUM 32
34 #define CONFIG_RX_DESCR_NUM 32
35 #define CONFIG_ETH_BUFSIZE 2024
37 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
38 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
40 #define H3_EPHY_DEFAULT_VALUE 0x58000
41 #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
42 #define H3_EPHY_ADDR_SHIFT 20
43 #define REG_PHY_ADDR_MASK GENMASK(4, 0)
44 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
45 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
46 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
48 #define SC_RMII_EN BIT(13)
49 #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
50 #define SC_ETCS_MASK GENMASK(1, 0)
51 #define SC_ETCS_EXT_GMII 0x1
52 #define SC_ETCS_INT_GMII 0x2
54 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
56 #define AHB_GATE_OFFSET_EPHY 0
58 #if defined(CONFIG_MACH_SUN8I_H3)
59 #define SUN8I_GPD8_GMAC 2
61 #define SUN8I_GPD8_GMAC 4
64 /* H3/A64 EMAC Register's offset */
65 #define EMAC_CTL0 0x00
66 #define EMAC_CTL1 0x04
67 #define EMAC_INT_STA 0x08
68 #define EMAC_INT_EN 0x0c
69 #define EMAC_TX_CTL0 0x10
70 #define EMAC_TX_CTL1 0x14
71 #define EMAC_TX_FLOW_CTL 0x1c
72 #define EMAC_TX_DMA_DESC 0x20
73 #define EMAC_RX_CTL0 0x24
74 #define EMAC_RX_CTL1 0x28
75 #define EMAC_RX_DMA_DESC 0x34
76 #define EMAC_MII_CMD 0x48
77 #define EMAC_MII_DATA 0x4c
78 #define EMAC_ADDR0_HIGH 0x50
79 #define EMAC_ADDR0_LOW 0x54
80 #define EMAC_TX_DMA_STA 0xb0
81 #define EMAC_TX_CUR_DESC 0xb4
82 #define EMAC_TX_CUR_BUF 0xb8
83 #define EMAC_RX_DMA_STA 0xc0
84 #define EMAC_RX_CUR_DESC 0xc4
86 DECLARE_GLOBAL_DATA_PTR;
94 struct emac_dma_desc {
99 } __aligned(ARCH_DMA_MINALIGN);
101 struct emac_eth_dev {
102 struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
103 struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
104 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
105 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
117 bool use_internal_phy;
119 enum emac_variant variant;
121 phys_addr_t sysctl_reg;
122 struct phy_device *phydev;
126 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
128 struct emac_eth_dev *priv = bus->priv;
131 int timeout = CONFIG_MDIO_TIMEOUT;
133 miiaddr &= ~MDIO_CMD_MII_WRITE;
134 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
135 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
136 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
138 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
140 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
141 MDIO_CMD_MII_PHY_ADDR_MASK;
143 miiaddr |= MDIO_CMD_MII_BUSY;
145 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
147 start = get_timer(0);
148 while (get_timer(start) < timeout) {
149 if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
150 return readl(priv->mac_reg + EMAC_MII_DATA);
157 static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
160 struct emac_eth_dev *priv = bus->priv;
163 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
165 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
166 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
167 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
169 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
170 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
171 MDIO_CMD_MII_PHY_ADDR_MASK;
173 miiaddr |= MDIO_CMD_MII_WRITE;
174 miiaddr |= MDIO_CMD_MII_BUSY;
176 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
177 writel(val, priv->mac_reg + EMAC_MII_DATA);
179 start = get_timer(0);
180 while (get_timer(start) < timeout) {
181 if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
182 MDIO_CMD_MII_BUSY)) {
192 static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
194 u32 macid_lo, macid_hi;
196 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
198 macid_hi = mac_id[4] + (mac_id[5] << 8);
200 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
201 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
206 static void sun8i_adjust_link(struct emac_eth_dev *priv,
207 struct phy_device *phydev)
211 v = readl(priv->mac_reg + EMAC_CTL0);
220 switch (phydev->speed) {
231 writel(v, priv->mac_reg + EMAC_CTL0);
234 static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
236 if (priv->use_internal_phy) {
237 /* H3 based SoC's that has an Internal 100MBit PHY
238 * needs to be configured and powered up before use
240 *reg &= ~H3_EPHY_DEFAULT_MASK;
241 *reg |= H3_EPHY_DEFAULT_VALUE;
242 *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
243 *reg &= ~H3_EPHY_SHUTDOWN;
244 *reg |= H3_EPHY_SELECT;
246 /* This is to select External Gigabit PHY on
247 * the boards with H3 SoC.
249 *reg &= ~H3_EPHY_SELECT;
254 static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)
259 reg = readl(priv->sysctl_reg);
261 if (priv->variant == H3_EMAC) {
262 ret = sun8i_emac_set_syscon_ephy(priv, ®);
267 reg &= ~(SC_ETCS_MASK | SC_EPIT);
268 if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
271 switch (priv->interface) {
272 case PHY_INTERFACE_MODE_MII:
275 case PHY_INTERFACE_MODE_RGMII:
276 reg |= SC_EPIT | SC_ETCS_INT_GMII;
278 case PHY_INTERFACE_MODE_RMII:
279 if (priv->variant == H3_EMAC ||
280 priv->variant == A64_EMAC) {
281 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
284 /* RMII not supported on A83T */
286 debug("%s: Invalid PHY interface\n", __func__);
290 writel(reg, priv->sysctl_reg);
295 static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
297 struct phy_device *phydev;
299 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
303 phy_connect_dev(phydev, dev);
305 priv->phydev = phydev;
306 phy_config(priv->phydev);
311 static void rx_descs_init(struct emac_eth_dev *priv)
313 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
314 char *rxbuffs = &priv->rxbuffer[0];
315 struct emac_dma_desc *desc_p;
318 /* flush Rx buffers */
319 flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
322 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
323 desc_p = &desc_table_p[idx];
324 desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
326 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
327 desc_p->st |= CONFIG_ETH_BUFSIZE;
328 desc_p->status = BIT(31);
331 /* Correcting the last pointer of the chain */
332 desc_p->next = (uintptr_t)&desc_table_p[0];
334 flush_dcache_range((uintptr_t)priv->rx_chain,
335 (uintptr_t)priv->rx_chain +
336 sizeof(priv->rx_chain));
338 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
339 priv->rx_currdescnum = 0;
342 static void tx_descs_init(struct emac_eth_dev *priv)
344 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
345 char *txbuffs = &priv->txbuffer[0];
346 struct emac_dma_desc *desc_p;
349 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
350 desc_p = &desc_table_p[idx];
351 desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
353 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
354 desc_p->status = (1 << 31);
358 /* Correcting the last pointer of the chain */
359 desc_p->next = (uintptr_t)&desc_table_p[0];
361 /* Flush all Tx buffer descriptors */
362 flush_dcache_range((uintptr_t)priv->tx_chain,
363 (uintptr_t)priv->tx_chain +
364 sizeof(priv->tx_chain));
366 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
367 priv->tx_currdescnum = 0;
370 static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
375 reg = readl((priv->mac_reg + EMAC_CTL1));
379 setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
381 reg = readl(priv->mac_reg + EMAC_CTL1);
382 } while ((reg & 0x01) != 0 && (--timeout));
384 printf("%s: Timeout\n", __func__);
389 /* Rewrite mac address after reset */
390 _sun8i_write_hwaddr(priv, enetaddr);
392 v = readl(priv->mac_reg + EMAC_TX_CTL1);
393 /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
395 writel(v, priv->mac_reg + EMAC_TX_CTL1);
397 v = readl(priv->mac_reg + EMAC_RX_CTL1);
398 /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
399 * complete frame has been written to RX DMA FIFO
402 writel(v, priv->mac_reg + EMAC_RX_CTL1);
405 writel(8 << 24, priv->mac_reg + EMAC_CTL1);
407 /* Initialize rx/tx descriptors */
412 genphy_parse_link(priv->phydev);
414 sun8i_adjust_link(priv, priv->phydev);
417 v = readl(priv->mac_reg + EMAC_RX_CTL1);
419 writel(v, priv->mac_reg + EMAC_RX_CTL1);
421 v = readl(priv->mac_reg + EMAC_TX_CTL1);
423 writel(v, priv->mac_reg + EMAC_TX_CTL1);
426 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
427 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
432 static int parse_phy_pins(struct udevice *dev)
435 const char *pin_name;
438 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
441 printf("WARNING: emac: cannot find pinctrl-0 node\n");
445 drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
446 "allwinner,drive", 4);
447 pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
448 "allwinner,pull", 0);
452 if (fdt_get_string_index(gd->fdt_blob, offset,
453 "allwinner,pins", i, &pin_name))
455 if (pin_name[0] != 'P')
457 pin = (pin_name[1] - 'A') << 5;
460 pin += simple_strtol(&pin_name[2], NULL, 10);
462 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC);
463 sunxi_gpio_set_drv(pin, drive);
464 sunxi_gpio_set_pull(pin, pull);
468 printf("WARNING: emac: cannot find allwinner,pins property\n");
475 static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
477 u32 status, desc_num = priv->rx_currdescnum;
478 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
479 int length = -EAGAIN;
481 uintptr_t desc_start = (uintptr_t)desc_p;
482 uintptr_t desc_end = desc_start +
483 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
485 ulong data_start = (uintptr_t)desc_p->buf_addr;
488 /* Invalidate entire buffer descriptor */
489 invalidate_dcache_range(desc_start, desc_end);
491 status = desc_p->status;
493 /* Check for DMA own bit */
494 if (!(status & BIT(31))) {
495 length = (desc_p->status >> 16) & 0x3FFF;
499 debug("RX: Bad Packet (runt)\n");
502 data_end = data_start + length;
503 /* Invalidate received data */
504 invalidate_dcache_range(rounddown(data_start,
509 if (length > CONFIG_ETH_BUFSIZE) {
510 printf("Received packet is too big (len=%d)\n",
514 *packetp = (uchar *)(ulong)desc_p->buf_addr;
522 static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
525 u32 v, desc_num = priv->tx_currdescnum;
526 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
527 uintptr_t desc_start = (uintptr_t)desc_p;
528 uintptr_t desc_end = desc_start +
529 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
531 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
532 uintptr_t data_end = data_start +
533 roundup(len, ARCH_DMA_MINALIGN);
535 /* Invalidate entire buffer descriptor */
536 invalidate_dcache_range(desc_start, desc_end);
539 /* Mandatory undocumented bit */
540 desc_p->st |= BIT(24);
542 memcpy((void *)data_start, packet, len);
544 /* Flush data to be sent */
545 flush_dcache_range(data_start, data_end);
548 desc_p->st |= BIT(30);
549 desc_p->st |= BIT(31);
552 desc_p->st |= BIT(29);
553 desc_p->status = BIT(31);
555 /*Descriptors st and status field has changed, so FLUSH it */
556 flush_dcache_range(desc_start, desc_end);
558 /* Move to next Descriptor and wrap around */
559 if (++desc_num >= CONFIG_TX_DESCR_NUM)
561 priv->tx_currdescnum = desc_num;
564 v = readl(priv->mac_reg + EMAC_TX_CTL1);
565 v |= BIT(31);/* mandatory */
566 v |= BIT(30);/* mandatory */
567 writel(v, priv->mac_reg + EMAC_TX_CTL1);
572 static int sun8i_eth_write_hwaddr(struct udevice *dev)
574 struct eth_pdata *pdata = dev_get_platdata(dev);
575 struct emac_eth_dev *priv = dev_get_priv(dev);
577 return _sun8i_write_hwaddr(priv, pdata->enetaddr);
580 static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
582 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
584 if (priv->use_internal_phy) {
585 /* Set clock gating for ephy */
586 setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
589 setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
592 /* Set clock gating for emac */
593 setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
596 setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
599 static int sun8i_mdio_init(const char *name, struct emac_eth_dev *priv)
601 struct mii_dev *bus = mdio_alloc();
604 debug("Failed to allocate MDIO bus\n");
608 bus->read = sun8i_mdio_read;
609 bus->write = sun8i_mdio_write;
610 snprintf(bus->name, sizeof(bus->name), name);
611 bus->priv = (void *)priv;
613 return mdio_register(bus);
616 static int sun8i_emac_eth_start(struct udevice *dev)
618 struct eth_pdata *pdata = dev_get_platdata(dev);
620 return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
623 static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
625 struct emac_eth_dev *priv = dev_get_priv(dev);
627 return _sun8i_emac_eth_send(priv, packet, length);
630 static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
632 struct emac_eth_dev *priv = dev_get_priv(dev);
634 return _sun8i_eth_recv(priv, packetp);
637 static int _sun8i_free_pkt(struct emac_eth_dev *priv)
639 u32 desc_num = priv->rx_currdescnum;
640 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
641 uintptr_t desc_start = (uintptr_t)desc_p;
642 uintptr_t desc_end = desc_start +
643 roundup(sizeof(u32), ARCH_DMA_MINALIGN);
645 /* Make the current descriptor valid again */
646 desc_p->status |= BIT(31);
648 /* Flush Status field of descriptor */
649 flush_dcache_range(desc_start, desc_end);
651 /* Move to next desc and wrap-around condition. */
652 if (++desc_num >= CONFIG_RX_DESCR_NUM)
654 priv->rx_currdescnum = desc_num;
659 static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
662 struct emac_eth_dev *priv = dev_get_priv(dev);
664 return _sun8i_free_pkt(priv);
667 static void sun8i_emac_eth_stop(struct udevice *dev)
669 struct emac_eth_dev *priv = dev_get_priv(dev);
671 /* Stop Rx/Tx transmitter */
672 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
673 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
676 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
678 phy_shutdown(priv->phydev);
681 static int sun8i_emac_eth_probe(struct udevice *dev)
683 struct eth_pdata *pdata = dev_get_platdata(dev);
684 struct emac_eth_dev *priv = dev_get_priv(dev);
686 priv->mac_reg = (void *)pdata->iobase;
688 sun8i_emac_board_setup(priv);
689 sun8i_emac_set_syscon(priv);
691 sun8i_mdio_init(dev->name, priv);
692 priv->bus = miiphy_get_dev_by_name(dev->name);
694 return sun8i_phy_init(priv, dev);
697 static const struct eth_ops sun8i_emac_eth_ops = {
698 .start = sun8i_emac_eth_start,
699 .write_hwaddr = sun8i_eth_write_hwaddr,
700 .send = sun8i_emac_eth_send,
701 .recv = sun8i_emac_eth_recv,
702 .free_pkt = sun8i_eth_free_pkt,
703 .stop = sun8i_emac_eth_stop,
706 static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
708 struct eth_pdata *pdata = dev_get_platdata(dev);
709 struct emac_eth_dev *priv = dev_get_priv(dev);
710 const char *phy_mode;
713 pdata->iobase = dev_get_addr_name(dev, "emac");
714 priv->sysctl_reg = dev_get_addr_name(dev, "syscon");
716 pdata->phy_interface = -1;
718 priv->use_internal_phy = false;
720 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
723 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg",
726 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
729 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
730 printf("phy interface%d\n", pdata->phy_interface);
732 if (pdata->phy_interface == -1) {
733 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
737 priv->variant = dev_get_driver_data(dev);
739 if (!priv->variant) {
740 printf("%s: Missing variant '%s'\n", __func__,
741 (char *)priv->variant);
745 if (priv->variant == H3_EMAC) {
746 if (fdt_getprop(gd->fdt_blob, dev->of_offset,
747 "allwinner,use-internal-phy", NULL))
748 priv->use_internal_phy = true;
751 priv->interface = pdata->phy_interface;
753 if (!priv->use_internal_phy)
759 static const struct udevice_id sun8i_emac_eth_ids[] = {
760 {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
761 {.compatible = "allwinner,sun50i-a64-emac",
762 .data = (uintptr_t)A64_EMAC },
763 {.compatible = "allwinner,sun8i-a83t-emac",
764 .data = (uintptr_t)A83T_EMAC },
768 U_BOOT_DRIVER(eth_sun8i_emac) = {
769 .name = "eth_sun8i_emac",
771 .of_match = sun8i_emac_eth_ids,
772 .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
773 .probe = sun8i_emac_eth_probe,
774 .ops = &sun8i_emac_eth_ops,
775 .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
776 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
777 .flags = DM_FLAG_ALLOC_PRIV_DMA,