2 * Freescale Three Speed Ethernet Controller driver
4 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
5 * (C) Copyright 2003, Motorola, Inc.
8 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/errno.h>
19 #include <asm/processor.h>
22 DECLARE_GLOBAL_DATA_PTR;
27 static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8);
28 static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8);
31 #error "rtx must be 64-bit aligned"
34 static int tsec_send(struct eth_device *dev, void *packet, int length);
36 /* Default initializations for TSEC controllers. */
38 static struct tsec_info_struct tsec_info[] = {
40 STD_TSEC_INFO(1), /* TSEC1 */
43 STD_TSEC_INFO(2), /* TSEC2 */
45 #ifdef CONFIG_MPC85XX_FEC
47 .regs = TSEC_GET_REGS(2, 0x2000),
48 .devname = CONFIG_MPC85XX_FEC_NAME,
49 .phyaddr = FEC_PHY_ADDR,
51 .mii_devname = DEFAULT_MII_NAME
55 STD_TSEC_INFO(3), /* TSEC3 */
58 STD_TSEC_INFO(4), /* TSEC4 */
62 #define TBIANA_SETTINGS ( \
63 TBIANA_ASYMMETRIC_PAUSE \
64 | TBIANA_SYMMETRIC_PAUSE \
65 | TBIANA_FULL_DUPLEX \
68 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
69 #ifndef CONFIG_TSEC_TBICR_SETTINGS
70 #define CONFIG_TSEC_TBICR_SETTINGS ( \
76 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
78 /* Configure the TBI for SGMII operation */
79 static void tsec_configure_serdes(struct tsec_private *priv)
82 * Access TBI PHY registers at given TSEC register offset as opposed
83 * to the register offset used for external PHY accesses
85 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
86 0, TBI_ANA, TBIANA_SETTINGS);
87 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
88 0, TBI_TBICON, TBICON_CLK_SELECT);
89 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
90 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
93 #ifdef CONFIG_MCAST_TFTP
95 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
97 /* Set the appropriate hash bit for the given addr */
100 * The algorithm works like so:
101 * 1) Take the Destination Address (ie the multicast address), and
102 * do a CRC on it (little endian), and reverse the bits of the
104 * 2) Use the 8 most significant bits as a hash into a 256-entry
105 * table. The table is controlled through 8 32-bit registers:
106 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
107 * 255. This means that the 3 most significant bits in the
108 * hash index which gaddr register to use, and the 5 other bits
109 * indicate which bit (assuming an IBM numbering scheme, which
110 * for PowerPC (tm) is usually the case) in the register holds
113 static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
115 struct tsec_private *priv = (struct tsec_private *)dev->priv;
116 struct tsec __iomem *regs = priv->regs;
118 u8 whichbit, whichreg;
120 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
121 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
122 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
124 value = 1 << (31-whichbit);
127 setbits_be32(®s->hash.gaddr0 + whichreg, value);
129 clrbits_be32(®s->hash.gaddr0 + whichreg, value);
133 #endif /* Multicast TFTP ? */
136 * Initialized required registers to appropriate values, zeroing
137 * those we don't care about (unless zero is bad, in which case,
138 * choose a more appropriate value)
140 static void init_registers(struct tsec __iomem *regs)
143 out_be32(®s->ievent, IEVENT_INIT_CLEAR);
145 out_be32(®s->imask, IMASK_INIT_CLEAR);
147 out_be32(®s->hash.iaddr0, 0);
148 out_be32(®s->hash.iaddr1, 0);
149 out_be32(®s->hash.iaddr2, 0);
150 out_be32(®s->hash.iaddr3, 0);
151 out_be32(®s->hash.iaddr4, 0);
152 out_be32(®s->hash.iaddr5, 0);
153 out_be32(®s->hash.iaddr6, 0);
154 out_be32(®s->hash.iaddr7, 0);
156 out_be32(®s->hash.gaddr0, 0);
157 out_be32(®s->hash.gaddr1, 0);
158 out_be32(®s->hash.gaddr2, 0);
159 out_be32(®s->hash.gaddr3, 0);
160 out_be32(®s->hash.gaddr4, 0);
161 out_be32(®s->hash.gaddr5, 0);
162 out_be32(®s->hash.gaddr6, 0);
163 out_be32(®s->hash.gaddr7, 0);
165 out_be32(®s->rctrl, 0x00000000);
167 /* Init RMON mib registers */
168 memset((void *)®s->rmon, 0, sizeof(regs->rmon));
170 out_be32(®s->rmon.cam1, 0xffffffff);
171 out_be32(®s->rmon.cam2, 0xffffffff);
173 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
175 out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
177 out_be32(®s->attr, ATTR_INIT_SETTINGS);
178 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
183 * Configure maccfg2 based on negotiated speed and duplex
184 * reported by PHY handling code
186 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
188 struct tsec __iomem *regs = priv->regs;
192 printf("%s: No link.\n", phydev->dev->name);
196 /* clear all bits relative with interface mode */
197 ecntrl = in_be32(®s->ecntrl);
198 ecntrl &= ~ECNTRL_R100;
200 maccfg2 = in_be32(®s->maccfg2);
201 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
204 maccfg2 |= MACCFG2_FULL_DUPLEX;
206 switch (phydev->speed) {
208 maccfg2 |= MACCFG2_GMII;
212 maccfg2 |= MACCFG2_MII;
215 * Set R100 bit in all modes although
216 * it is only used in RGMII mode
218 if (phydev->speed == 100)
219 ecntrl |= ECNTRL_R100;
222 printf("%s: Speed was bad\n", phydev->dev->name);
226 out_be32(®s->ecntrl, ecntrl);
227 out_be32(®s->maccfg2, maccfg2);
229 printf("Speed: %d, %s duplex%s\n", phydev->speed,
230 (phydev->duplex) ? "full" : "half",
231 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
234 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
236 * When MACCFG1[Rx_EN] is enabled during system boot as part
237 * of the eTSEC port initialization sequence,
238 * the eTSEC Rx logic may not be properly initialized.
240 void redundant_init(struct eth_device *dev)
242 struct tsec_private *priv = dev->priv;
243 struct tsec __iomem *regs = priv->regs;
246 static const u8 pkt[] = {
247 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
248 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
249 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
250 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
251 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
252 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
253 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
254 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
255 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
256 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
257 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
258 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
259 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
262 /* Enable promiscuous mode */
263 setbits_be32(®s->rctrl, 0x8);
264 /* Enable loopback mode */
265 setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
266 /* Enable transmit and receive */
267 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
269 /* Tell the DMA it is clear to go */
270 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
271 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
272 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
273 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
277 tsec_send(dev, (void *)pkt, sizeof(pkt));
279 /* Wait for buffer to be received */
280 for (t = 0; in_be16(&rxbd[priv->rx_idx].status) & RXBD_EMPTY;
282 if (t >= 10 * TOUT_LOOP) {
283 printf("%s: tsec: rx error\n", dev->name);
288 if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
291 out_be16(&rxbd[priv->rx_idx].length, 0);
293 if ((priv->rx_idx + 1) == PKTBUFSRX)
295 out_be16(&rxbd[priv->rx_idx].status, status);
296 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
298 if (in_be32(®s->ievent) & IEVENT_BSY) {
299 out_be32(®s->ievent, IEVENT_BSY);
300 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
303 printf("loopback recv packet error!\n");
304 clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
306 setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
308 } while ((count++ < 4) && (fail == 1));
311 panic("eTSEC init fail!\n");
312 /* Disable promiscuous mode */
313 clrbits_be32(®s->rctrl, 0x8);
314 /* Disable loopback mode */
315 clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
320 * Set up the buffers and their descriptors, and bring up the
323 static void startup_tsec(struct eth_device *dev)
325 struct tsec_private *priv = (struct tsec_private *)dev->priv;
326 struct tsec __iomem *regs = priv->regs;
330 /* reset the indices to zero */
333 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
337 /* Point to the buffer descriptors */
338 out_be32(®s->tbase, (u32)&txbd[0]);
339 out_be32(®s->rbase, (u32)&rxbd[0]);
341 /* Initialize the Rx Buffer descriptors */
342 for (i = 0; i < PKTBUFSRX; i++) {
343 out_be16(&rxbd[i].status, RXBD_EMPTY);
344 out_be16(&rxbd[i].length, 0);
345 out_be32(&rxbd[i].bufptr, (u32)net_rx_packets[i]);
347 status = in_be16(&rxbd[PKTBUFSRX - 1].status);
348 out_be16(&rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
350 /* Initialize the TX Buffer Descriptors */
351 for (i = 0; i < TX_BUF_CNT; i++) {
352 out_be16(&txbd[i].status, 0);
353 out_be16(&txbd[i].length, 0);
354 out_be32(&txbd[i].bufptr, 0);
356 status = in_be16(&txbd[TX_BUF_CNT - 1].status);
357 out_be16(&txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
359 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
361 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
364 /* Enable Transmit and Receive */
365 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
367 /* Tell the DMA it is clear to go */
368 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
369 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
370 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
371 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
375 * This returns the status bits of the device. The return value
376 * is never checked, and this is what the 8260 driver did, so we
377 * do the same. Presumably, this would be zero if there were no
380 static int tsec_send(struct eth_device *dev, void *packet, int length)
382 struct tsec_private *priv = (struct tsec_private *)dev->priv;
383 struct tsec __iomem *regs = priv->regs;
388 /* Find an empty buffer descriptor */
389 for (i = 0; in_be16(&txbd[priv->tx_idx].status) & TXBD_READY; i++) {
390 if (i >= TOUT_LOOP) {
391 debug("%s: tsec: tx buffers full\n", dev->name);
396 out_be32(&txbd[priv->tx_idx].bufptr, (u32)packet);
397 out_be16(&txbd[priv->tx_idx].length, length);
398 status = in_be16(&txbd[priv->tx_idx].status);
399 out_be16(&txbd[priv->tx_idx].status, status |
400 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
402 /* Tell the DMA to go */
403 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
405 /* Wait for buffer to be transmitted */
406 for (i = 0; in_be16(&txbd[priv->tx_idx].status) & TXBD_READY; i++) {
407 if (i >= TOUT_LOOP) {
408 debug("%s: tsec: tx error\n", dev->name);
413 priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
414 result = in_be16(&txbd[priv->tx_idx].status) & TXBD_STATS;
419 static int tsec_recv(struct eth_device *dev)
421 struct tsec_private *priv = (struct tsec_private *)dev->priv;
422 struct tsec __iomem *regs = priv->regs;
424 while (!(in_be16(&rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
425 int length = in_be16(&rxbd[priv->rx_idx].length);
426 uint16_t status = in_be16(&rxbd[priv->rx_idx].status);
427 uchar *packet = net_rx_packets[priv->rx_idx];
429 /* Send the packet up if there were no errors */
430 if (!(status & RXBD_STATS))
431 net_process_received_packet(packet, length - 4);
433 printf("Got error %x\n", (status & RXBD_STATS));
435 out_be16(&rxbd[priv->rx_idx].length, 0);
438 /* Set the wrap bit if this is the last element in the list */
439 if ((priv->rx_idx + 1) == PKTBUFSRX)
441 out_be16(&rxbd[priv->rx_idx].status, status);
443 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
446 if (in_be32(®s->ievent) & IEVENT_BSY) {
447 out_be32(®s->ievent, IEVENT_BSY);
448 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
454 /* Stop the interface */
455 static void tsec_halt(struct eth_device *dev)
457 struct tsec_private *priv = (struct tsec_private *)dev->priv;
458 struct tsec __iomem *regs = priv->regs;
460 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
461 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
463 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
464 != (IEVENT_GRSC | IEVENT_GTSC))
467 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
469 /* Shut down the PHY, as needed */
470 phy_shutdown(priv->phydev);
474 * Initializes data structures and registers for the controller,
475 * and brings the interface up. Returns the link status, meaning
476 * that it returns success if the link is up, failure otherwise.
477 * This allows U-Boot to find the first active controller.
479 static int tsec_init(struct eth_device *dev, bd_t * bd)
481 struct tsec_private *priv = (struct tsec_private *)dev->priv;
482 struct tsec __iomem *regs = priv->regs;
486 /* Make sure the controller is stopped */
489 /* Init MACCFG2. Defaults to GMII */
490 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
493 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
496 * Copy the station address into the address registers.
497 * For a station address of 0x12345678ABCD in transmission
498 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
499 * MACnADDR2 is set to 0x34120000.
501 tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
502 (dev->enetaddr[3] << 8) | dev->enetaddr[2];
504 out_be32(®s->macstnaddr1, tempval);
506 tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
508 out_be32(®s->macstnaddr2, tempval);
510 /* Clear out (for the most part) the other registers */
511 init_registers(regs);
513 /* Ready the device for tx/rx */
516 /* Start up the PHY */
517 ret = phy_startup(priv->phydev);
519 printf("Could not initialize PHY %s\n",
520 priv->phydev->dev->name);
524 adjust_link(priv, priv->phydev);
526 /* If there's no link, fail */
527 return priv->phydev->link ? 0 : -1;
530 static phy_interface_t tsec_get_interface(struct tsec_private *priv)
532 struct tsec __iomem *regs = priv->regs;
535 ecntrl = in_be32(®s->ecntrl);
537 if (ecntrl & ECNTRL_SGMII_MODE)
538 return PHY_INTERFACE_MODE_SGMII;
540 if (ecntrl & ECNTRL_TBI_MODE) {
541 if (ecntrl & ECNTRL_REDUCED_MODE)
542 return PHY_INTERFACE_MODE_RTBI;
544 return PHY_INTERFACE_MODE_TBI;
547 if (ecntrl & ECNTRL_REDUCED_MODE) {
548 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
549 return PHY_INTERFACE_MODE_RMII;
551 phy_interface_t interface = priv->interface;
554 * This isn't autodetected, so it must
555 * be set by the platform code.
557 if ((interface == PHY_INTERFACE_MODE_RGMII_ID) ||
558 (interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
559 (interface == PHY_INTERFACE_MODE_RGMII_RXID))
562 return PHY_INTERFACE_MODE_RGMII;
566 if (priv->flags & TSEC_GIGABIT)
567 return PHY_INTERFACE_MODE_GMII;
569 return PHY_INTERFACE_MODE_MII;
573 * Discover which PHY is attached to the device, and configure it
574 * properly. If the PHY is not recognized, then return 0
575 * (failure). Otherwise, return 1
577 static int init_phy(struct eth_device *dev)
579 struct tsec_private *priv = (struct tsec_private *)dev->priv;
580 struct phy_device *phydev;
581 struct tsec __iomem *regs = priv->regs;
582 u32 supported = (SUPPORTED_10baseT_Half |
583 SUPPORTED_10baseT_Full |
584 SUPPORTED_100baseT_Half |
585 SUPPORTED_100baseT_Full);
587 if (priv->flags & TSEC_GIGABIT)
588 supported |= SUPPORTED_1000baseT_Full;
590 /* Assign a Physical address to the TBI */
591 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
593 priv->interface = tsec_get_interface(priv);
595 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
596 tsec_configure_serdes(priv);
598 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
602 phydev->supported &= supported;
603 phydev->advertising = phydev->supported;
605 priv->phydev = phydev;
613 * Initialize device structure. Returns success if PHY
614 * initialization succeeded (i.e. if it recognizes the PHY)
616 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
618 struct eth_device *dev;
620 struct tsec_private *priv;
622 dev = (struct eth_device *)malloc(sizeof *dev);
627 memset(dev, 0, sizeof *dev);
629 priv = (struct tsec_private *)malloc(sizeof(*priv));
634 priv->regs = tsec_info->regs;
635 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
637 priv->phyaddr = tsec_info->phyaddr;
638 priv->flags = tsec_info->flags;
640 sprintf(dev->name, tsec_info->devname);
641 priv->interface = tsec_info->interface;
642 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
645 dev->init = tsec_init;
646 dev->halt = tsec_halt;
647 dev->send = tsec_send;
648 dev->recv = tsec_recv;
649 #ifdef CONFIG_MCAST_TFTP
650 dev->mcast = tsec_mcast_addr;
653 /* Tell U-Boot to get the addr from the env */
654 for (i = 0; i < 6; i++)
655 dev->enetaddr[i] = 0;
660 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
661 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
662 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
664 /* Try to initialize PHY here, and return */
665 return init_phy(dev);
669 * Initialize all the TSEC devices
671 * Returns the number of TSEC devices that were initialized
673 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
678 for (i = 0; i < num; i++) {
679 ret = tsec_initialize(bis, &tsecs[i]);
687 int tsec_standard_init(bd_t *bis)
689 struct fsl_pq_mdio_info info;
691 info.regs = TSEC_GET_MDIO_REGS_BASE(1);
692 info.name = DEFAULT_MII_NAME;
694 fsl_pq_mdio_init(bis, &info);
696 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));