2 * Freescale Three Speed Ethernet Controller driver
4 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
5 * (C) Copyright 2003, Motorola, Inc.
8 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/errno.h>
19 #include <asm/processor.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 static int tsec_send(struct eth_device *dev, void *packet, int length);
26 /* Default initializations for TSEC controllers. */
28 static struct tsec_info_struct tsec_info[] = {
30 STD_TSEC_INFO(1), /* TSEC1 */
33 STD_TSEC_INFO(2), /* TSEC2 */
35 #ifdef CONFIG_MPC85XX_FEC
37 .regs = TSEC_GET_REGS(2, 0x2000),
38 .devname = CONFIG_MPC85XX_FEC_NAME,
39 .phyaddr = FEC_PHY_ADDR,
41 .mii_devname = DEFAULT_MII_NAME
45 STD_TSEC_INFO(3), /* TSEC3 */
48 STD_TSEC_INFO(4), /* TSEC4 */
52 #define TBIANA_SETTINGS ( \
53 TBIANA_ASYMMETRIC_PAUSE \
54 | TBIANA_SYMMETRIC_PAUSE \
55 | TBIANA_FULL_DUPLEX \
58 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
59 #ifndef CONFIG_TSEC_TBICR_SETTINGS
60 #define CONFIG_TSEC_TBICR_SETTINGS ( \
66 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
68 /* Configure the TBI for SGMII operation */
69 static void tsec_configure_serdes(struct tsec_private *priv)
72 * Access TBI PHY registers at given TSEC register offset as opposed
73 * to the register offset used for external PHY accesses
75 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
76 0, TBI_ANA, TBIANA_SETTINGS);
77 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
78 0, TBI_TBICON, TBICON_CLK_SELECT);
79 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
80 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
83 #ifdef CONFIG_MCAST_TFTP
85 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
87 /* Set the appropriate hash bit for the given addr */
90 * The algorithm works like so:
91 * 1) Take the Destination Address (ie the multicast address), and
92 * do a CRC on it (little endian), and reverse the bits of the
94 * 2) Use the 8 most significant bits as a hash into a 256-entry
95 * table. The table is controlled through 8 32-bit registers:
96 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
97 * 255. This means that the 3 most significant bits in the
98 * hash index which gaddr register to use, and the 5 other bits
99 * indicate which bit (assuming an IBM numbering scheme, which
100 * for PowerPC (tm) is usually the case) in the register holds
103 static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
105 struct tsec_private *priv = (struct tsec_private *)dev->priv;
106 struct tsec __iomem *regs = priv->regs;
108 u8 whichbit, whichreg;
110 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
111 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
112 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
114 value = 1 << (31-whichbit);
117 setbits_be32(®s->hash.gaddr0 + whichreg, value);
119 clrbits_be32(®s->hash.gaddr0 + whichreg, value);
123 #endif /* Multicast TFTP ? */
126 * Initialized required registers to appropriate values, zeroing
127 * those we don't care about (unless zero is bad, in which case,
128 * choose a more appropriate value)
130 static void init_registers(struct tsec __iomem *regs)
133 out_be32(®s->ievent, IEVENT_INIT_CLEAR);
135 out_be32(®s->imask, IMASK_INIT_CLEAR);
137 out_be32(®s->hash.iaddr0, 0);
138 out_be32(®s->hash.iaddr1, 0);
139 out_be32(®s->hash.iaddr2, 0);
140 out_be32(®s->hash.iaddr3, 0);
141 out_be32(®s->hash.iaddr4, 0);
142 out_be32(®s->hash.iaddr5, 0);
143 out_be32(®s->hash.iaddr6, 0);
144 out_be32(®s->hash.iaddr7, 0);
146 out_be32(®s->hash.gaddr0, 0);
147 out_be32(®s->hash.gaddr1, 0);
148 out_be32(®s->hash.gaddr2, 0);
149 out_be32(®s->hash.gaddr3, 0);
150 out_be32(®s->hash.gaddr4, 0);
151 out_be32(®s->hash.gaddr5, 0);
152 out_be32(®s->hash.gaddr6, 0);
153 out_be32(®s->hash.gaddr7, 0);
155 out_be32(®s->rctrl, 0x00000000);
157 /* Init RMON mib registers */
158 memset((void *)®s->rmon, 0, sizeof(regs->rmon));
160 out_be32(®s->rmon.cam1, 0xffffffff);
161 out_be32(®s->rmon.cam2, 0xffffffff);
163 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
165 out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
167 out_be32(®s->attr, ATTR_INIT_SETTINGS);
168 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
173 * Configure maccfg2 based on negotiated speed and duplex
174 * reported by PHY handling code
176 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
178 struct tsec __iomem *regs = priv->regs;
182 printf("%s: No link.\n", phydev->dev->name);
186 /* clear all bits relative with interface mode */
187 ecntrl = in_be32(®s->ecntrl);
188 ecntrl &= ~ECNTRL_R100;
190 maccfg2 = in_be32(®s->maccfg2);
191 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
194 maccfg2 |= MACCFG2_FULL_DUPLEX;
196 switch (phydev->speed) {
198 maccfg2 |= MACCFG2_GMII;
202 maccfg2 |= MACCFG2_MII;
205 * Set R100 bit in all modes although
206 * it is only used in RGMII mode
208 if (phydev->speed == 100)
209 ecntrl |= ECNTRL_R100;
212 printf("%s: Speed was bad\n", phydev->dev->name);
216 out_be32(®s->ecntrl, ecntrl);
217 out_be32(®s->maccfg2, maccfg2);
219 printf("Speed: %d, %s duplex%s\n", phydev->speed,
220 (phydev->duplex) ? "full" : "half",
221 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
224 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
226 * When MACCFG1[Rx_EN] is enabled during system boot as part
227 * of the eTSEC port initialization sequence,
228 * the eTSEC Rx logic may not be properly initialized.
230 void redundant_init(struct eth_device *dev)
232 struct tsec_private *priv = dev->priv;
233 struct tsec __iomem *regs = priv->regs;
236 static const u8 pkt[] = {
237 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
238 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
239 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
240 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
241 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
242 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
243 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
244 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
245 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
246 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
247 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
248 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
249 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
252 /* Enable promiscuous mode */
253 setbits_be32(®s->rctrl, 0x8);
254 /* Enable loopback mode */
255 setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
256 /* Enable transmit and receive */
257 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
259 /* Tell the DMA it is clear to go */
260 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
261 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
262 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
263 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
267 tsec_send(dev, (void *)pkt, sizeof(pkt));
269 /* Wait for buffer to be received */
271 in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
273 if (t >= 10 * TOUT_LOOP) {
274 printf("%s: tsec: rx error\n", dev->name);
279 if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
282 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
284 if ((priv->rx_idx + 1) == PKTBUFSRX)
286 out_be16(&priv->rxbd[priv->rx_idx].status, status);
287 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
289 if (in_be32(®s->ievent) & IEVENT_BSY) {
290 out_be32(®s->ievent, IEVENT_BSY);
291 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
294 printf("loopback recv packet error!\n");
295 clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
297 setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
299 } while ((count++ < 4) && (fail == 1));
302 panic("eTSEC init fail!\n");
303 /* Disable promiscuous mode */
304 clrbits_be32(®s->rctrl, 0x8);
305 /* Disable loopback mode */
306 clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
311 * Set up the buffers and their descriptors, and bring up the
314 static void startup_tsec(struct eth_device *dev)
316 struct tsec_private *priv = (struct tsec_private *)dev->priv;
317 struct tsec __iomem *regs = priv->regs;
321 /* reset the indices to zero */
324 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
328 /* Point to the buffer descriptors */
329 out_be32(®s->tbase, (u32)&priv->txbd[0]);
330 out_be32(®s->rbase, (u32)&priv->rxbd[0]);
332 /* Initialize the Rx Buffer descriptors */
333 for (i = 0; i < PKTBUFSRX; i++) {
334 out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
335 out_be16(&priv->rxbd[i].length, 0);
336 out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
338 status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
339 out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
341 /* Initialize the TX Buffer Descriptors */
342 for (i = 0; i < TX_BUF_CNT; i++) {
343 out_be16(&priv->txbd[i].status, 0);
344 out_be16(&priv->txbd[i].length, 0);
345 out_be32(&priv->txbd[i].bufptr, 0);
347 status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
348 out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
350 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
352 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
355 /* Enable Transmit and Receive */
356 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
358 /* Tell the DMA it is clear to go */
359 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
360 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
361 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
362 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
366 * This returns the status bits of the device. The return value
367 * is never checked, and this is what the 8260 driver did, so we
368 * do the same. Presumably, this would be zero if there were no
371 static int tsec_send(struct eth_device *dev, void *packet, int length)
373 struct tsec_private *priv = (struct tsec_private *)dev->priv;
374 struct tsec __iomem *regs = priv->regs;
379 /* Find an empty buffer descriptor */
381 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
383 if (i >= TOUT_LOOP) {
384 debug("%s: tsec: tx buffers full\n", dev->name);
389 out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
390 out_be16(&priv->txbd[priv->tx_idx].length, length);
391 status = in_be16(&priv->txbd[priv->tx_idx].status);
392 out_be16(&priv->txbd[priv->tx_idx].status, status |
393 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
395 /* Tell the DMA to go */
396 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
398 /* Wait for buffer to be transmitted */
400 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
402 if (i >= TOUT_LOOP) {
403 debug("%s: tsec: tx error\n", dev->name);
408 priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
409 result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
414 static int tsec_recv(struct eth_device *dev)
416 struct tsec_private *priv = (struct tsec_private *)dev->priv;
417 struct tsec __iomem *regs = priv->regs;
419 while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
420 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
421 uint16_t status = in_be16(&priv->rxbd[priv->rx_idx].status);
422 uchar *packet = net_rx_packets[priv->rx_idx];
424 /* Send the packet up if there were no errors */
425 if (!(status & RXBD_STATS))
426 net_process_received_packet(packet, length - 4);
428 printf("Got error %x\n", (status & RXBD_STATS));
430 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
433 /* Set the wrap bit if this is the last element in the list */
434 if ((priv->rx_idx + 1) == PKTBUFSRX)
436 out_be16(&priv->rxbd[priv->rx_idx].status, status);
438 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
441 if (in_be32(®s->ievent) & IEVENT_BSY) {
442 out_be32(®s->ievent, IEVENT_BSY);
443 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
449 /* Stop the interface */
450 static void tsec_halt(struct eth_device *dev)
452 struct tsec_private *priv = (struct tsec_private *)dev->priv;
453 struct tsec __iomem *regs = priv->regs;
455 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
456 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
458 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
459 != (IEVENT_GRSC | IEVENT_GTSC))
462 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
464 /* Shut down the PHY, as needed */
465 phy_shutdown(priv->phydev);
469 * Initializes data structures and registers for the controller,
470 * and brings the interface up. Returns the link status, meaning
471 * that it returns success if the link is up, failure otherwise.
472 * This allows U-Boot to find the first active controller.
474 static int tsec_init(struct eth_device *dev, bd_t * bd)
476 struct tsec_private *priv = (struct tsec_private *)dev->priv;
477 struct tsec __iomem *regs = priv->regs;
481 /* Make sure the controller is stopped */
484 /* Init MACCFG2. Defaults to GMII */
485 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
488 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
491 * Copy the station address into the address registers.
492 * For a station address of 0x12345678ABCD in transmission
493 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
494 * MACnADDR2 is set to 0x34120000.
496 tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
497 (dev->enetaddr[3] << 8) | dev->enetaddr[2];
499 out_be32(®s->macstnaddr1, tempval);
501 tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
503 out_be32(®s->macstnaddr2, tempval);
505 /* Clear out (for the most part) the other registers */
506 init_registers(regs);
508 /* Ready the device for tx/rx */
511 /* Start up the PHY */
512 ret = phy_startup(priv->phydev);
514 printf("Could not initialize PHY %s\n",
515 priv->phydev->dev->name);
519 adjust_link(priv, priv->phydev);
521 /* If there's no link, fail */
522 return priv->phydev->link ? 0 : -1;
525 static phy_interface_t tsec_get_interface(struct tsec_private *priv)
527 struct tsec __iomem *regs = priv->regs;
530 ecntrl = in_be32(®s->ecntrl);
532 if (ecntrl & ECNTRL_SGMII_MODE)
533 return PHY_INTERFACE_MODE_SGMII;
535 if (ecntrl & ECNTRL_TBI_MODE) {
536 if (ecntrl & ECNTRL_REDUCED_MODE)
537 return PHY_INTERFACE_MODE_RTBI;
539 return PHY_INTERFACE_MODE_TBI;
542 if (ecntrl & ECNTRL_REDUCED_MODE) {
543 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
544 return PHY_INTERFACE_MODE_RMII;
546 phy_interface_t interface = priv->interface;
549 * This isn't autodetected, so it must
550 * be set by the platform code.
552 if ((interface == PHY_INTERFACE_MODE_RGMII_ID) ||
553 (interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
554 (interface == PHY_INTERFACE_MODE_RGMII_RXID))
557 return PHY_INTERFACE_MODE_RGMII;
561 if (priv->flags & TSEC_GIGABIT)
562 return PHY_INTERFACE_MODE_GMII;
564 return PHY_INTERFACE_MODE_MII;
568 * Discover which PHY is attached to the device, and configure it
569 * properly. If the PHY is not recognized, then return 0
570 * (failure). Otherwise, return 1
572 static int init_phy(struct eth_device *dev)
574 struct tsec_private *priv = (struct tsec_private *)dev->priv;
575 struct phy_device *phydev;
576 struct tsec __iomem *regs = priv->regs;
577 u32 supported = (SUPPORTED_10baseT_Half |
578 SUPPORTED_10baseT_Full |
579 SUPPORTED_100baseT_Half |
580 SUPPORTED_100baseT_Full);
582 if (priv->flags & TSEC_GIGABIT)
583 supported |= SUPPORTED_1000baseT_Full;
585 /* Assign a Physical address to the TBI */
586 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
588 priv->interface = tsec_get_interface(priv);
590 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
591 tsec_configure_serdes(priv);
593 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
597 phydev->supported &= supported;
598 phydev->advertising = phydev->supported;
600 priv->phydev = phydev;
608 * Initialize device structure. Returns success if PHY
609 * initialization succeeded (i.e. if it recognizes the PHY)
611 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
613 struct eth_device *dev;
615 struct tsec_private *priv;
617 dev = (struct eth_device *)malloc(sizeof *dev);
622 memset(dev, 0, sizeof *dev);
624 priv = (struct tsec_private *)malloc(sizeof(*priv));
629 priv->regs = tsec_info->regs;
630 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
632 priv->phyaddr = tsec_info->phyaddr;
633 priv->flags = tsec_info->flags;
635 sprintf(dev->name, tsec_info->devname);
636 priv->interface = tsec_info->interface;
637 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
640 dev->init = tsec_init;
641 dev->halt = tsec_halt;
642 dev->send = tsec_send;
643 dev->recv = tsec_recv;
644 #ifdef CONFIG_MCAST_TFTP
645 dev->mcast = tsec_mcast_addr;
648 /* Tell U-Boot to get the addr from the env */
649 for (i = 0; i < 6; i++)
650 dev->enetaddr[i] = 0;
655 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
656 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
657 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
659 /* Try to initialize PHY here, and return */
660 return init_phy(dev);
664 * Initialize all the TSEC devices
666 * Returns the number of TSEC devices that were initialized
668 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
673 for (i = 0; i < num; i++) {
674 ret = tsec_initialize(bis, &tsecs[i]);
682 int tsec_standard_init(bd_t *bis)
684 struct fsl_pq_mdio_info info;
686 info.regs = TSEC_GET_MDIO_REGS_BASE(1);
687 info.name = DEFAULT_MII_NAME;
689 fsl_pq_mdio_init(bis, &info);
691 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));