4 * Driver for the Motorola Triple Speed Ethernet Controller
6 * This software may be used and distributed according to the
7 * terms of the GNU Public License, Version 2, incorporated
10 * Copyright 2004, 2007 Freescale Semiconductor, Inc.
11 * (C) Copyright 2003, Motorola, Inc.
12 * maintained by Xianghua Xiao (x.xiao@motorola.com)
23 #ifndef CFG_TSEC1_OFFSET
24 #define CFG_TSEC1_OFFSET (0x24000)
27 #define TSEC_SIZE 0x01000
29 /* FIXME: Should these be pushed back to 83xx and 85xx config files? */
30 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
31 #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET)
32 #elif defined(CONFIG_MPC83XX)
33 #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET)
37 #define MAC_ADDR_LEN 6
39 /* #define TSEC_TIMEOUT 1000000 */
40 #define TSEC_TIMEOUT 1000
41 #define TOUT_LOOP 1000000
43 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
45 /* MAC register bits */
46 #define MACCFG1_SOFT_RESET 0x80000000
47 #define MACCFG1_RESET_RX_MC 0x00080000
48 #define MACCFG1_RESET_TX_MC 0x00040000
49 #define MACCFG1_RESET_RX_FUN 0x00020000
50 #define MACCFG1_RESET_TX_FUN 0x00010000
51 #define MACCFG1_LOOPBACK 0x00000100
52 #define MACCFG1_RX_FLOW 0x00000020
53 #define MACCFG1_TX_FLOW 0x00000010
54 #define MACCFG1_SYNCD_RX_EN 0x00000008
55 #define MACCFG1_RX_EN 0x00000004
56 #define MACCFG1_SYNCD_TX_EN 0x00000002
57 #define MACCFG1_TX_EN 0x00000001
59 #define MACCFG2_INIT_SETTINGS 0x00007205
60 #define MACCFG2_FULL_DUPLEX 0x00000001
61 #define MACCFG2_IF 0x00000300
62 #define MACCFG2_GMII 0x00000200
63 #define MACCFG2_MII 0x00000100
65 #define ECNTRL_INIT_SETTINGS 0x00001000
66 #define ECNTRL_TBI_MODE 0x00000020
67 #define ECNTRL_R100 0x00000008
68 #define ECNTRL_SGMII_MODE 0x00000002
73 #ifndef CFG_TBIPA_VALUE
74 #define CFG_TBIPA_VALUE 0x1f
76 #define MIIMCFG_INIT_VALUE 0x00000003
77 #define MIIMCFG_RESET 0x80000000
79 #define MIIMIND_BUSY 0x00000001
80 #define MIIMIND_NOTVALID 0x00000004
82 #define MIIM_CONTROL 0x00
83 #define MIIM_CONTROL_RESET 0x00009140
84 #define MIIM_CONTROL_INIT 0x00001140
85 #define MIIM_CONTROL_RESTART 0x00001340
86 #define MIIM_ANEN 0x00001000
89 #define MIIM_CR_RST 0x00008000
90 #define MIIM_CR_INIT 0x00001000
92 #define MIIM_STATUS 0x1
93 #define MIIM_STATUS_AN_DONE 0x00000020
94 #define MIIM_STATUS_LINK 0x0004
95 #define PHY_BMSR_AUTN_ABLE 0x0008
96 #define PHY_BMSR_AUTN_COMP 0x0020
98 #define MIIM_PHYIR1 0x2
99 #define MIIM_PHYIR2 0x3
101 #define MIIM_ANAR 0x4
102 #define MIIM_ANAR_INIT 0x1e1
104 #define MIIM_TBI_ANLPBPA 0x5
105 #define MIIM_TBI_ANLPBPA_HALF 0x00000040
106 #define MIIM_TBI_ANLPBPA_FULL 0x00000020
108 #define MIIM_TBI_ANEX 0x6
109 #define MIIM_TBI_ANEX_NP 0x00000004
110 #define MIIM_TBI_ANEX_PRX 0x00000002
112 #define MIIM_GBIT_CONTROL 0x9
113 #define MIIM_GBIT_CONTROL_INIT 0xe00
115 #define MIIM_EXT_PAGE_ACCESS 0x1f
117 /* Broadcom BCM54xx -- taken from linux sungem_phy */
118 #define MIIM_BCM54xx_AUXSTATUS 0x19
119 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
120 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8
122 /* Cicada Auxiliary Control/Status Register */
123 #define MIIM_CIS8201_AUX_CONSTAT 0x1c
124 #define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004
125 #define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020
126 #define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018
127 #define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010
128 #define MIIM_CIS8201_AUXCONSTAT_100 0x0008
130 /* Cicada Extended Control Register 1 */
131 #define MIIM_CIS8201_EXT_CON1 0x17
132 #define MIIM_CIS8201_EXTCON1_INIT 0x0000
134 /* Cicada 8204 Extended PHY Control Register 1 */
135 #define MIIM_CIS8204_EPHY_CON 0x17
136 #define MIIM_CIS8204_EPHYCON_INIT 0x0006
137 #define MIIM_CIS8204_EPHYCON_RGMII 0x1100
139 /* Cicada 8204 Serial LED Control Register */
140 #define MIIM_CIS8204_SLED_CON 0x1b
141 #define MIIM_CIS8204_SLEDCON_INIT 0x1115
143 #define MIIM_GBIT_CON 0x09
144 #define MIIM_GBIT_CON_ADVERT 0x0e00
146 /* Entry for Vitesse VSC8244 regs starts here */
147 /* Vitesse VSC8244 Auxiliary Control/Status Register */
148 #define MIIM_VSC8244_AUX_CONSTAT 0x1c
149 #define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000
150 #define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020
151 #define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018
152 #define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010
153 #define MIIM_VSC8244_AUXCONSTAT_100 0x0008
154 #define MIIM_CONTROL_INIT_LOOPBACK 0x4000
156 /* Vitesse VSC8244 Extended PHY Control Register 1 */
157 #define MIIM_VSC8244_EPHY_CON 0x17
158 #define MIIM_VSC8244_EPHYCON_INIT 0x0006
160 /* Vitesse VSC8244 Serial LED Control Register */
161 #define MIIM_VSC8244_LED_CON 0x1b
162 #define MIIM_VSC8244_LEDCON_INIT 0xF011
164 /* Entry for Vitesse VSC8601 regs starts here (Not complete) */
165 /* Vitesse VSC8601 Extended PHY Control Register 1 */
166 #define MIIM_VSC8601_EPHY_CON 0x17
167 #define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
168 #define MIIM_VSC8601_SKEW_CTRL 0x1c
170 /* 88E1011 PHY Status Register */
171 #define MIIM_88E1011_PHY_STATUS 0x11
172 #define MIIM_88E1011_PHYSTAT_SPEED 0xc000
173 #define MIIM_88E1011_PHYSTAT_GBIT 0x8000
174 #define MIIM_88E1011_PHYSTAT_100 0x4000
175 #define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
176 #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
177 #define MIIM_88E1011_PHYSTAT_LINK 0x0400
179 #define MIIM_88E1011_PHY_SCR 0x10
180 #define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
182 /* 88E1111 PHY LED Control Register */
183 #define MIIM_88E1111_PHY_LED_CONTROL 24
184 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100
185 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C
187 /* 88E1145 Extended PHY Specific Control Register */
188 #define MIIM_88E1145_PHY_EXT_CR 20
189 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
190 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
192 #define MIIM_88E1145_PHY_PAGE 29
193 #define MIIM_88E1145_PHY_CAL_OV 30
195 /* RTL8211B PHY Status Register */
196 #define MIIM_RTL8211B_PHY_STATUS 0x11
197 #define MIIM_RTL8211B_PHYSTAT_SPEED 0xc000
198 #define MIIM_RTL8211B_PHYSTAT_GBIT 0x8000
199 #define MIIM_RTL8211B_PHYSTAT_100 0x4000
200 #define MIIM_RTL8211B_PHYSTAT_DUPLEX 0x2000
201 #define MIIM_RTL8211B_PHYSTAT_SPDDONE 0x0800
202 #define MIIM_RTL8211B_PHYSTAT_LINK 0x0400
204 /* DM9161 Control register values */
205 #define MIIM_DM9161_CR_STOP 0x0400
206 #define MIIM_DM9161_CR_RSTAN 0x1200
208 #define MIIM_DM9161_SCR 0x10
209 #define MIIM_DM9161_SCR_INIT 0x0610
211 /* DM9161 Specified Configuration and Status Register */
212 #define MIIM_DM9161_SCSR 0x11
213 #define MIIM_DM9161_SCSR_100F 0x8000
214 #define MIIM_DM9161_SCSR_100H 0x4000
215 #define MIIM_DM9161_SCSR_10F 0x2000
216 #define MIIM_DM9161_SCSR_10H 0x1000
218 /* DM9161 10BT Configuration/Status */
219 #define MIIM_DM9161_10BTCSR 0x12
220 #define MIIM_DM9161_10BTCSR_INIT 0x7800
222 /* LXT971 Status 2 registers */
223 #define MIIM_LXT971_SR2 0x11 /* Status Register 2 */
224 #define MIIM_LXT971_SR2_SPEED_MASK 0x4200
225 #define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */
226 #define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */
227 #define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
228 #define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
230 /* DP83865 Control register values */
231 #define MIIM_DP83865_CR_INIT 0x9200
233 /* DP83865 Link and Auto-Neg Status Register */
234 #define MIIM_DP83865_LANR 0x11
235 #define MIIM_DP83865_SPD_MASK 0x0018
236 #define MIIM_DP83865_SPD_1000 0x0010
237 #define MIIM_DP83865_SPD_100 0x0008
238 #define MIIM_DP83865_DPX_FULL 0x0002
240 #define MIIM_READ_COMMAND 0x00000001
242 #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
244 #define MINFLR_INIT_SETTINGS 0x00000040
246 #define DMACTRL_INIT_SETTINGS 0x000000c3
247 #define DMACTRL_GRS 0x00000010
248 #define DMACTRL_GTS 0x00000008
250 #define TSTAT_CLEAR_THALT 0x80000000
251 #define RSTAT_CLEAR_RHALT 0x00800000
254 #define IEVENT_INIT_CLEAR 0xffffffff
255 #define IEVENT_BABR 0x80000000
256 #define IEVENT_RXC 0x40000000
257 #define IEVENT_BSY 0x20000000
258 #define IEVENT_EBERR 0x10000000
259 #define IEVENT_MSRO 0x04000000
260 #define IEVENT_GTSC 0x02000000
261 #define IEVENT_BABT 0x01000000
262 #define IEVENT_TXC 0x00800000
263 #define IEVENT_TXE 0x00400000
264 #define IEVENT_TXB 0x00200000
265 #define IEVENT_TXF 0x00100000
266 #define IEVENT_IE 0x00080000
267 #define IEVENT_LC 0x00040000
268 #define IEVENT_CRL 0x00020000
269 #define IEVENT_XFUN 0x00010000
270 #define IEVENT_RXB0 0x00008000
271 #define IEVENT_GRSC 0x00000100
272 #define IEVENT_RXF0 0x00000080
274 #define IMASK_INIT_CLEAR 0x00000000
275 #define IMASK_TXEEN 0x00400000
276 #define IMASK_TXBEN 0x00200000
277 #define IMASK_TXFEN 0x00100000
278 #define IMASK_RXFEN0 0x00000080
281 /* Default Attribute fields */
282 #define ATTR_INIT_SETTINGS 0x000000c0
283 #define ATTRELI_INIT_SETTINGS 0x00000000
286 /* TxBD status field bits */
287 #define TXBD_READY 0x8000
288 #define TXBD_PADCRC 0x4000
289 #define TXBD_WRAP 0x2000
290 #define TXBD_INTERRUPT 0x1000
291 #define TXBD_LAST 0x0800
292 #define TXBD_CRC 0x0400
293 #define TXBD_DEF 0x0200
294 #define TXBD_HUGEFRAME 0x0080
295 #define TXBD_LATECOLLISION 0x0080
296 #define TXBD_RETRYLIMIT 0x0040
297 #define TXBD_RETRYCOUNTMASK 0x003c
298 #define TXBD_UNDERRUN 0x0002
299 #define TXBD_STATS 0x03ff
301 /* RxBD status field bits */
302 #define RXBD_EMPTY 0x8000
303 #define RXBD_RO1 0x4000
304 #define RXBD_WRAP 0x2000
305 #define RXBD_INTERRUPT 0x1000
306 #define RXBD_LAST 0x0800
307 #define RXBD_FIRST 0x0400
308 #define RXBD_MISS 0x0100
309 #define RXBD_BROADCAST 0x0080
310 #define RXBD_MULTICAST 0x0040
311 #define RXBD_LARGE 0x0020
312 #define RXBD_NONOCTET 0x0010
313 #define RXBD_SHORT 0x0008
314 #define RXBD_CRCERR 0x0004
315 #define RXBD_OVERRUN 0x0002
316 #define RXBD_TRUNCATED 0x0001
317 #define RXBD_STATS 0x003f
321 ushort status; /* Status Fields */
322 ushort length; /* Buffer length */
323 uint bufPtr; /* Buffer Pointer */
328 ushort status; /* Status Fields */
329 ushort length; /* Buffer Length */
330 uint bufPtr; /* Buffer Pointer */
333 typedef struct rmon_mib
335 /* Transmit and Receive Counters */
336 uint tr64; /* Transmit and Receive 64-byte Frame Counter */
337 uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */
338 uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */
339 uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */
340 uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */
341 uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */
342 uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
343 /* Receive Counters */
344 uint rbyt; /* Receive Byte Counter */
345 uint rpkt; /* Receive Packet Counter */
346 uint rfcs; /* Receive FCS Error Counter */
347 uint rmca; /* Receive Multicast Packet (Counter) */
348 uint rbca; /* Receive Broadcast Packet */
349 uint rxcf; /* Receive Control Frame Packet */
350 uint rxpf; /* Receive Pause Frame Packet */
351 uint rxuo; /* Receive Unknown OP Code */
352 uint raln; /* Receive Alignment Error */
353 uint rflr; /* Receive Frame Length Error */
354 uint rcde; /* Receive Code Error */
355 uint rcse; /* Receive Carrier Sense Error */
356 uint rund; /* Receive Undersize Packet */
357 uint rovr; /* Receive Oversize Packet */
358 uint rfrg; /* Receive Fragments */
359 uint rjbr; /* Receive Jabber */
360 uint rdrp; /* Receive Drop */
361 /* Transmit Counters */
362 uint tbyt; /* Transmit Byte Counter */
363 uint tpkt; /* Transmit Packet */
364 uint tmca; /* Transmit Multicast Packet */
365 uint tbca; /* Transmit Broadcast Packet */
366 uint txpf; /* Transmit Pause Control Frame */
367 uint tdfr; /* Transmit Deferral Packet */
368 uint tedf; /* Transmit Excessive Deferral Packet */
369 uint tscl; /* Transmit Single Collision Packet */
371 uint tmcl; /* Transmit Multiple Collision Packet */
372 uint tlcl; /* Transmit Late Collision Packet */
373 uint txcl; /* Transmit Excessive Collision Packet */
374 uint tncl; /* Transmit Total Collision */
378 uint tdrp; /* Transmit Drop Frame */
379 uint tjbr; /* Transmit Jabber Frame */
380 uint tfcs; /* Transmit FCS Error */
381 uint txcf; /* Transmit Control Frame */
382 uint tovr; /* Transmit Oversize Frame */
383 uint tund; /* Transmit Undersize Frame */
384 uint tfrg; /* Transmit Fragments Frame */
385 /* General Registers */
386 uint car1; /* Carry Register One */
387 uint car2; /* Carry Register Two */
388 uint cam1; /* Carry Register One Mask */
389 uint cam2; /* Carry Register Two Mask */
392 typedef struct tsec_hash_regs
394 uint iaddr0; /* Individual Address Register 0 */
395 uint iaddr1; /* Individual Address Register 1 */
396 uint iaddr2; /* Individual Address Register 2 */
397 uint iaddr3; /* Individual Address Register 3 */
398 uint iaddr4; /* Individual Address Register 4 */
399 uint iaddr5; /* Individual Address Register 5 */
400 uint iaddr6; /* Individual Address Register 6 */
401 uint iaddr7; /* Individual Address Register 7 */
403 uint gaddr0; /* Group Address Register 0 */
404 uint gaddr1; /* Group Address Register 1 */
405 uint gaddr2; /* Group Address Register 2 */
406 uint gaddr3; /* Group Address Register 3 */
407 uint gaddr4; /* Group Address Register 4 */
408 uint gaddr5; /* Group Address Register 5 */
409 uint gaddr6; /* Group Address Register 6 */
410 uint gaddr7; /* Group Address Register 7 */
416 /* General Control and Status Registers (0x2_n000) */
419 uint ievent; /* Interrupt Event */
420 uint imask; /* Interrupt Mask */
421 uint edis; /* Error Disabled */
423 uint ecntrl; /* Ethernet Control */
424 uint minflr; /* Minimum Frame Length */
425 uint ptv; /* Pause Time Value */
426 uint dmactrl; /* DMA Control */
427 uint tbipa; /* TBI PHY Address */
432 /* Transmit Control and Status Registers (0x2_n100) */
433 uint tctrl; /* Transmit Control */
434 uint tstat; /* Transmit Status */
436 uint tbdlen; /* Tx BD Data Length */
438 uint ctbptr; /* Current TxBD Pointer */
440 uint tbptr; /* TxBD Pointer */
444 uint tbase; /* TxBD Base Address */
446 uint ostbd; /* Out of Sequence TxBD */
447 uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
450 /* Receive Control and Status Registers (0x2_n300) */
451 uint rctrl; /* Receive Control */
452 uint rstat; /* Receive Status */
454 uint rbdlen; /* RxBD Data Length */
457 uint crbptr; /* Current Receive Buffer Pointer */
459 uint mrblr; /* Maximum Receive Buffer Length */
461 uint rbptr; /* RxBD Pointer */
465 uint rbase; /* RxBD Base Address */
468 /* MAC Registers (0x2_n500) */
469 uint maccfg1; /* MAC Configuration #1 */
470 uint maccfg2; /* MAC Configuration #2 */
471 uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */
472 uint hafdup; /* Half-duplex */
473 uint maxfrm; /* Maximum Frame */
479 uint miimcfg; /* MII Management: Configuration */
480 uint miimcom; /* MII Management: Command */
481 uint miimadd; /* MII Management: Address */
482 uint miimcon; /* MII Management: Control */
483 uint miimstat; /* MII Management: Status */
484 uint miimind; /* MII Management: Indicators */
488 uint ifstat; /* Interface Status */
489 uint macstnaddr1; /* Station Address, part 1 */
490 uint macstnaddr2; /* Station Address, part 2 */
496 /* RMON MIB Registers (0x2_n680-0x2_n73c) */
500 /* Hash Function Registers (0x2_n800) */
505 /* Pattern Registers (0x2_nb00) */
507 uint attr; /* Default Attribute Register */
508 uint attreli; /* Default Attribute Extract Length and Index */
510 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
514 #define TSEC_GIGABIT (1)
516 /* This flag currently only has
517 * meaning if we're using the eTSEC */
518 #define TSEC_REDUCED (1 << 1)
520 struct tsec_private {
521 volatile tsec_t *regs;
522 volatile tsec_t *phyregs;
523 struct phy_info *phyinfo;
533 * struct phy_cmd: A command for reading or writing a PHY register
535 * mii_reg: The register to read or write
537 * mii_data: For writes, the value to put in the register.
538 * A value of -1 indicates this is a read.
540 * funct: A function pointer which is invoked for each command.
541 * For reads, this function will be passed the value read
542 * from the PHY, and process it.
543 * For writes, the result of this function will be written
544 * to the PHY register
549 uint (*funct) (uint mii_reg, struct tsec_private* priv);
552 /* struct phy_info: a structure which defines attributes for a PHY
554 * id will contain a number which represents the PHY. During
555 * startup, the driver will poll the PHY to find out what its
556 * UID--as defined by registers 2 and 3--is. The 32-bit result
557 * gotten from the PHY will be shifted right by "shift" bits to
558 * discard any bits which may change based on revision numbers
559 * unimportant to functionality
561 * The struct phy_cmd entries represent pointers to an arrays of
562 * commands which tell the driver what to do to the PHY.
568 /* Called to configure the PHY, and modify the controller
569 * based on the results */
570 struct phy_cmd *config;
572 /* Called when starting up the controller */
573 struct phy_cmd *startup;
575 /* Called when bringing down the controller */
576 struct phy_cmd *shutdown;
579 #endif /* __TSEC_H */