1 // SPDX-License-Identifier: GPL-2.0+
2 /***********************************************************************
4 * Copyright (c) 2005 Freescale Semiconductor, Inc.
7 * Ethernet interface for Tundra TSI108 bridge chip
9 ***********************************************************************/
13 #if !defined(CONFIG_TSI108_ETH_NUM_PORTS) || (CONFIG_TSI108_ETH_NUM_PORTS > 2)
14 #error "CONFIG_TSI108_ETH_NUM_PORTS must be defined as 1 or 2"
21 #include <asm/cache.h>
24 #define TSI108_ETH_DEBUG 7
26 #define TSI108_ETH_DEBUG 0
29 #if TSI108_ETH_DEBUG > 0
30 #define debug_lev(lev, fmt, args...) \
31 if (lev <= TSI108_ETH_DEBUG) \
32 printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args)
34 #define debug_lev(lev, fmt, args...) do{}while(0)
37 #define RX_PRINT_ERRORS
38 #define TX_PRINT_ERRORS
40 #define ETH_BASE (CONFIG_SYS_TSI108_CSR_BASE + 0x6000)
42 #define ETH_PORT_OFFSET 0x400
44 #define __REG32(base, offset) (*((volatile u32 *)((char *)(base) + (offset))))
46 #define reg_MAC_CONFIG_1(base) __REG32(base, 0x00000000)
47 #define MAC_CONFIG_1_TX_ENABLE (0x00000001)
48 #define MAC_CONFIG_1_SYNC_TX_ENABLE (0x00000002)
49 #define MAC_CONFIG_1_RX_ENABLE (0x00000004)
50 #define MAC_CONFIG_1_SYNC_RX_ENABLE (0x00000008)
51 #define MAC_CONFIG_1_TX_FLOW_CONTROL (0x00000010)
52 #define MAC_CONFIG_1_RX_FLOW_CONTROL (0x00000020)
53 #define MAC_CONFIG_1_LOOP_BACK (0x00000100)
54 #define MAC_CONFIG_1_RESET_TX_FUNCTION (0x00010000)
55 #define MAC_CONFIG_1_RESET_RX_FUNCTION (0x00020000)
56 #define MAC_CONFIG_1_RESET_TX_MAC (0x00040000)
57 #define MAC_CONFIG_1_RESET_RX_MAC (0x00080000)
58 #define MAC_CONFIG_1_SIM_RESET (0x40000000)
59 #define MAC_CONFIG_1_SOFT_RESET (0x80000000)
61 #define reg_MAC_CONFIG_2(base) __REG32(base, 0x00000004)
62 #define MAC_CONFIG_2_FULL_DUPLEX (0x00000001)
63 #define MAC_CONFIG_2_CRC_ENABLE (0x00000002)
64 #define MAC_CONFIG_2_PAD_CRC (0x00000004)
65 #define MAC_CONFIG_2_LENGTH_CHECK (0x00000010)
66 #define MAC_CONFIG_2_HUGE_FRAME (0x00000020)
67 #define MAC_CONFIG_2_INTERFACE_MODE(val) (((val) & 0x3) << 8)
68 #define MAC_CONFIG_2_PREAMBLE_LENGTH(val) (((val) & 0xf) << 12)
69 #define INTERFACE_MODE_NIBBLE 1 /* 10/100 Mb/s MII) */
70 #define INTERFACE_MODE_BYTE 2 /* 1000 Mb/s GMII/TBI */
72 #define reg_MAXIMUM_FRAME_LENGTH(base) __REG32(base, 0x00000010)
74 #define reg_MII_MGMT_CONFIG(base) __REG32(base, 0x00000020)
75 #define MII_MGMT_CONFIG_MGMT_CLOCK_SELECT(val) ((val) & 0x7)
76 #define MII_MGMT_CONFIG_NO_PREAMBLE (0x00000010)
77 #define MII_MGMT_CONFIG_SCAN_INCREMENT (0x00000020)
78 #define MII_MGMT_CONFIG_RESET_MGMT (0x80000000)
80 #define reg_MII_MGMT_COMMAND(base) __REG32(base, 0x00000024)
81 #define MII_MGMT_COMMAND_READ_CYCLE (0x00000001)
82 #define MII_MGMT_COMMAND_SCAN_CYCLE (0x00000002)
84 #define reg_MII_MGMT_ADDRESS(base) __REG32(base, 0x00000028)
85 #define reg_MII_MGMT_CONTROL(base) __REG32(base, 0x0000002c)
86 #define reg_MII_MGMT_STATUS(base) __REG32(base, 0x00000030)
88 #define reg_MII_MGMT_INDICATORS(base) __REG32(base, 0x00000034)
89 #define MII_MGMT_INDICATORS_BUSY (0x00000001)
90 #define MII_MGMT_INDICATORS_SCAN (0x00000002)
91 #define MII_MGMT_INDICATORS_NOT_VALID (0x00000004)
93 #define reg_INTERFACE_STATUS(base) __REG32(base, 0x0000003c)
94 #define INTERFACE_STATUS_LINK_FAIL (0x00000008)
95 #define INTERFACE_STATUS_EXCESS_DEFER (0x00000200)
97 #define reg_STATION_ADDRESS_1(base) __REG32(base, 0x00000040)
98 #define reg_STATION_ADDRESS_2(base) __REG32(base, 0x00000044)
100 #define reg_PORT_CONTROL(base) __REG32(base, 0x00000200)
101 #define PORT_CONTROL_PRI (0x00000001)
102 #define PORT_CONTROL_BPT (0x00010000)
103 #define PORT_CONTROL_SPD (0x00040000)
104 #define PORT_CONTROL_RBC (0x00080000)
105 #define PORT_CONTROL_PRB (0x00200000)
106 #define PORT_CONTROL_DIS (0x00400000)
107 #define PORT_CONTROL_TBI (0x00800000)
108 #define PORT_CONTROL_STE (0x10000000)
109 #define PORT_CONTROL_ZOR (0x20000000)
110 #define PORT_CONTROL_CLR (0x40000000)
111 #define PORT_CONTROL_SRT (0x80000000)
113 #define reg_TX_CONFIG(base) __REG32(base, 0x00000220)
114 #define TX_CONFIG_START_Q (0x00000003)
115 #define TX_CONFIG_EHP (0x00400000)
116 #define TX_CONFIG_CHP (0x00800000)
117 #define TX_CONFIG_RST (0x80000000)
119 #define reg_TX_CONTROL(base) __REG32(base, 0x00000224)
120 #define TX_CONTROL_GO (0x00008000)
121 #define TX_CONTROL_MP (0x01000000)
122 #define TX_CONTROL_EAI (0x20000000)
123 #define TX_CONTROL_ABT (0x40000000)
124 #define TX_CONTROL_EII (0x80000000)
126 #define reg_TX_STATUS(base) __REG32(base, 0x00000228)
127 #define TX_STATUS_QUEUE_USABLE (0x0000000f)
128 #define TX_STATUS_CURR_Q (0x00000300)
129 #define TX_STATUS_ACT (0x00008000)
130 #define TX_STATUS_QUEUE_IDLE (0x000f0000)
131 #define TX_STATUS_EOQ_PENDING (0x0f000000)
133 #define reg_TX_EXTENDED_STATUS(base) __REG32(base, 0x0000022c)
134 #define TX_EXTENDED_STATUS_END_OF_QUEUE_CONDITION (0x0000000f)
135 #define TX_EXTENDED_STATUS_END_OF_FRAME_CONDITION (0x00000f00)
136 #define TX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000)
137 #define TX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000)
139 #define reg_TX_THRESHOLDS(base) __REG32(base, 0x00000230)
141 #define reg_TX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000270)
142 #define TX_DIAGNOSTIC_ADDR_INDEX (0x0000007f)
143 #define TX_DIAGNOSTIC_ADDR_DFR (0x40000000)
144 #define TX_DIAGNOSTIC_ADDR_AI (0x80000000)
146 #define reg_TX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000274)
148 #define reg_TX_ERROR_STATUS(base) __REG32(base, 0x00000278)
149 #define TX_ERROR_STATUS (0x00000278)
150 #define TX_ERROR_STATUS_QUEUE_0_ERROR_RESPONSE (0x0000000f)
151 #define TX_ERROR_STATUS_TEA_ON_QUEUE_0 (0x00000010)
152 #define TX_ERROR_STATUS_RER_ON_QUEUE_0 (0x00000020)
153 #define TX_ERROR_STATUS_TER_ON_QUEUE_0 (0x00000040)
154 #define TX_ERROR_STATUS_DER_ON_QUEUE_0 (0x00000080)
155 #define TX_ERROR_STATUS_QUEUE_1_ERROR_RESPONSE (0x00000f00)
156 #define TX_ERROR_STATUS_TEA_ON_QUEUE_1 (0x00001000)
157 #define TX_ERROR_STATUS_RER_ON_QUEUE_1 (0x00002000)
158 #define TX_ERROR_STATUS_TER_ON_QUEUE_1 (0x00004000)
159 #define TX_ERROR_STATUS_DER_ON_QUEUE_1 (0x00008000)
160 #define TX_ERROR_STATUS_QUEUE_2_ERROR_RESPONSE (0x000f0000)
161 #define TX_ERROR_STATUS_TEA_ON_QUEUE_2 (0x00100000)
162 #define TX_ERROR_STATUS_RER_ON_QUEUE_2 (0x00200000)
163 #define TX_ERROR_STATUS_TER_ON_QUEUE_2 (0x00400000)
164 #define TX_ERROR_STATUS_DER_ON_QUEUE_2 (0x00800000)
165 #define TX_ERROR_STATUS_QUEUE_3_ERROR_RESPONSE (0x0f000000)
166 #define TX_ERROR_STATUS_TEA_ON_QUEUE_3 (0x10000000)
167 #define TX_ERROR_STATUS_RER_ON_QUEUE_3 (0x20000000)
168 #define TX_ERROR_STATUS_TER_ON_QUEUE_3 (0x40000000)
169 #define TX_ERROR_STATUS_DER_ON_QUEUE_3 (0x80000000)
171 #define reg_TX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000280)
172 #define TX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f)
173 #define TX_QUEUE_0_CONFIG_BSWP (0x00000400)
174 #define TX_QUEUE_0_CONFIG_WSWP (0x00000800)
175 #define TX_QUEUE_0_CONFIG_AM (0x00004000)
176 #define TX_QUEUE_0_CONFIG_GVI (0x00008000)
177 #define TX_QUEUE_0_CONFIG_EEI (0x00010000)
178 #define TX_QUEUE_0_CONFIG_ELI (0x00020000)
179 #define TX_QUEUE_0_CONFIG_ENI (0x00040000)
180 #define TX_QUEUE_0_CONFIG_ESI (0x00080000)
181 #define TX_QUEUE_0_CONFIG_EDI (0x00100000)
183 #define reg_TX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000284)
184 #define TX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f)
185 #define TX_QUEUE_0_BUF_CONFIG_BURST (0x00000300)
186 #define TX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400)
187 #define TX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800)
189 #define OCN_PORT_HLP 0 /* HLP Interface */
190 #define OCN_PORT_PCI_X 1 /* PCI-X Interface */
191 #define OCN_PORT_PROCESSOR_MASTER 2 /* Processor Interface (master) */
192 #define OCN_PORT_PROCESSOR_SLAVE 3 /* Processor Interface (slave) */
193 #define OCN_PORT_MEMORY 4 /* Memory Controller */
194 #define OCN_PORT_DMA 5 /* DMA Controller */
195 #define OCN_PORT_ETHERNET 6 /* Ethernet Controller */
196 #define OCN_PORT_PRINT 7 /* Print Engine Interface */
198 #define reg_TX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000288)
200 #define reg_TX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000028c)
201 #define TX_QUEUE_0_PTR_HIGH_VALID (0x80000000)
203 #define reg_RX_CONFIG(base) __REG32(base, 0x00000320)
204 #define RX_CONFIG_DEF_Q (0x00000003)
205 #define RX_CONFIG_EMF (0x00000100)
206 #define RX_CONFIG_EUF (0x00000200)
207 #define RX_CONFIG_BFE (0x00000400)
208 #define RX_CONFIG_MFE (0x00000800)
209 #define RX_CONFIG_UFE (0x00001000)
210 #define RX_CONFIG_SE (0x00002000)
211 #define RX_CONFIG_ABF (0x00200000)
212 #define RX_CONFIG_APE (0x00400000)
213 #define RX_CONFIG_CHP (0x00800000)
214 #define RX_CONFIG_RST (0x80000000)
216 #define reg_RX_CONTROL(base) __REG32(base, 0x00000324)
217 #define GE_E0_RX_CONTROL_QUEUE_ENABLES (0x0000000f)
218 #define GE_E0_RX_CONTROL_GO (0x00008000)
219 #define GE_E0_RX_CONTROL_EAI (0x20000000)
220 #define GE_E0_RX_CONTROL_ABT (0x40000000)
221 #define GE_E0_RX_CONTROL_EII (0x80000000)
223 #define reg_RX_EXTENDED_STATUS(base) __REG32(base, 0x0000032c)
224 #define RX_EXTENDED_STATUS (0x0000032c)
225 #define RX_EXTENDED_STATUS_EOQ (0x0000000f)
226 #define RX_EXTENDED_STATUS_EOQ_0 (0x00000001)
227 #define RX_EXTENDED_STATUS_EOF (0x00000f00)
228 #define RX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000)
229 #define RX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000)
231 #define reg_RX_THRESHOLDS(base) __REG32(base, 0x00000330)
233 #define reg_RX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000370)
234 #define RX_DIAGNOSTIC_ADDR_INDEX (0x0000007f)
235 #define RX_DIAGNOSTIC_ADDR_DFR (0x40000000)
236 #define RX_DIAGNOSTIC_ADDR_AI (0x80000000)
238 #define reg_RX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000374)
240 #define reg_RX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000380)
241 #define RX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f)
242 #define RX_QUEUE_0_CONFIG_BSWP (0x00000400)
243 #define RX_QUEUE_0_CONFIG_WSWP (0x00000800)
244 #define RX_QUEUE_0_CONFIG_AM (0x00004000)
245 #define RX_QUEUE_0_CONFIG_EEI (0x00010000)
246 #define RX_QUEUE_0_CONFIG_ELI (0x00020000)
247 #define RX_QUEUE_0_CONFIG_ENI (0x00040000)
248 #define RX_QUEUE_0_CONFIG_ESI (0x00080000)
249 #define RX_QUEUE_0_CONFIG_EDI (0x00100000)
251 #define reg_RX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000384)
252 #define RX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f)
253 #define RX_QUEUE_0_BUF_CONFIG_BURST (0x00000300)
254 #define RX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400)
255 #define RX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800)
257 #define reg_RX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000388)
259 #define reg_RX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000038c)
260 #define RX_QUEUE_0_PTR_HIGH_VALID (0x80000000)
263 * PHY register definitions
265 /* the first 15 PHY registers are standard. */
266 #define PHY_CTRL_REG 0 /* Control Register */
267 #define PHY_STATUS_REG 1 /* Status Regiser */
268 #define PHY_ID1_REG 2 /* Phy Id Reg (word 1) */
269 #define PHY_ID2_REG 3 /* Phy Id Reg (word 2) */
270 #define PHY_AN_ADV_REG 4 /* Autoneg Advertisement */
271 #define PHY_LP_ABILITY_REG 5 /* Link Partner Ability (Base Page) */
272 #define PHY_AUTONEG_EXP_REG 6 /* Autoneg Expansion Reg */
273 #define PHY_NEXT_PAGE_TX_REG 7 /* Next Page TX */
274 #define PHY_LP_NEXT_PAGE_REG 8 /* Link Partner Next Page */
275 #define PHY_1000T_CTRL_REG 9 /* 1000Base-T Control Reg */
276 #define PHY_1000T_STATUS_REG 10 /* 1000Base-T Status Reg */
277 #define PHY_EXT_STATUS_REG 11 /* Extended Status Reg */
280 * PHY Register bit masks.
282 #define PHY_CTRL_RESET (1 << 15)
283 #define PHY_CTRL_LOOPBACK (1 << 14)
284 #define PHY_CTRL_SPEED0 (1 << 13)
285 #define PHY_CTRL_AN_EN (1 << 12)
286 #define PHY_CTRL_PWR_DN (1 << 11)
287 #define PHY_CTRL_ISOLATE (1 << 10)
288 #define PHY_CTRL_RESTART_AN (1 << 9)
289 #define PHY_CTRL_FULL_DUPLEX (1 << 8)
290 #define PHY_CTRL_CT_EN (1 << 7)
291 #define PHY_CTRL_SPEED1 (1 << 6)
293 #define PHY_STAT_100BASE_T4 (1 << 15)
294 #define PHY_STAT_100BASE_X_FD (1 << 14)
295 #define PHY_STAT_100BASE_X_HD (1 << 13)
296 #define PHY_STAT_10BASE_T_FD (1 << 12)
297 #define PHY_STAT_10BASE_T_HD (1 << 11)
298 #define PHY_STAT_100BASE_T2_FD (1 << 10)
299 #define PHY_STAT_100BASE_T2_HD (1 << 9)
300 #define PHY_STAT_EXT_STAT (1 << 8)
301 #define PHY_STAT_RESERVED (1 << 7)
302 #define PHY_STAT_MFPS (1 << 6) /* Management Frames Preamble Suppression */
303 #define PHY_STAT_AN_COMPLETE (1 << 5)
304 #define PHY_STAT_REM_FAULT (1 << 4)
305 #define PHY_STAT_AN_CAP (1 << 3)
306 #define PHY_STAT_LINK_UP (1 << 2)
307 #define PHY_STAT_JABBER (1 << 1)
308 #define PHY_STAT_EXT_CAP (1 << 0)
310 #define TBI_CONTROL_2 0x11
311 #define TBI_CONTROL_2_ENABLE_COMMA_DETECT 0x0001
312 #define TBI_CONTROL_2_ENABLE_WRAP 0x0002
313 #define TBI_CONTROL_2_G_MII_MODE 0x0010
314 #define TBI_CONTROL_2_RECEIVE_CLOCK_SELECT 0x0020
315 #define TBI_CONTROL_2_AUTO_NEGOTIATION_SENSE 0x0100
316 #define TBI_CONTROL_2_DISABLE_TRANSMIT_RUNNING_DISPARITY 0x1000
317 #define TBI_CONTROL_2_DISABLE_RECEIVE_RUNNING_DISPARITY 0x2000
318 #define TBI_CONTROL_2_SHORTCUT_LINK_TIMER 0x4000
319 #define TBI_CONTROL_2_SOFT_RESET 0x8000
321 /* marvel specific */
322 #define MV1111_EXT_CTRL1_REG 16 /* PHY Specific Control Reg */
323 #define MV1111_SPEC_STAT_REG 17 /* PHY Specific Status Reg */
324 #define MV1111_EXT_CTRL2_REG 20 /* Extended PHY Specific Control Reg */
327 * MARVELL 88E1111 PHY register bit masks
329 /* PHY Specific Status Register (MV1111_EXT_CTRL1_REG) */
331 #define SPEC_STAT_SPEED_MASK (3 << 14)
332 #define SPEC_STAT_FULL_DUP (1 << 13)
333 #define SPEC_STAT_PAGE_RCVD (1 << 12)
334 #define SPEC_STAT_RESOLVED (1 << 11) /* Speed and Duplex Resolved */
335 #define SPEC_STAT_LINK_UP (1 << 10)
336 #define SPEC_STAT_CABLE_LEN_MASK (7 << 7)/* Cable Length (100/1000 modes only) */
337 #define SPEC_STAT_MDIX (1 << 6)
338 #define SPEC_STAT_POLARITY (1 << 1)
339 #define SPEC_STAT_JABBER (1 << 0)
341 #define SPEED_1000 (2 << 14)
342 #define SPEED_100 (1 << 14)
343 #define SPEED_10 (0 << 14)
345 #define TBI_ADDR 0x1E /* Ten Bit Interface address */
347 /* negotiated link parameters */
348 #define LINK_SPEED_UNKNOWN 0
349 #define LINK_SPEED_10 1
350 #define LINK_SPEED_100 2
351 #define LINK_SPEED_1000 3
353 #define LINK_DUPLEX_UNKNOWN 0
354 #define LINK_DUPLEX_HALF 1
355 #define LINK_DUPLEX_FULL 2
357 static unsigned int phy_address[] = { 8, 9 };
359 #define vuint32 volatile u32
361 /* TX/RX buffer descriptors. MUST be cache line aligned in memory. (32 byte)
362 * This structure is accessed by the ethernet DMA engine which means it
363 * MUST be in LITTLE ENDIAN format */
364 struct dma_descriptor {
365 vuint32 start_addr0; /* buffer address, least significant bytes. */
366 vuint32 start_addr1; /* buffer address, most significant bytes. */
367 vuint32 next_descr_addr0;/* next descriptor address, least significant bytes. Must be 64-bit aligned. */
368 vuint32 next_descr_addr1;/* next descriptor address, most significant bytes. */
369 vuint32 vlan_byte_count;/* VLAN tag(top 2 bytes) and byte countt (bottom 2 bytes). */
370 vuint32 config_status; /* Configuration/Status. */
371 vuint32 reserved1; /* reserved to make the descriptor cache line aligned. */
372 vuint32 reserved2; /* reserved to make the descriptor cache line aligned. */
375 /* last next descriptor address flag */
376 #define DMA_DESCR_LAST (1 << 31)
378 /* TX DMA descriptor config status bits */
379 #define DMA_DESCR_TX_EOF (1 << 0) /* end of frame */
380 #define DMA_DESCR_TX_SOF (1 << 1) /* start of frame */
381 #define DMA_DESCR_TX_PFVLAN (1 << 2)
382 #define DMA_DESCR_TX_HUGE (1 << 3)
383 #define DMA_DESCR_TX_PAD (1 << 4)
384 #define DMA_DESCR_TX_CRC (1 << 5)
385 #define DMA_DESCR_TX_DESCR_INT (1 << 14)
386 #define DMA_DESCR_TX_RETRY_COUNT 0x000F0000
387 #define DMA_DESCR_TX_ONE_COLLISION (1 << 20)
388 #define DMA_DESCR_TX_LATE_COLLISION (1 << 24)
389 #define DMA_DESCR_TX_UNDERRUN (1 << 25)
390 #define DMA_DESCR_TX_RETRY_LIMIT (1 << 26)
391 #define DMA_DESCR_TX_OK (1 << 30)
392 #define DMA_DESCR_TX_OWNER (1 << 31)
394 /* RX DMA descriptor status bits */
395 #define DMA_DESCR_RX_EOF (1 << 0)
396 #define DMA_DESCR_RX_SOF (1 << 1)
397 #define DMA_DESCR_RX_VTF (1 << 2)
398 #define DMA_DESCR_RX_FRAME_IS_TYPE (1 << 3)
399 #define DMA_DESCR_RX_SHORT_FRAME (1 << 4)
400 #define DMA_DESCR_RX_HASH_MATCH (1 << 7)
401 #define DMA_DESCR_RX_BAD_FRAME (1 << 8)
402 #define DMA_DESCR_RX_OVERRUN (1 << 9)
403 #define DMA_DESCR_RX_MAX_FRAME_LEN (1 << 11)
404 #define DMA_DESCR_RX_CRC_ERROR (1 << 12)
405 #define DMA_DESCR_RX_DESCR_INT (1 << 13)
406 #define DMA_DESCR_RX_OWNER (1 << 15)
408 #define RX_BUFFER_SIZE PKTSIZE
409 #define NUM_RX_DESC PKTBUFSRX
411 static struct dma_descriptor tx_descriptor __attribute__ ((aligned(32)));
413 static struct dma_descriptor rx_descr_array[NUM_RX_DESC]
414 __attribute__ ((aligned(32)));
416 static struct dma_descriptor *rx_descr_current;
418 static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis);
419 static int tsi108_eth_send(struct eth_device *dev, void *packet, int length);
420 static int tsi108_eth_recv (struct eth_device *dev);
421 static void tsi108_eth_halt (struct eth_device *dev);
422 static unsigned int read_phy (unsigned int base,
423 unsigned int phy_addr, unsigned int phy_reg);
424 static void write_phy (unsigned int base,
425 unsigned int phy_addr,
426 unsigned int phy_reg, unsigned int phy_data);
428 #if TSI108_ETH_DEBUG > 100
430 * print phy debug infomation
432 static void dump_phy_regs (unsigned int phy_addr)
436 printf ("PHY %d registers\n", phy_addr);
437 for (i = 0; i <= 30; i++) {
438 printf ("%2d 0x%04x\n", i, read_phy (ETH_BASE, phy_addr, i));
444 #define dump_phy_regs(base) do{}while(0)
447 #if TSI108_ETH_DEBUG > 100
449 * print debug infomation
451 static void tx_diag_regs (unsigned int base)
456 printf ("TX diagnostics registers\n");
457 reg_TX_DIAGNOSTIC_ADDR(base) = 0x00 | TX_DIAGNOSTIC_ADDR_AI;
459 dummy = reg_TX_DIAGNOSTIC_DATA(base);
460 for (i = 0x00; i <= 0x05; i++) {
462 printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base));
464 reg_TX_DIAGNOSTIC_ADDR(base) = 0x40 | TX_DIAGNOSTIC_ADDR_AI;
466 dummy = reg_TX_DIAGNOSTIC_DATA(base);
467 for (i = 0x40; i <= 0x47; i++) {
469 printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base));
475 #define tx_diag_regs(base) do{}while(0)
478 #if TSI108_ETH_DEBUG > 100
480 * print debug infomation
482 static void rx_diag_regs (unsigned int base)
487 printf ("RX diagnostics registers\n");
488 reg_RX_DIAGNOSTIC_ADDR(base) = 0x00 | RX_DIAGNOSTIC_ADDR_AI;
490 dummy = reg_RX_DIAGNOSTIC_DATA(base);
491 for (i = 0x00; i <= 0x05; i++) {
493 printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base));
495 reg_RX_DIAGNOSTIC_ADDR(base) = 0x40 | RX_DIAGNOSTIC_ADDR_AI;
497 dummy = reg_RX_DIAGNOSTIC_DATA(base);
498 for (i = 0x08; i <= 0x0a; i++) {
500 printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base));
506 #define rx_diag_regs(base) do{}while(0)
509 #if TSI108_ETH_DEBUG > 100
511 * print debug infomation
513 static void debug_mii_regs (unsigned int base)
515 printf ("MII_MGMT_CONFIG 0x%08x\n", reg_MII_MGMT_CONFIG(base));
516 printf ("MII_MGMT_COMMAND 0x%08x\n", reg_MII_MGMT_COMMAND(base));
517 printf ("MII_MGMT_ADDRESS 0x%08x\n", reg_MII_MGMT_ADDRESS(base));
518 printf ("MII_MGMT_CONTROL 0x%08x\n", reg_MII_MGMT_CONTROL(base));
519 printf ("MII_MGMT_STATUS 0x%08x\n", reg_MII_MGMT_STATUS(base));
520 printf ("MII_MGMT_INDICATORS 0x%08x\n", reg_MII_MGMT_INDICATORS(base));
525 #define debug_mii_regs(base) do{}while(0)
529 * Wait until the phy bus is non-busy
531 static void phy_wait (unsigned int base, unsigned int condition)
536 while (reg_MII_MGMT_INDICATORS(base) & condition) {
538 if (++timeout > 10000) {
539 printf ("ERROR: timeout waiting for phy bus (%d)\n",
549 static unsigned int read_phy (unsigned int base,
550 unsigned int phy_addr, unsigned int phy_reg)
554 phy_wait (base, MII_MGMT_INDICATORS_BUSY);
556 reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg;
558 /* Ensure that the Read Cycle bit is cleared prior to next read cycle */
559 reg_MII_MGMT_COMMAND(base) = 0;
562 reg_MII_MGMT_COMMAND(base) = MII_MGMT_COMMAND_READ_CYCLE;
564 /* wait for the read to complete */
566 MII_MGMT_INDICATORS_NOT_VALID | MII_MGMT_INDICATORS_BUSY);
568 value = reg_MII_MGMT_STATUS(base);
570 reg_MII_MGMT_COMMAND(base) = 0;
578 static void write_phy (unsigned int base,
579 unsigned int phy_addr,
580 unsigned int phy_reg, unsigned int phy_data)
582 phy_wait (base, MII_MGMT_INDICATORS_BUSY);
584 reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg;
586 /* Ensure that the Read Cycle bit is cleared prior to next cycle */
587 reg_MII_MGMT_COMMAND(base) = 0;
589 /* start the write */
590 reg_MII_MGMT_CONTROL(base) = phy_data;
594 * configure the marvell 88e1111 phy
596 static int marvell_88e_phy_config (struct eth_device *dev, int *speed,
600 unsigned long phy_addr;
601 unsigned int phy_status;
602 unsigned int phy_spec_status;
608 phy_speed = LINK_SPEED_UNKNOWN;
609 phy_duplex = LINK_DUPLEX_UNKNOWN;
612 phy_addr = (unsigned long)dev->priv;
614 /* Take the PHY out of reset. */
615 write_phy (ETH_BASE, phy_addr, PHY_CTRL_REG, PHY_CTRL_RESET);
617 /* Wait for the reset process to complete. */
621 read_phy (ETH_BASE, phy_addr, PHY_CTRL_REG)) & PHY_CTRL_RESET) {
623 if (++timeout > 10000) {
624 printf ("ERROR: timeout waiting for phy reset\n");
629 /* TBI Configuration. */
630 write_phy (base, TBI_ADDR, TBI_CONTROL_2, TBI_CONTROL_2_G_MII_MODE |
631 TBI_CONTROL_2_RECEIVE_CLOCK_SELECT);
632 /* Wait for the link to be established. */
636 phy_status = read_phy (ETH_BASE, phy_addr, PHY_STATUS_REG);
637 if (++timeout > 100) {
638 debug_lev(1, "ERROR: unable to establish link!!!\n");
641 } while ((phy_status & PHY_STAT_LINK_UP) == 0);
643 if ((phy_status & PHY_STAT_LINK_UP) == 0)
647 phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
648 if (phy_spec_status & SPEC_STAT_RESOLVED) {
649 switch (phy_spec_status & SPEC_STAT_SPEED_MASK) {
651 phy_speed = LINK_SPEED_1000;
652 value |= PHY_CTRL_SPEED1;
655 phy_speed = LINK_SPEED_100;
656 value |= PHY_CTRL_SPEED0;
659 phy_speed = LINK_SPEED_10;
662 if (phy_spec_status & SPEC_STAT_FULL_DUP) {
663 phy_duplex = LINK_DUPLEX_FULL;
664 value |= PHY_CTRL_FULL_DUPLEX;
666 phy_duplex = LINK_DUPLEX_HALF;
669 write_phy (base, TBI_ADDR, PHY_CTRL_REG, value);
670 write_phy (base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060);
672 #if TSI108_ETH_DEBUG > 0
673 printf ("%s link is up", dev->name);
674 phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
675 if (phy_spec_status & SPEC_STAT_RESOLVED) {
677 case LINK_SPEED_1000:
678 printf (", 1000 Mbps");
681 printf (", 100 Mbps");
684 printf (", 10 Mbps");
687 if (phy_duplex == LINK_DUPLEX_FULL)
688 printf (", Full duplex");
690 printf (", Half duplex");
695 dump_phy_regs (TBI_ADDR);
699 *duplex = phy_duplex;
707 * register the tsi108 ethernet controllers with the multi-ethernet system
709 int tsi108_eth_initialize (bd_t * bis)
711 struct eth_device *dev;
714 for (index = 0; index < CONFIG_TSI108_ETH_NUM_PORTS; index++) {
715 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
717 printf("tsi108: Can not allocate memory\n");
720 memset(dev, 0, sizeof(*dev));
721 sprintf (dev->name, "TSI108_eth%d", index);
723 dev->iobase = ETH_BASE + (index * ETH_PORT_OFFSET);
724 dev->priv = (void *)(phy_address[index]);
725 dev->init = tsi108_eth_probe;
726 dev->halt = tsi108_eth_halt;
727 dev->send = tsi108_eth_send;
728 dev->recv = tsi108_eth_recv;
736 * probe for and initialize a single ethernet interface
738 static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis)
743 struct dma_descriptor *tx_descr;
744 struct dma_descriptor *rx_descr;
750 reg_PORT_CONTROL(base) = PORT_CONTROL_STE | PORT_CONTROL_BPT;
752 /* Bring DMA/FIFO out of reset. */
753 reg_TX_CONFIG(base) = 0x00000000;
754 reg_RX_CONFIG(base) = 0x00000000;
756 reg_TX_THRESHOLDS(base) = (192 << 16) | 192;
757 reg_RX_THRESHOLDS(base) = (192 << 16) | 112;
759 /* Bring MAC out of reset. */
760 reg_MAC_CONFIG_1(base) = 0x00000000;
762 /* DMA MAC configuration. */
763 reg_MAC_CONFIG_1(base) =
764 MAC_CONFIG_1_RX_ENABLE | MAC_CONFIG_1_TX_ENABLE;
766 reg_MII_MGMT_CONFIG(base) = MII_MGMT_CONFIG_NO_PREAMBLE;
767 reg_MAXIMUM_FRAME_LENGTH(base) = RX_BUFFER_SIZE;
769 /* Note: Early tsi108 manual did not have correct byte order
770 * for the station address.*/
771 reg_STATION_ADDRESS_1(base) = (dev->enetaddr[5] << 24) |
772 (dev->enetaddr[4] << 16) |
773 (dev->enetaddr[3] << 8) | (dev->enetaddr[2] << 0);
775 reg_STATION_ADDRESS_2(base) = (dev->enetaddr[1] << 24) |
776 (dev->enetaddr[0] << 16);
778 if (marvell_88e_phy_config(dev, &speed, &duplex) == 0)
782 MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC |
783 MAC_CONFIG_2_CRC_ENABLE;
784 if (speed == LINK_SPEED_1000)
785 value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_BYTE);
787 value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_NIBBLE);
788 reg_PORT_CONTROL(base) |= PORT_CONTROL_SPD;
790 if (duplex == LINK_DUPLEX_FULL) {
791 value |= MAC_CONFIG_2_FULL_DUPLEX;
792 reg_PORT_CONTROL(base) &= ~PORT_CONTROL_BPT;
794 reg_PORT_CONTROL(base) |= PORT_CONTROL_BPT;
795 reg_MAC_CONFIG_2(base) = value;
797 reg_RX_CONFIG(base) = RX_CONFIG_SE;
798 reg_RX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY;
799 reg_RX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY;
801 /* initialize the RX DMA descriptors */
802 rx_descr = &rx_descr_array[0];
803 rx_descr_current = rx_descr;
804 for (index = 0; index < NUM_RX_DESC; index++) {
805 /* make sure the receive buffers are not in cache */
806 invalidate_dcache_range((unsigned long)net_rx_packets[index],
807 (unsigned long)net_rx_packets[index] +
809 rx_descr->start_addr0 =
810 cpu_to_le32((vuint32) net_rx_packets[index]);
811 rx_descr->start_addr1 = 0;
812 rx_descr->next_descr_addr0 =
813 cpu_to_le32((vuint32) (rx_descr + 1));
814 rx_descr->next_descr_addr1 = 0;
815 rx_descr->vlan_byte_count = 0;
816 rx_descr->config_status = cpu_to_le32((RX_BUFFER_SIZE << 16) |
821 rx_descr->next_descr_addr0 = 0;
822 rx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
823 /* Push the descriptors to RAM so the ethernet DMA can see them */
824 invalidate_dcache_range((unsigned long)rx_descr_array,
825 (unsigned long)rx_descr_array +
826 sizeof(rx_descr_array));
828 /* enable RX queue */
829 reg_RX_CONTROL(base) = TX_CONTROL_GO | 0x01;
830 reg_RX_QUEUE_0_PTR_LOW(base) = (u32) rx_descr_current;
831 /* enable receive DMA */
832 reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID;
834 reg_TX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY;
835 reg_TX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY;
837 /* initialize the TX DMA descriptor */
838 tx_descr = &tx_descriptor;
840 tx_descr->start_addr0 = 0;
841 tx_descr->start_addr1 = 0;
842 tx_descr->next_descr_addr0 = 0;
843 tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
844 tx_descr->vlan_byte_count = 0;
845 tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OK |
848 /* enable TX queue */
849 reg_TX_CONTROL(base) = TX_CONTROL_GO | 0x01;
857 static int tsi108_eth_send(struct eth_device *dev, void *packet, int length)
861 struct dma_descriptor *tx_descr;
862 unsigned long status;
865 tx_descr = &tx_descriptor;
867 /* Wait until the last packet has been transmitted. */
870 /* make sure we see the changes made by the DMA engine */
871 invalidate_dcache_range((unsigned long)tx_descr,
872 (unsigned long)tx_descr +
873 sizeof(struct dma_descriptor));
877 if (++timeout > 10000) {
880 "ERROR: timeout waiting for last transmit packet to be sent\n");
883 } while (tx_descr->config_status & cpu_to_le32(DMA_DESCR_TX_OWNER));
885 status = le32_to_cpu(tx_descr->config_status);
886 if ((status & DMA_DESCR_TX_OK) == 0) {
887 #ifdef TX_PRINT_ERRORS
888 printf ("TX packet error: 0x%08lx\n %s%s%s%s\n", status,
889 status & DMA_DESCR_TX_OK ? "tx error, " : "",
890 status & DMA_DESCR_TX_RETRY_LIMIT ?
891 "retry limit reached, " : "",
892 status & DMA_DESCR_TX_UNDERRUN ? "underrun, " : "",
893 status & DMA_DESCR_TX_LATE_COLLISION ? "late collision, "
898 debug_lev (9, "sending packet %d\n", length);
899 tx_descr->start_addr0 = cpu_to_le32((vuint32) packet);
900 tx_descr->start_addr1 = 0;
901 tx_descr->next_descr_addr0 = 0;
902 tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
903 tx_descr->vlan_byte_count = cpu_to_le32(length);
904 tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OWNER |
910 invalidate_dcache_range((unsigned long)tx_descr,
911 (unsigned long)tx_descr +
912 sizeof(struct dma_descriptor));
914 invalidate_dcache_range((unsigned long)packet,
915 (unsigned long)packet + length);
917 reg_TX_QUEUE_0_PTR_LOW(base) = (u32) tx_descr;
918 reg_TX_QUEUE_0_PTR_HIGH(base) = TX_QUEUE_0_PTR_HIGH_VALID;
924 * Check for received packets and send them up the protocal stack
926 static int tsi108_eth_recv (struct eth_device *dev)
928 struct dma_descriptor *rx_descr;
931 unsigned long status;
936 /* make sure we see the changes made by the DMA engine */
937 invalidate_dcache_range ((unsigned long)rx_descr_array,
938 (unsigned long)rx_descr_array +
939 sizeof(rx_descr_array));
941 /* process all of the received packets */
942 rx_descr = rx_descr_current;
943 while ((rx_descr->config_status & cpu_to_le32(DMA_DESCR_RX_OWNER)) == 0) {
944 /* check for error */
945 status = le32_to_cpu(rx_descr->config_status);
946 if (status & DMA_DESCR_RX_BAD_FRAME) {
947 #ifdef RX_PRINT_ERRORS
948 printf ("RX packet error: 0x%08lx\n %s%s%s%s%s%s\n",
950 status & DMA_DESCR_RX_FRAME_IS_TYPE ? "too big, "
952 status & DMA_DESCR_RX_SHORT_FRAME ? "too short, "
954 status & DMA_DESCR_RX_BAD_FRAME ? "bad frame, " :
956 status & DMA_DESCR_RX_OVERRUN ? "overrun, " : "",
957 status & DMA_DESCR_RX_MAX_FRAME_LEN ?
959 status & DMA_DESCR_RX_CRC_ERROR ? "CRC error, " :
964 le32_to_cpu(rx_descr->vlan_byte_count) & 0xFFFF;
966 /*** process packet ***/
967 buffer = (uchar *)(le32_to_cpu(rx_descr->start_addr0));
968 net_process_received_packet(buffer, length);
970 invalidate_dcache_range ((unsigned long)buffer,
971 (unsigned long)buffer +
974 /* Give this buffer back to the DMA engine */
975 rx_descr->vlan_byte_count = 0;
976 rx_descr->config_status = cpu_to_le32 ((RX_BUFFER_SIZE << 16) |
978 /* move descriptor pointer forward */
980 (struct dma_descriptor
981 *)(le32_to_cpu (rx_descr->next_descr_addr0));
983 rx_descr = &rx_descr_array[0];
985 /* remember where we are for next time */
986 rx_descr_current = rx_descr;
988 /* If the DMA engine has reached the end of the queue
989 * start over at the begining */
990 if (reg_RX_EXTENDED_STATUS(base) & RX_EXTENDED_STATUS_EOQ_0) {
992 reg_RX_EXTENDED_STATUS(base) = RX_EXTENDED_STATUS_EOQ_0;
993 reg_RX_QUEUE_0_PTR_LOW(base) = (u32) & rx_descr_array[0];
994 reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID;
1001 * disable an ethernet interface
1003 static void tsi108_eth_halt (struct eth_device *dev)
1009 /* Put DMA/FIFO into reset state. */
1010 reg_TX_CONFIG(base) = TX_CONFIG_RST;
1011 reg_RX_CONFIG(base) = RX_CONFIG_RST;
1013 /* Put MAC into reset state. */
1014 reg_MAC_CONFIG_1(base) = MAC_CONFIG_1_SOFT_RESET;