2 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2011 PetaLogix
4 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
6 * SPDX-License-Identifier: GPL-2.0+
19 DECLARE_GLOBAL_DATA_PTR;
22 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
23 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
24 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
25 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
27 /* Interrupt Status/Enable/Mask Registers bit definitions */
28 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
29 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
31 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
32 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
34 /* Transmitter Configuration (TC) Register bit definitions */
35 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
37 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
39 /* MDIO Management Configuration (MC) Register bit definitions */
40 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
42 /* MDIO Management Control Register (MCR) Register bit definitions */
43 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
44 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
45 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
46 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
47 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
48 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
49 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
50 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
52 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
55 /* Bitmasks of XAXIDMA_CR_OFFSET register */
56 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
57 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
59 /* Bitmasks of XAXIDMA_SR_OFFSET register */
60 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
62 /* Bitmask for interrupts */
63 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
64 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
65 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
67 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
68 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
69 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
73 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
75 /* Reflect dma offsets */
77 u32 control; /* DMACR */
78 u32 status; /* DMASR */
79 u32 current; /* CURDESC */
81 u32 tail; /* TAILDESC */
84 /* Private driver structures */
86 struct axidma_reg *dmatx;
87 struct axidma_reg *dmarx;
89 struct axi_regs *iobase;
90 phy_interface_t interface;
91 struct phy_device *phydev;
97 u32 next; /* Next descriptor pointer */
99 u32 phys; /* Buffer address */
103 u32 cntrl; /* Control */
104 u32 status; /* Status */
106 u32 app1; /* TX start << 16 | insert */
107 u32 app2; /* TX csum seed */
115 /* Static BDs - driver uses only one BD */
116 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
117 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
121 u32 is; /* 0xC: Interrupt status */
123 u32 ie; /* 0x14: Interrupt enable */
125 u32 rcw1; /* 0x404: Rx Configuration Word 1 */
126 u32 tc; /* 0x408: Tx Configuration */
128 u32 emmc; /* 0x410: EMAC mode configuration */
130 u32 mdio_mc; /* 0x500: MII Management Config */
131 u32 mdio_mcr; /* 0x504: MII Management Control */
132 u32 mdio_mwd; /* 0x508: MII Management Write Data */
133 u32 mdio_mrd; /* 0x50C: MII Management Read Data */
135 u32 uaw0; /* 0x700: Unicast address word 0 */
136 u32 uaw1; /* 0x704: Unicast address word 1 */
139 /* Use MII register 1 (MII status register) to detect PHY */
140 #define PHY_DETECT_REG 1
143 * Mask used to verify certain PHY features (or register contents)
144 * in the register above:
145 * 0x1000: 10Mbps full duplex support
146 * 0x0800: 10Mbps half duplex support
147 * 0x0008: Auto-negotiation support
149 #define PHY_DETECT_MASK 0x1808
151 static inline int mdio_wait(struct axi_regs *regs)
155 /* Wait till MDIO interface is ready to accept a new transaction. */
156 while (timeout && (!(in_be32(®s->mdio_mcr)
157 & XAE_MDIO_MCR_READY_MASK))) {
162 printf("%s: Timeout\n", __func__);
168 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
171 struct axi_regs *regs = priv->iobase;
177 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
178 XAE_MDIO_MCR_PHYAD_MASK) |
179 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
180 & XAE_MDIO_MCR_REGAD_MASK) |
181 XAE_MDIO_MCR_INITIATE_MASK |
182 XAE_MDIO_MCR_OP_READ_MASK;
184 out_be32(®s->mdio_mcr, mdioctrlreg);
190 *val = in_be32(®s->mdio_mrd);
194 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
197 struct axi_regs *regs = priv->iobase;
203 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
204 XAE_MDIO_MCR_PHYAD_MASK) |
205 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
206 & XAE_MDIO_MCR_REGAD_MASK) |
207 XAE_MDIO_MCR_INITIATE_MASK |
208 XAE_MDIO_MCR_OP_WRITE_MASK;
211 out_be32(®s->mdio_mwd, data);
213 out_be32(®s->mdio_mcr, mdioctrlreg);
221 static int axiemac_phy_init(struct udevice *dev)
225 struct axidma_priv *priv = dev_get_priv(dev);
226 struct axi_regs *regs = priv->iobase;
227 struct phy_device *phydev;
229 u32 supported = SUPPORTED_10baseT_Half |
230 SUPPORTED_10baseT_Full |
231 SUPPORTED_100baseT_Half |
232 SUPPORTED_100baseT_Full |
233 SUPPORTED_1000baseT_Half |
234 SUPPORTED_1000baseT_Full;
236 /* Set default MDIO divisor */
237 out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
239 if (priv->phyaddr == -1) {
240 /* Detect the PHY address */
241 for (i = 31; i >= 0; i--) {
242 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
243 if (!ret && (phyreg != 0xFFFF) &&
244 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
245 /* Found a valid PHY address */
247 debug("axiemac: Found valid phy address, %x\n",
254 /* Interface - look at tsec */
255 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
257 phydev->supported &= supported;
258 phydev->advertising = phydev->supported;
259 priv->phydev = phydev;
265 /* Setting axi emac and phy to proper setting */
266 static int setup_phy(struct udevice *dev)
269 u32 speed, emmc_reg, ret;
270 struct axidma_priv *priv = dev_get_priv(dev);
271 struct axi_regs *regs = priv->iobase;
272 struct phy_device *phydev = priv->phydev;
274 if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
276 * In SGMII cases the isolate bit might set
277 * after DMA and ethernet resets and hence
278 * check and clear if set.
280 ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
283 if (temp & BMCR_ISOLATE) {
284 temp &= ~BMCR_ISOLATE;
285 ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
291 if (phy_startup(phydev)) {
292 printf("axiemac: could not initialize PHY %s\n",
297 printf("%s: No link.\n", phydev->dev->name);
301 switch (phydev->speed) {
303 speed = XAE_EMMC_LINKSPD_1000;
306 speed = XAE_EMMC_LINKSPD_100;
309 speed = XAE_EMMC_LINKSPD_10;
315 /* Setup the emac for the phy speed */
316 emmc_reg = in_be32(®s->emmc);
317 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
320 /* Write new speed setting out to Axi Ethernet */
321 out_be32(®s->emmc, emmc_reg);
324 * Setting the operating speed of the MAC needs a delay. There
325 * doesn't seem to be register to poll, so please consider this
326 * during your application design.
333 /* STOP DMA transfers */
334 static void axiemac_stop(struct udevice *dev)
336 struct axidma_priv *priv = dev_get_priv(dev);
339 /* Stop the hardware */
340 temp = in_be32(&priv->dmatx->control);
341 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
342 out_be32(&priv->dmatx->control, temp);
344 temp = in_be32(&priv->dmarx->control);
345 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
346 out_be32(&priv->dmarx->control, temp);
348 debug("axiemac: Halted\n");
351 static int axi_ethernet_init(struct axidma_priv *priv)
353 struct axi_regs *regs = priv->iobase;
357 * Check the status of the MgtRdy bit in the interrupt status
358 * registers. This must be done to allow the MGT clock to become stable
359 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
360 * will be valid until this bit is valid.
361 * The bit is always a 1 for all other PHY interfaces.
363 err = wait_for_bit(__func__, (const u32 *)®s->is,
364 XAE_INT_MGTRDY_MASK, true, 200, false);
366 printf("%s: Timeout\n", __func__);
370 /* Stop the device and reset HW */
371 /* Disable interrupts */
372 out_be32(®s->ie, 0);
374 /* Disable the receiver */
375 out_be32(®s->rcw1, in_be32(®s->rcw1) & ~XAE_RCW1_RX_MASK);
378 * Stopping the receiver in mid-packet causes a dropped packet
379 * indication from HW. Clear it.
381 /* Set the interrupt status register to clear the interrupt */
382 out_be32(®s->is, XAE_INT_RXRJECT_MASK);
385 /* Set default MDIO divisor */
386 out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
388 debug("axiemac: InitHw done\n");
392 static int axiemac_write_hwaddr(struct udevice *dev)
394 struct eth_pdata *pdata = dev_get_platdata(dev);
395 struct axidma_priv *priv = dev_get_priv(dev);
396 struct axi_regs *regs = priv->iobase;
398 /* Set the MAC address */
399 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
400 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
401 out_be32(®s->uaw0, val);
403 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
404 val |= in_be32(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
405 out_be32(®s->uaw1, val);
409 /* Reset DMA engine */
410 static void axi_dma_init(struct axidma_priv *priv)
414 /* Reset the engine so the hardware starts from a known state */
415 out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK);
416 out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK);
418 /* At the initialization time, hardware should finish reset quickly */
420 /* Check transmit/receive channel */
421 /* Reset is done when the reset bit is low */
422 if (!((in_be32(&priv->dmatx->control) |
423 in_be32(&priv->dmarx->control))
424 & XAXIDMA_CR_RESET_MASK)) {
429 printf("%s: Timeout\n", __func__);
432 static int axiemac_start(struct udevice *dev)
434 struct axidma_priv *priv = dev_get_priv(dev);
435 struct axi_regs *regs = priv->iobase;
438 debug("axiemac: Init started\n");
440 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
441 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
442 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
443 * would ensure a reset of AxiEthernet.
447 /* Initialize AxiEthernet hardware. */
448 if (axi_ethernet_init(priv))
451 /* Disable all RX interrupts before RxBD space setup */
452 temp = in_be32(&priv->dmarx->control);
453 temp &= ~XAXIDMA_IRQ_ALL_MASK;
454 out_be32(&priv->dmarx->control, temp);
456 /* Start DMA RX channel. Now it's ready to receive data.*/
457 out_be32(&priv->dmarx->current, (u32)&rx_bd);
460 memset(&rx_bd, 0, sizeof(rx_bd));
461 rx_bd.next = (u32)&rx_bd;
462 rx_bd.phys = (u32)&rxframe;
463 rx_bd.cntrl = sizeof(rxframe);
464 /* Flush the last BD so DMA core could see the updates */
465 flush_cache((u32)&rx_bd, sizeof(rx_bd));
467 /* It is necessary to flush rxframe because if you don't do it
468 * then cache can contain uninitialized data */
469 flush_cache((u32)&rxframe, sizeof(rxframe));
471 /* Start the hardware */
472 temp = in_be32(&priv->dmarx->control);
473 temp |= XAXIDMA_CR_RUNSTOP_MASK;
474 out_be32(&priv->dmarx->control, temp);
476 /* Rx BD is ready - start */
477 out_be32(&priv->dmarx->tail, (u32)&rx_bd);
480 out_be32(®s->tc, XAE_TC_TX_MASK);
482 out_be32(®s->rcw1, XAE_RCW1_RX_MASK);
485 if (!setup_phy(dev)) {
490 debug("axiemac: Init complete\n");
494 static int axiemac_send(struct udevice *dev, void *ptr, int len)
496 struct axidma_priv *priv = dev_get_priv(dev);
499 if (len > PKTSIZE_ALIGN)
502 /* Flush packet to main memory to be trasfered by DMA */
503 flush_cache((u32)ptr, len);
506 memset(&tx_bd, 0, sizeof(tx_bd));
507 /* At the end of the ring, link the last BD back to the top */
508 tx_bd.next = (u32)&tx_bd;
509 tx_bd.phys = (u32)ptr;
511 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
512 XAXIDMA_BD_CTRL_TXEOF_MASK;
514 /* Flush the last BD so DMA core could see the updates */
515 flush_cache((u32)&tx_bd, sizeof(tx_bd));
517 if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
519 out_be32(&priv->dmatx->current, (u32)&tx_bd);
520 /* Start the hardware */
521 temp = in_be32(&priv->dmatx->control);
522 temp |= XAXIDMA_CR_RUNSTOP_MASK;
523 out_be32(&priv->dmatx->control, temp);
527 out_be32(&priv->dmatx->tail, (u32)&tx_bd);
529 /* Wait for transmission to complete */
530 debug("axiemac: Waiting for tx to be done\n");
532 while (timeout && (!(in_be32(&priv->dmatx->status) &
533 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
538 printf("%s: Timeout\n", __func__);
542 debug("axiemac: Sending complete\n");
546 static int isrxready(struct axidma_priv *priv)
550 /* Read pending interrupts */
551 status = in_be32(&priv->dmarx->status);
553 /* Acknowledge pending interrupts */
554 out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK);
557 * If Reception done interrupt is asserted, call RX call back function
558 * to handle the processed BDs and then raise the according flag.
560 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
566 static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
569 struct axidma_priv *priv = dev_get_priv(dev);
572 /* Wait for an incoming packet */
573 if (!isrxready(priv))
576 debug("axiemac: RX data ready\n");
578 /* Disable IRQ for a moment till packet is handled */
579 temp = in_be32(&priv->dmarx->control);
580 temp &= ~XAXIDMA_IRQ_ALL_MASK;
581 out_be32(&priv->dmarx->control, temp);
583 length = rx_bd.app4 & 0xFFFF; /* max length mask */
585 print_buffer(&rxframe, &rxframe[0], 1, length, 16);
592 static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
594 struct axidma_priv *priv = dev_get_priv(dev);
597 /* It is useful to clear buffer to be sure that it is consistent */
598 memset(rxframe, 0, sizeof(rxframe));
601 /* Clear the whole buffer and setup it again - all flags are cleared */
602 memset(&rx_bd, 0, sizeof(rx_bd));
603 rx_bd.next = (u32)&rx_bd;
604 rx_bd.phys = (u32)&rxframe;
605 rx_bd.cntrl = sizeof(rxframe);
608 flush_cache((u32)&rx_bd, sizeof(rx_bd));
610 /* It is necessary to flush rxframe because if you don't do it
611 * then cache will contain previous packet */
612 flush_cache((u32)&rxframe, sizeof(rxframe));
614 /* Rx BD is ready - start again */
615 out_be32(&priv->dmarx->tail, (u32)&rx_bd);
617 debug("axiemac: RX completed, framelength = %d\n", length);
622 static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
628 ret = phyread(bus->priv, addr, reg, &value);
629 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
634 static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
637 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
638 return phywrite(bus->priv, addr, reg, value);
641 static int axi_emac_probe(struct udevice *dev)
643 struct axidma_priv *priv = dev_get_priv(dev);
646 priv->bus = mdio_alloc();
647 priv->bus->read = axiemac_miiphy_read;
648 priv->bus->write = axiemac_miiphy_write;
649 priv->bus->priv = priv;
651 ret = mdio_register_seq(priv->bus, dev->seq);
655 axiemac_phy_init(dev);
660 static int axi_emac_remove(struct udevice *dev)
662 struct axidma_priv *priv = dev_get_priv(dev);
665 mdio_unregister(priv->bus);
666 mdio_free(priv->bus);
671 static const struct eth_ops axi_emac_ops = {
672 .start = axiemac_start,
673 .send = axiemac_send,
674 .recv = axiemac_recv,
675 .free_pkt = axiemac_free_pkt,
676 .stop = axiemac_stop,
677 .write_hwaddr = axiemac_write_hwaddr,
680 static int axi_emac_ofdata_to_platdata(struct udevice *dev)
682 struct eth_pdata *pdata = dev_get_platdata(dev);
683 struct axidma_priv *priv = dev_get_priv(dev);
684 int node = dev_of_offset(dev);
686 const char *phy_mode;
688 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
689 priv->iobase = (struct axi_regs *)pdata->iobase;
691 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
692 "axistream-connected");
694 printf("%s: axistream is not found\n", __func__);
697 priv->dmatx = (struct axidma_reg *)fdtdec_get_int(gd->fdt_blob,
700 printf("%s: axi_dma register space not found\n", __func__);
703 /* RX channel offset is 0x30 */
704 priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
708 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
710 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
712 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
714 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
715 if (pdata->phy_interface == -1) {
716 printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
719 priv->interface = pdata->phy_interface;
721 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
722 priv->phyaddr, phy_string_for_interface(priv->interface));
727 static const struct udevice_id axi_emac_ids[] = {
728 { .compatible = "xlnx,axi-ethernet-1.00.a" },
732 U_BOOT_DRIVER(axi_emac) = {
735 .of_match = axi_emac_ids,
736 .ofdata_to_platdata = axi_emac_ofdata_to_platdata,
737 .probe = axi_emac_probe,
738 .remove = axi_emac_remove,
739 .ops = &axi_emac_ops,
740 .priv_auto_alloc_size = sizeof(struct axidma_priv),
741 .platdata_auto_alloc_size = sizeof(struct eth_pdata),