1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2009 Michal Simek
4 * (C) Copyright 2003 Xilinx Inc.
6 * Michal SIMEK <monstr@monstr.eu>
19 #include <linux/errno.h>
20 #include <linux/kernel.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #define ENET_ADDR_LENGTH 6
26 #define ETH_FCS_LEN 4 /* Octets in the FCS */
29 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
30 /* Xmit interrupt enable bit */
31 #define XEL_TSR_XMIT_IE_MASK 0x00000008UL
32 /* Program the MAC address */
33 #define XEL_TSR_PROGRAM_MASK 0x00000002UL
34 /* define for programming the MAC address into the EMAC Lite */
35 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
37 /* Transmit packet length upper byte */
38 #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
39 /* Transmit packet length lower byte */
40 #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
43 #define XEL_RSR_RECV_DONE_MASK 0x00000001UL
44 /* Recv interrupt enable bit */
45 #define XEL_RSR_RECV_IE_MASK 0x00000008UL
47 /* MDIO Address Register Bit Masks */
48 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
49 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
50 #define XEL_MDIOADDR_PHYADR_SHIFT 5
51 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
53 /* MDIO Write Data Register Bit Masks */
54 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
56 /* MDIO Read Data Register Bit Masks */
57 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
59 /* MDIO Control Register Bit Masks */
60 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
61 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
63 struct emaclite_regs {
64 u32 tx_ping; /* 0x0 - TX Ping buffer */
66 u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
67 u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
68 u32 mdiord;/* 0x7ec - MDIO Read Data Register */
69 u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
70 u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
71 u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
72 u32 tx_ping_tsr; /* 0x7fc - Tx status */
73 u32 tx_pong; /* 0x800 - TX Pong buffer */
75 u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
76 u32 reserved3; /* 0xff8 */
77 u32 tx_pong_tsr; /* 0xffc - Tx status */
78 u32 rx_ping; /* 0x1000 - Receive Buffer */
80 u32 rx_ping_rsr; /* 0x17fc - Rx status */
81 u32 rx_pong; /* 0x1800 - Receive Buffer */
83 u32 rx_pong_rsr; /* 0x1ffc - Rx status */
87 bool use_rx_pong_buffer_next; /* Next RX buffer to read from */
88 u32 txpp; /* TX ping pong buffer */
89 u32 rxpp; /* RX ping pong buffer */
91 struct emaclite_regs *regs;
92 struct phy_device *phydev;
96 static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
98 static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
107 from32ptr = (u32 *) srcptr;
109 /* Word aligned buffer, no correction needed. */
110 to32ptr = (u32 *) destptr;
111 while (bytecount > 3) {
112 *to32ptr++ = *from32ptr++;
115 to8ptr = (u8 *) to32ptr;
117 alignbuffer = *from32ptr++;
118 from8ptr = (u8 *) &alignbuffer;
120 for (i = 0; i < bytecount; i++)
121 *to8ptr++ = *from8ptr++;
124 static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
128 u32 *to32ptr = (u32 *) destptr;
133 from32ptr = (u32 *) srcptr;
134 while (bytecount > 3) {
136 *to32ptr++ = *from32ptr++;
141 to8ptr = (u8 *) &alignbuffer;
142 from8ptr = (u8 *) from32ptr;
144 for (i = 0; i < bytecount; i++)
145 *to8ptr++ = *from8ptr++;
147 *to32ptr++ = alignbuffer;
150 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
151 bool set, unsigned int timeout)
154 unsigned long start = get_timer(0);
157 val = __raw_readl(reg);
162 if ((val & mask) == mask)
165 if (get_timer(start) > timeout)
176 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
177 func, reg, mask, set);
182 static int mdio_wait(struct emaclite_regs *regs)
184 return wait_for_bit(__func__, ®s->mdioctrl,
185 XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
188 static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
191 struct emaclite_regs *regs = emaclite->regs;
196 u32 ctrl_reg = __raw_readl(®s->mdioctrl);
197 __raw_writel(XEL_MDIOADDR_OP_MASK
198 | ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
199 | registernum), ®s->mdioaddr);
200 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl);
206 *data = __raw_readl(®s->mdiord);
210 static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
213 struct emaclite_regs *regs = emaclite->regs;
219 * Write the PHY address, register number and clear the OP bit in the
220 * MDIO Address register and then write the value into the MDIO Write
221 * Data register. Finally, set the Status bit in the MDIO Control
222 * register to start a MDIO write transaction.
224 u32 ctrl_reg = __raw_readl(®s->mdioctrl);
225 __raw_writel(~XEL_MDIOADDR_OP_MASK
226 & ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
227 | registernum), ®s->mdioaddr);
228 __raw_writel(data, ®s->mdiowr);
229 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl);
237 static void emaclite_stop(struct udevice *dev)
242 /* Use MII register 1 (MII status register) to detect PHY */
243 #define PHY_DETECT_REG 1
245 /* Mask used to verify certain PHY features (or register contents)
246 * in the register above:
247 * 0x1000: 10Mbps full duplex support
248 * 0x0800: 10Mbps half duplex support
249 * 0x0008: Auto-negotiation support
251 #define PHY_DETECT_MASK 0x1808
253 static int setup_phy(struct udevice *dev)
257 struct xemaclite *emaclite = dev_get_priv(dev);
258 struct phy_device *phydev;
260 u32 supported = SUPPORTED_10baseT_Half |
261 SUPPORTED_10baseT_Full |
262 SUPPORTED_100baseT_Half |
263 SUPPORTED_100baseT_Full;
265 if (emaclite->phyaddr != -1) {
266 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
267 if ((phyreg != 0xFFFF) &&
268 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
269 /* Found a valid PHY address */
270 debug("Default phy address %d is valid\n",
273 debug("PHY address is not setup correctly %d\n",
275 emaclite->phyaddr = -1;
279 if (emaclite->phyaddr == -1) {
280 /* detect the PHY address */
281 for (i = 31; i >= 0; i--) {
282 phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
283 if ((phyreg != 0xFFFF) &&
284 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
285 /* Found a valid PHY address */
286 emaclite->phyaddr = i;
287 debug("emaclite: Found valid phy address, %d\n",
294 /* interface - look at tsec */
295 phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
296 PHY_INTERFACE_MODE_MII);
298 * Phy can support 1000baseT but device NOT that's why phydev->supported
299 * must be setup for 1000baseT. phydev->advertising setups what speeds
300 * will be used for autonegotiation where 1000baseT must be disabled.
302 phydev->supported = supported | SUPPORTED_1000baseT_Half |
303 SUPPORTED_1000baseT_Full;
304 phydev->advertising = supported;
305 emaclite->phydev = phydev;
307 ret = phy_startup(phydev);
312 printf("%s: No link.\n", phydev->dev->name);
316 /* Do not setup anything */
320 static int emaclite_start(struct udevice *dev)
322 struct xemaclite *emaclite = dev_get_priv(dev);
323 struct eth_pdata *pdata = dev_get_platdata(dev);
324 struct emaclite_regs *regs = emaclite->regs;
326 debug("EmacLite Initialization Started\n");
329 * TX - TX_PING & TX_PONG initialization
331 /* Restart PING TX */
332 __raw_writel(0, ®s->tx_ping_tsr);
333 /* Copy MAC address */
334 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping,
337 __raw_writel(ENET_ADDR_LENGTH, ®s->tx_ping_tplr);
338 /* Update the MAC address in the EMAC Lite */
339 __raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_ping_tsr);
340 /* Wait for EMAC Lite to finish with the MAC address update */
341 while ((__raw_readl(®s->tx_ping_tsr) &
342 XEL_TSR_PROG_MAC_ADDR) != 0)
345 if (emaclite->txpp) {
346 /* The same operation with PONG TX */
347 __raw_writel(0, ®s->tx_pong_tsr);
348 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong,
350 __raw_writel(ENET_ADDR_LENGTH, ®s->tx_pong_tplr);
351 __raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_pong_tsr);
352 while ((__raw_readl(®s->tx_pong_tsr) &
353 XEL_TSR_PROG_MAC_ADDR) != 0)
358 * RX - RX_PING & RX_PONG initialization
360 /* Write out the value to flush the RX buffer */
361 __raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_ping_rsr);
364 __raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_pong_rsr);
366 __raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, ®s->mdioctrl);
367 if (__raw_readl(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
371 debug("EmacLite Initialization complete\n");
375 static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
378 struct emaclite_regs *regs = emaclite->regs;
381 * Read the other buffer register
382 * and determine if the other buffer is available
384 tmp = ~__raw_readl(®s->tx_ping_tsr);
386 tmp |= ~__raw_readl(®s->tx_pong_tsr);
388 return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
391 static int emaclite_send(struct udevice *dev, void *ptr, int len)
394 struct xemaclite *emaclite = dev_get_priv(dev);
395 struct emaclite_regs *regs = emaclite->regs;
402 while (xemaclite_txbufferavailable(emaclite) && maxtry) {
408 printf("Error: Timeout waiting for ethernet TX buffer\n");
409 /* Restart PING TX */
410 __raw_writel(0, ®s->tx_ping_tsr);
411 if (emaclite->txpp) {
412 __raw_writel(0, ®s->tx_pong_tsr);
417 /* Determine if the expected buffer address is empty */
418 reg = __raw_readl(®s->tx_ping_tsr);
419 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
420 debug("Send packet from tx_ping buffer\n");
421 /* Write the frame to the buffer */
422 xemaclite_alignedwrite(ptr, ®s->tx_ping, len);
424 & (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO),
425 ®s->tx_ping_tplr);
426 reg = __raw_readl(®s->tx_ping_tsr);
427 reg |= XEL_TSR_XMIT_BUSY_MASK;
428 __raw_writel(reg, ®s->tx_ping_tsr);
432 if (emaclite->txpp) {
433 /* Determine if the expected buffer address is empty */
434 reg = __raw_readl(®s->tx_pong_tsr);
435 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
436 debug("Send packet from tx_pong buffer\n");
437 /* Write the frame to the buffer */
438 xemaclite_alignedwrite(ptr, ®s->tx_pong, len);
440 (XEL_TPLR_LENGTH_MASK_HI |
441 XEL_TPLR_LENGTH_MASK_LO),
442 ®s->tx_pong_tplr);
443 reg = __raw_readl(®s->tx_pong_tsr);
444 reg |= XEL_TSR_XMIT_BUSY_MASK;
445 __raw_writel(reg, ®s->tx_pong_tsr);
450 puts("Error while sending frame\n");
454 static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
456 u32 length, first_read, reg, attempt = 0;
458 struct xemaclite *emaclite = dev->priv;
459 struct emaclite_regs *regs = emaclite->regs;
460 struct ethernet_hdr *eth;
461 struct ip_udp_hdr *ip;
464 if (!emaclite->use_rx_pong_buffer_next) {
465 reg = __raw_readl(®s->rx_ping_rsr);
466 debug("Testing data at rx_ping\n");
467 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
468 debug("Data found in rx_ping buffer\n");
469 addr = ®s->rx_ping;
470 ack = ®s->rx_ping_rsr;
472 debug("Data not found in rx_ping buffer\n");
473 /* Pong buffer is not available - return immediately */
477 /* Try pong buffer if this is first attempt */
480 emaclite->use_rx_pong_buffer_next =
481 !emaclite->use_rx_pong_buffer_next;
485 reg = __raw_readl(®s->rx_pong_rsr);
486 debug("Testing data at rx_pong\n");
487 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
488 debug("Data found in rx_pong buffer\n");
489 addr = ®s->rx_pong;
490 ack = ®s->rx_pong_rsr;
492 debug("Data not found in rx_pong buffer\n");
493 /* Try ping buffer if this is first attempt */
496 emaclite->use_rx_pong_buffer_next =
497 !emaclite->use_rx_pong_buffer_next;
502 /* Read all bytes for ARP packet with 32bit alignment - 48bytes */
503 first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
504 xemaclite_alignedread(addr, etherrxbuff, first_read);
506 /* Detect real packet size */
507 eth = (struct ethernet_hdr *)etherrxbuff;
508 switch (ntohs(eth->et_protlen)) {
511 debug("ARP Packet %x\n", length);
514 ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
515 length = ntohs(ip->ip_len);
516 length += ETHER_HDR_SIZE + ETH_FCS_LEN;
517 debug("IP Packet %x\n", length);
520 debug("Other Packet\n");
525 /* Read the rest of the packet which is longer then first read */
526 if (length != first_read)
527 xemaclite_alignedread(addr + first_read,
528 etherrxbuff + first_read,
529 length - first_read);
531 /* Acknowledge the frame */
532 reg = __raw_readl(ack);
533 reg &= ~XEL_RSR_RECV_DONE_MASK;
534 __raw_writel(reg, ack);
536 debug("Packet receive from 0x%p, length %dB\n", addr, length);
537 *packetp = etherrxbuff;
541 static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
547 ret = phyread(bus->priv, addr, reg, &val);
548 debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
552 static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
555 debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
556 return phywrite(bus->priv, addr, reg, value);
559 static int emaclite_probe(struct udevice *dev)
561 struct xemaclite *emaclite = dev_get_priv(dev);
564 emaclite->bus = mdio_alloc();
565 emaclite->bus->read = emaclite_miiphy_read;
566 emaclite->bus->write = emaclite_miiphy_write;
567 emaclite->bus->priv = emaclite;
569 ret = mdio_register_seq(emaclite->bus, dev->seq);
576 static int emaclite_remove(struct udevice *dev)
578 struct xemaclite *emaclite = dev_get_priv(dev);
580 free(emaclite->phydev);
581 mdio_unregister(emaclite->bus);
582 mdio_free(emaclite->bus);
587 static const struct eth_ops emaclite_ops = {
588 .start = emaclite_start,
589 .send = emaclite_send,
590 .recv = emaclite_recv,
591 .stop = emaclite_stop,
594 static int emaclite_ofdata_to_platdata(struct udevice *dev)
596 struct eth_pdata *pdata = dev_get_platdata(dev);
597 struct xemaclite *emaclite = dev_get_priv(dev);
600 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
601 emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
604 emaclite->phyaddr = -1;
606 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
609 emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
612 emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
613 "xlnx,tx-ping-pong", 0);
614 emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
615 "xlnx,rx-ping-pong", 0);
617 printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
618 emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
623 static const struct udevice_id emaclite_ids[] = {
624 { .compatible = "xlnx,xps-ethernetlite-1.00.a" },
628 U_BOOT_DRIVER(emaclite) = {
631 .of_match = emaclite_ids,
632 .ofdata_to_platdata = emaclite_ofdata_to_platdata,
633 .probe = emaclite_probe,
634 .remove = emaclite_remove,
635 .ops = &emaclite_ops,
636 .priv_auto_alloc_size = sizeof(struct xemaclite),
637 .platdata_auto_alloc_size = sizeof(struct eth_pdata),