git.sur5r.net Git - u-boot/blob - drivers/nvme/nvme.c

   1 /*
   2  * Copyright (C) 2017 NXP Semiconductors
   3  * Copyright (C) 2017 Bin Meng <bmeng.cn@gmail.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <memalign.h>
  12 #include <pci.h>
  13 #include <dm/device-internal.h>
  14 #include "nvme.h"
  15
  16 struct nvme_info *nvme_info;
  17
  18 #define NVME_Q_DEPTH            2
  19 #define NVME_AQ_DEPTH           2
  20 #define NVME_SQ_SIZE(depth)     (depth * sizeof(struct nvme_command))
  21 #define NVME_CQ_SIZE(depth)     (depth * sizeof(struct nvme_completion))
  22 #define ADMIN_TIMEOUT           60
  23 #define IO_TIMEOUT              30
  24 #define MAX_PRP_POOL            512
  25
  26 enum nvme_queue_id {
  27         NVME_ADMIN_Q,
  28         NVME_IO_Q,
  29         NVME_Q_NUM,
  30 };
  31
  32 /*
  33  * An NVM Express queue. Each device has at least two (one for admin
  34  * commands and one for I/O commands).
  35  */
  36 struct nvme_queue {
  37         struct nvme_dev *dev;
  38         struct nvme_command *sq_cmds;
  39         struct nvme_completion *cqes;
  40         wait_queue_head_t sq_full;
  41         u32 __iomem *q_db;
  42         u16 q_depth;
  43         s16 cq_vector;
  44         u16 sq_head;
  45         u16 sq_tail;
  46         u16 cq_head;
  47         u16 qid;
  48         u8 cq_phase;
  49         u8 cqe_seen;
  50         unsigned long cmdid_data[];
  51 };
  52
  53 static int nvme_wait_ready(struct nvme_dev *dev, bool enabled)
  54 {
  55         u32 bit = enabled ? NVME_CSTS_RDY : 0;
  56         int timeout;
  57         ulong start;
  58
  59         /* Timeout field in the CAP register is in 500 millisecond units */
  60         timeout = NVME_CAP_TIMEOUT(dev->cap) * 500;
  61
  62         start = get_timer(0);
  63         while (get_timer(start) < timeout) {
  64                 if ((readl(&dev->bar->csts) & NVME_CSTS_RDY) == bit)
  65                         return 0;
  66         }
  67
  68         return -ETIME;
  69 }
  70
  71 static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
  72                            int total_len, u64 dma_addr)
  73 {
  74         u32 page_size = dev->page_size;
  75         int offset = dma_addr & (page_size - 1);
  76         u64 *prp_pool;
  77         int length = total_len;
  78         int i, nprps;
  79         length -= (page_size - offset);
  80
  81         if (length <= 0) {
  82                 *prp2 = 0;
  83                 return 0;
  84         }
  85
  86         if (length)
  87                 dma_addr += (page_size - offset);
  88
  89         if (length <= page_size) {
  90                 *prp2 = dma_addr;
  91                 return 0;
  92         }
  93
  94         nprps = DIV_ROUND_UP(length, page_size);
  95
  96         if (nprps > dev->prp_entry_num) {
  97                 free(dev->prp_pool);
  98                 dev->prp_pool = malloc(nprps << 3);
  99                 if (!dev->prp_pool) {
 100                         printf("Error: malloc prp_pool fail\n");
 101                         return -ENOMEM;
 102                 }
 103                 dev->prp_entry_num = nprps;
 104         }
 105
 106         prp_pool = dev->prp_pool;
 107         i = 0;
 108         while (nprps) {
 109                 if (i == ((page_size >> 3) - 1)) {
 110                         *(prp_pool + i) = cpu_to_le64((ulong)prp_pool +
 111                                         page_size);
 112                         i = 0;
 113                         prp_pool += page_size;
 114                 }
 115                 *(prp_pool + i++) = cpu_to_le64(dma_addr);
 116                 dma_addr += page_size;
 117                 nprps--;
 118         }
 119         *prp2 = (ulong)dev->prp_pool;
 120
 121         return 0;
 122 }
 123
 124 static __le16 nvme_get_cmd_id(void)
 125 {
 126         static unsigned short cmdid;
 127
 128         return cpu_to_le16((cmdid < USHRT_MAX) ? cmdid++ : 0);
 129 }
 130
 131 static u16 nvme_read_completion_status(struct nvme_queue *nvmeq, u16 index)
 132 {
 133         u64 start = (ulong)&nvmeq->cqes[index];
 134         u64 stop = start + sizeof(struct nvme_completion);
 135
 136         invalidate_dcache_range(start, stop);
 137
 138         return le16_to_cpu(readw(&(nvmeq->cqes[index].status)));
 139 }
 140
 141 /**
 142  * nvme_submit_cmd() - copy a command into a queue and ring the doorbell
 143  *
 144  * @nvmeq:      The queue to use
 145  * @cmd:        The command to send
 146  */
 147 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 148 {
 149         u16 tail = nvmeq->sq_tail;
 150
 151         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 152         flush_dcache_range((ulong)&nvmeq->sq_cmds[tail],
 153                            (ulong)&nvmeq->sq_cmds[tail] + sizeof(*cmd));
 154
 155         if (++tail == nvmeq->q_depth)
 156                 tail = 0;
 157         writel(tail, nvmeq->q_db);
 158         nvmeq->sq_tail = tail;
 159 }
 160
 161 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 162                                 struct nvme_command *cmd,
 163                                 u32 *result, unsigned timeout)
 164 {
 165         u16 head = nvmeq->cq_head;
 166         u16 phase = nvmeq->cq_phase;
 167         u16 status;
 168         ulong start_time;
 169         ulong timeout_us = timeout * 100000;
 170
 171         cmd->common.command_id = nvme_get_cmd_id();
 172         nvme_submit_cmd(nvmeq, cmd);
 173
 174         start_time = timer_get_us();
 175
 176         for (;;) {
 177                 status = nvme_read_completion_status(nvmeq, head);
 178                 if ((status & 0x01) == phase)
 179                         break;
 180                 if (timeout_us > 0 && (timer_get_us() - start_time)
 181                     >= timeout_us)
 182                         return -ETIMEDOUT;
 183         }
 184
 185         status >>= 1;
 186         if (status) {
 187                 printf("ERROR: status = %x, phase = %d, head = %d\n",
 188                        status, phase, head);
 189                 status = 0;
 190                 if (++head == nvmeq->q_depth) {
 191                         head = 0;
 192                         phase = !phase;
 193                 }
 194                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 195                 nvmeq->cq_head = head;
 196                 nvmeq->cq_phase = phase;
 197
 198                 return -EIO;
 199         }
 200
 201         if (result)
 202                 *result = le32_to_cpu(readl(&(nvmeq->cqes[head].result)));
 203
 204         if (++head == nvmeq->q_depth) {
 205                 head = 0;
 206                 phase = !phase;
 207         }
 208         writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 209         nvmeq->cq_head = head;
 210         nvmeq->cq_phase = phase;
 211
 212         return status;
 213 }
 214
 215 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 216                                  u32 *result)
 217 {
 218         return nvme_submit_sync_cmd(dev->queues[NVME_ADMIN_Q], cmd,
 219                                     result, ADMIN_TIMEOUT);
 220 }
 221
 222 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev,
 223                                            int qid, int depth)
 224 {
 225         struct nvme_queue *nvmeq = malloc(sizeof(*nvmeq));
 226         if (!nvmeq)
 227                 return NULL;
 228         memset(nvmeq, 0, sizeof(*nvmeq));
 229
 230         nvmeq->cqes = (void *)memalign(4096, NVME_CQ_SIZE(depth));
 231         if (!nvmeq->cqes)
 232                 goto free_nvmeq;
 233         memset((void *)nvmeq->cqes, 0, NVME_CQ_SIZE(depth));
 234
 235         nvmeq->sq_cmds = (void *)memalign(4096, NVME_SQ_SIZE(depth));
 236         if (!nvmeq->sq_cmds)
 237                 goto free_queue;
 238         memset((void *)nvmeq->sq_cmds, 0, NVME_SQ_SIZE(depth));
 239
 240         nvmeq->dev = dev;
 241
 242         nvmeq->cq_head = 0;
 243         nvmeq->cq_phase = 1;
 244         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
 245         nvmeq->q_depth = depth;
 246         nvmeq->qid = qid;
 247         dev->queue_count++;
 248         dev->queues[qid] = nvmeq;
 249
 250         return nvmeq;
 251
 252  free_queue:
 253         free((void *)nvmeq->cqes);
 254  free_nvmeq:
 255         free(nvmeq);
 256
 257         return NULL;
 258 }
 259
 260 static int nvme_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 261 {
 262         struct nvme_command c;
 263
 264         memset(&c, 0, sizeof(c));
 265         c.delete_queue.opcode = opcode;
 266         c.delete_queue.qid = cpu_to_le16(id);
 267
 268         return nvme_submit_admin_cmd(dev, &c, NULL);
 269 }
 270
 271 static int nvme_delete_sq(struct nvme_dev *dev, u16 sqid)
 272 {
 273         return nvme_delete_queue(dev, nvme_admin_delete_sq, sqid);
 274 }
 275
 276 static int nvme_delete_cq(struct nvme_dev *dev, u16 cqid)
 277 {
 278         return nvme_delete_queue(dev, nvme_admin_delete_cq, cqid);
 279 }
 280
 281 static int nvme_enable_ctrl(struct nvme_dev *dev)
 282 {
 283         dev->ctrl_config &= ~NVME_CC_SHN_MASK;
 284         dev->ctrl_config |= NVME_CC_ENABLE;
 285         writel(cpu_to_le32(dev->ctrl_config), &dev->bar->cc);
 286
 287         return nvme_wait_ready(dev, true);
 288 }
 289
 290 static int nvme_disable_ctrl(struct nvme_dev *dev)
 291 {
 292         dev->ctrl_config &= ~NVME_CC_SHN_MASK;
 293         dev->ctrl_config &= ~NVME_CC_ENABLE;
 294         writel(cpu_to_le32(dev->ctrl_config), &dev->bar->cc);
 295
 296         return nvme_wait_ready(dev, false);
 297 }
 298
 299 static void nvme_free_queue(struct nvme_queue *nvmeq)
 300 {
 301         free((void *)nvmeq->cqes);
 302         free(nvmeq->sq_cmds);
 303         free(nvmeq);
 304 }
 305
 306 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
 307 {
 308         int i;
 309
 310         for (i = dev->queue_count - 1; i >= lowest; i--) {
 311                 struct nvme_queue *nvmeq = dev->queues[i];
 312                 dev->queue_count--;
 313                 dev->queues[i] = NULL;
 314                 nvme_free_queue(nvmeq);
 315         }
 316 }
 317
 318 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
 319 {
 320         struct nvme_dev *dev = nvmeq->dev;
 321
 322         nvmeq->sq_tail = 0;
 323         nvmeq->cq_head = 0;
 324         nvmeq->cq_phase = 1;
 325         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
 326         memset((void *)nvmeq->cqes, 0, NVME_CQ_SIZE(nvmeq->q_depth));
 327         flush_dcache_range((ulong)nvmeq->cqes,
 328                            (ulong)nvmeq->cqes + NVME_CQ_SIZE(nvmeq->q_depth));
 329         dev->online_queues++;
 330 }
 331
 332 static int nvme_configure_admin_queue(struct nvme_dev *dev)
 333 {
 334         int result;
 335         u32 aqa;
 336         u64 cap = dev->cap;
 337         struct nvme_queue *nvmeq;
 338         /* most architectures use 4KB as the page size */
 339         unsigned page_shift = 12;
 340         unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
 341         unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
 342
 343         if (page_shift < dev_page_min) {
 344                 debug("Device minimum page size (%u) too large for host (%u)\n",
 345                       1 << dev_page_min, 1 << page_shift);
 346                 return -ENODEV;
 347         }
 348
 349         if (page_shift > dev_page_max) {
 350                 debug("Device maximum page size (%u) smaller than host (%u)\n",
 351                       1 << dev_page_max, 1 << page_shift);
 352                 page_shift = dev_page_max;
 353         }
 354
 355         result = nvme_disable_ctrl(dev);
 356         if (result < 0)
 357                 return result;
 358
 359         nvmeq = dev->queues[NVME_ADMIN_Q];
 360         if (!nvmeq) {
 361                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
 362                 if (!nvmeq)
 363                         return -ENOMEM;
 364         }
 365
 366         aqa = nvmeq->q_depth - 1;
 367         aqa |= aqa << 16;
 368         aqa |= aqa << 16;
 369
 370         dev->page_size = 1 << page_shift;
 371
 372         dev->ctrl_config = NVME_CC_CSS_NVM;
 373         dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
 374         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 375         dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
 376
 377         writel(aqa, &dev->bar->aqa);
 378         nvme_writeq((ulong)nvmeq->sq_cmds, &dev->bar->asq);
 379         nvme_writeq((ulong)nvmeq->cqes, &dev->bar->acq);
 380
 381         result = nvme_enable_ctrl(dev);
 382         if (result)
 383                 goto free_nvmeq;
 384
 385         nvmeq->cq_vector = 0;
 386
 387         nvme_init_queue(dev->queues[NVME_ADMIN_Q], 0);
 388
 389         return result;
 390
 391  free_nvmeq:
 392         nvme_free_queues(dev, 0);
 393
 394         return result;
 395 }
 396
 397 static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid,
 398                             struct nvme_queue *nvmeq)
 399 {
 400         struct nvme_command c;
 401         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 402
 403         memset(&c, 0, sizeof(c));
 404         c.create_cq.opcode = nvme_admin_create_cq;
 405         c.create_cq.prp1 = cpu_to_le64((ulong)nvmeq->cqes);
 406         c.create_cq.cqid = cpu_to_le16(qid);
 407         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 408         c.create_cq.cq_flags = cpu_to_le16(flags);
 409         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 410
 411         return nvme_submit_admin_cmd(dev, &c, NULL);
 412 }
 413
 414 static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid,
 415                             struct nvme_queue *nvmeq)
 416 {
 417         struct nvme_command c;
 418         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 419
 420         memset(&c, 0, sizeof(c));
 421         c.create_sq.opcode = nvme_admin_create_sq;
 422         c.create_sq.prp1 = cpu_to_le64((ulong)nvmeq->sq_cmds);
 423         c.create_sq.sqid = cpu_to_le16(qid);
 424         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 425         c.create_sq.sq_flags = cpu_to_le16(flags);
 426         c.create_sq.cqid = cpu_to_le16(qid);
 427
 428         return nvme_submit_admin_cmd(dev, &c, NULL);
 429 }
 430
 431 int nvme_identify(struct nvme_dev *dev, unsigned nsid,
 432                   unsigned cns, dma_addr_t dma_addr)
 433 {
 434         struct nvme_command c;
 435         u32 page_size = dev->page_size;
 436         int offset = dma_addr & (page_size - 1);
 437         int length = sizeof(struct nvme_id_ctrl);
 438         int ret;
 439
 440         memset(&c, 0, sizeof(c));
 441         c.identify.opcode = nvme_admin_identify;
 442         c.identify.nsid = cpu_to_le32(nsid);
 443         c.identify.prp1 = cpu_to_le64(dma_addr);
 444
 445         length -= (page_size - offset);
 446         if (length <= 0) {
 447                 c.identify.prp2 = 0;
 448         } else {
 449                 dma_addr += (page_size - offset);
 450                 c.identify.prp2 = cpu_to_le64(dma_addr);
 451         }
 452
 453         c.identify.cns = cpu_to_le32(cns);
 454
 455         ret = nvme_submit_admin_cmd(dev, &c, NULL);
 456         if (!ret)
 457                 invalidate_dcache_range(dma_addr,
 458                                         dma_addr + sizeof(struct nvme_id_ctrl));
 459
 460         return ret;
 461 }
 462
 463 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
 464                       dma_addr_t dma_addr, u32 *result)
 465 {
 466         struct nvme_command c;
 467
 468         memset(&c, 0, sizeof(c));
 469         c.features.opcode = nvme_admin_get_features;
 470         c.features.nsid = cpu_to_le32(nsid);
 471         c.features.prp1 = cpu_to_le64(dma_addr);
 472         c.features.fid = cpu_to_le32(fid);
 473
 474         /*
 475          * TODO: add cache invalidate operation when the size of
 476          * the DMA buffer is known
 477          */
 478
 479         return nvme_submit_admin_cmd(dev, &c, result);
 480 }
 481
 482 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
 483                       dma_addr_t dma_addr, u32 *result)
 484 {
 485         struct nvme_command c;
 486
 487         memset(&c, 0, sizeof(c));
 488         c.features.opcode = nvme_admin_set_features;
 489         c.features.prp1 = cpu_to_le64(dma_addr);
 490         c.features.fid = cpu_to_le32(fid);
 491         c.features.dword11 = cpu_to_le32(dword11);
 492
 493         /*
 494          * TODO: add cache flush operation when the size of
 495          * the DMA buffer is known
 496          */
 497
 498         return nvme_submit_admin_cmd(dev, &c, result);
 499 }
 500
 501 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
 502 {
 503         struct nvme_dev *dev = nvmeq->dev;
 504         int result;
 505
 506         nvmeq->cq_vector = qid - 1;
 507         result = nvme_alloc_cq(dev, qid, nvmeq);
 508         if (result < 0)
 509                 goto release_cq;
 510
 511         result = nvme_alloc_sq(dev, qid, nvmeq);
 512         if (result < 0)
 513                 goto release_sq;
 514
 515         nvme_init_queue(nvmeq, qid);
 516
 517         return result;
 518
 519  release_sq:
 520         nvme_delete_sq(dev, qid);
 521  release_cq:
 522         nvme_delete_cq(dev, qid);
 523
 524         return result;
 525 }
 526
 527 static int nvme_set_queue_count(struct nvme_dev *dev, int count)
 528 {
 529         int status;
 530         u32 result;
 531         u32 q_count = (count - 1) | ((count - 1) << 16);
 532
 533         status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES,
 534                         q_count, 0, &result);
 535
 536         if (status < 0)
 537                 return status;
 538         if (status > 1)
 539                 return 0;
 540
 541         return min(result & 0xffff, result >> 16) + 1;
 542 }
 543
 544 static void nvme_create_io_queues(struct nvme_dev *dev)
 545 {
 546         unsigned int i;
 547
 548         for (i = dev->queue_count; i <= dev->max_qid; i++)
 549                 if (!nvme_alloc_queue(dev, i, dev->q_depth))
 550                         break;
 551
 552         for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
 553                 if (nvme_create_queue(dev->queues[i], i))
 554                         break;
 555 }
 556
 557 static int nvme_setup_io_queues(struct nvme_dev *dev)
 558 {
 559         int nr_io_queues;
 560         int result;
 561
 562         nr_io_queues = 1;
 563         result = nvme_set_queue_count(dev, nr_io_queues);
 564         if (result <= 0)
 565                 return result;
 566
 567         if (result < nr_io_queues)
 568                 nr_io_queues = result;
 569
 570         dev->max_qid = nr_io_queues;
 571
 572         /* Free previously allocated queues */
 573         nvme_free_queues(dev, nr_io_queues + 1);
 574         nvme_create_io_queues(dev);
 575
 576         return 0;
 577 }
 578
 579 static int nvme_get_info_from_identify(struct nvme_dev *dev)
 580 {
 581         ALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ctrl));
 582         struct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf;
 583         int ret;
 584         int shift = NVME_CAP_MPSMIN(dev->cap) + 12;
 585
 586         ret = nvme_identify(dev, 0, 1, (dma_addr_t)ctrl);
 587         if (ret)
 588                 return -EIO;
 589
 590         dev->nn = le32_to_cpu(ctrl->nn);
 591         dev->vwc = ctrl->vwc;
 592         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
 593         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
 594         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
 595         if (ctrl->mdts)
 596                 dev->max_transfer_shift = (ctrl->mdts + shift);
 597         else {
 598                 /*
 599                  * Maximum Data Transfer Size (MDTS) field indicates the maximum
 600                  * data transfer size between the host and the controller. The
 601                  * host should not submit a command that exceeds this transfer
 602                  * size. The value is in units of the minimum memory page size
 603                  * and is reported as a power of two (2^n).
 604                  *
 605                  * The spec also says: a value of 0h indicates no restrictions
 606                  * on transfer size. But in nvme_blk_read/write() below we have
 607                  * the following algorithm for maximum number of logic blocks
 608                  * per transfer:
 609                  *
 610                  * u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift);
 611                  *
 612                  * In order for lbas not to overflow, the maximum number is 15
 613                  * which means dev->max_transfer_shift = 15 + 9 (ns->lba_shift).
 614                  * Let's use 20 which provides 1MB size.
 615                  */
 616                 dev->max_transfer_shift = 20;
 617         }
 618
 619         return 0;
 620 }
 621
 622 int nvme_scan_namespace(void)
 623 {
 624         struct uclass *uc;
 625         struct udevice *dev;
 626         int ret;
 627
 628         ret = uclass_get(UCLASS_NVME, &uc);
 629         if (ret)
 630                 return ret;
 631
 632         uclass_foreach_dev(dev, uc) {
 633                 ret = device_probe(dev);
 634                 if (ret)
 635                         return ret;
 636         }
 637
 638         return 0;
 639 }
 640
 641 static int nvme_blk_probe(struct udevice *udev)
 642 {
 643         struct nvme_dev *ndev = dev_get_priv(udev->parent);
 644         struct blk_desc *desc = dev_get_uclass_platdata(udev);
 645         struct nvme_ns *ns = dev_get_priv(udev);
 646         u8 flbas;
 647         ALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ns));
 648         struct nvme_id_ns *id = (struct nvme_id_ns *)buf;
 649         struct pci_child_platdata *pplat;
 650
 651         memset(ns, 0, sizeof(*ns));
 652         ns->dev = ndev;
 653         ns->ns_id = desc->devnum - ndev->blk_dev_start + 1;
 654         if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)id))
 655                 return -EIO;
 656
 657         flbas = id->flbas & NVME_NS_FLBAS_LBA_MASK;
 658         ns->flbas = flbas;
 659         ns->lba_shift = id->lbaf[flbas].ds;
 660         ns->mode_select_num_blocks = le64_to_cpu(id->nsze);
 661         ns->mode_select_block_len = 1 << ns->lba_shift;
 662         list_add(&ns->list, &ndev->namespaces);
 663
 664         desc->lba = ns->mode_select_num_blocks;
 665         desc->log2blksz = ns->lba_shift;
 666         desc->blksz = 1 << ns->lba_shift;
 667         desc->bdev = udev;
 668         pplat = dev_get_parent_platdata(udev->parent);
 669         sprintf(desc->vendor, "0x%.4x", pplat->vendor);
 670         memcpy(desc->product, ndev->serial, sizeof(ndev->serial));
 671         memcpy(desc->revision, ndev->firmware_rev, sizeof(ndev->firmware_rev));
 672         part_init(desc);
 673
 674         return 0;
 675 }
 676
 677 static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr,
 678                          lbaint_t blkcnt, void *buffer, bool read)
 679 {
 680         struct nvme_ns *ns = dev_get_priv(udev);
 681         struct nvme_dev *dev = ns->dev;
 682         struct nvme_command c;
 683         struct blk_desc *desc = dev_get_uclass_platdata(udev);
 684         int status;
 685         u64 prp2;
 686         u64 total_len = blkcnt << desc->log2blksz;
 687         u64 temp_len = total_len;
 688
 689         u64 slba = blknr;
 690         u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift);
 691         u64 total_lbas = blkcnt;
 692
 693         if (!read)
 694                 flush_dcache_range((unsigned long)buffer,
 695                                    (unsigned long)buffer + total_len);
 696
 697         c.rw.opcode = read ? nvme_cmd_read : nvme_cmd_write;
 698         c.rw.flags = 0;
 699         c.rw.nsid = cpu_to_le32(ns->ns_id);
 700         c.rw.control = 0;
 701         c.rw.dsmgmt = 0;
 702         c.rw.reftag = 0;
 703         c.rw.apptag = 0;
 704         c.rw.appmask = 0;
 705         c.rw.metadata = 0;
 706
 707         while (total_lbas) {
 708                 if (total_lbas < lbas) {
 709                         lbas = (u16)total_lbas;
 710                         total_lbas = 0;
 711                 } else {
 712                         total_lbas -= lbas;
 713                 }
 714
 715                 if (nvme_setup_prps(dev, &prp2,
 716                                     lbas << ns->lba_shift, (ulong)buffer))
 717                         return -EIO;
 718                 c.rw.slba = cpu_to_le64(slba);
 719                 slba += lbas;
 720                 c.rw.length = cpu_to_le16(lbas - 1);
 721                 c.rw.prp1 = cpu_to_le64((ulong)buffer);
 722                 c.rw.prp2 = cpu_to_le64(prp2);
 723                 status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q],
 724                                 &c, NULL, IO_TIMEOUT);
 725                 if (status)
 726                         break;
 727                 temp_len -= lbas << ns->lba_shift;
 728                 buffer += lbas << ns->lba_shift;
 729         }
 730
 731         if (read)
 732                 invalidate_dcache_range((unsigned long)buffer,
 733                                         (unsigned long)buffer + total_len);
 734
 735         return (total_len - temp_len) >> desc->log2blksz;
 736 }
 737
 738 static ulong nvme_blk_read(struct udevice *udev, lbaint_t blknr,
 739                            lbaint_t blkcnt, void *buffer)
 740 {
 741         return nvme_blk_rw(udev, blknr, blkcnt, buffer, true);
 742 }
 743
 744 static ulong nvme_blk_write(struct udevice *udev, lbaint_t blknr,
 745                             lbaint_t blkcnt, const void *buffer)
 746 {
 747         return nvme_blk_rw(udev, blknr, blkcnt, (void *)buffer, false);
 748 }
 749
 750 static const struct blk_ops nvme_blk_ops = {
 751         .read   = nvme_blk_read,
 752         .write  = nvme_blk_write,
 753 };
 754
 755 U_BOOT_DRIVER(nvme_blk) = {
 756         .name   = "nvme-blk",
 757         .id     = UCLASS_BLK,
 758         .probe  = nvme_blk_probe,
 759         .ops    = &nvme_blk_ops,
 760         .priv_auto_alloc_size = sizeof(struct nvme_ns),
 761 };
 762
 763 static int nvme_bind(struct udevice *udev)
 764 {
 765         char name[20];
 766         sprintf(name, "nvme#%d", nvme_info->ndev_num++);
 767
 768         return device_set_name(udev, name);
 769 }
 770
 771 static int nvme_probe(struct udevice *udev)
 772 {
 773         int ret;
 774         struct nvme_dev *ndev = dev_get_priv(udev);
 775
 776         ndev->instance = trailing_strtol(udev->name);
 777
 778         INIT_LIST_HEAD(&ndev->namespaces);
 779         ndev->bar = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0,
 780                         PCI_REGION_MEM);
 781         if (readl(&ndev->bar->csts) == -1) {
 782                 ret = -ENODEV;
 783                 printf("Error: %s: Out of memory!\n", udev->name);
 784                 goto free_nvme;
 785         }
 786
 787         ndev->queues = malloc(NVME_Q_NUM * sizeof(struct nvme_queue *));
 788         if (!ndev->queues) {
 789                 ret = -ENOMEM;
 790                 printf("Error: %s: Out of memory!\n", udev->name);
 791                 goto free_nvme;
 792         }
 793         memset(ndev->queues, 0,
 794                sizeof(NVME_Q_NUM * sizeof(struct nvme_queue *)));
 795
 796         ndev->prp_pool = malloc(MAX_PRP_POOL);
 797         if (!ndev->prp_pool) {
 798                 ret = -ENOMEM;
 799                 printf("Error: %s: Out of memory!\n", udev->name);
 800                 goto free_nvme;
 801         }
 802         ndev->prp_entry_num = MAX_PRP_POOL >> 3;
 803
 804         ndev->cap = nvme_readq(&ndev->bar->cap);
 805         ndev->q_depth = min_t(int, NVME_CAP_MQES(ndev->cap) + 1, NVME_Q_DEPTH);
 806         ndev->db_stride = 1 << NVME_CAP_STRIDE(ndev->cap);
 807         ndev->dbs = ((void __iomem *)ndev->bar) + 4096;
 808
 809         ret = nvme_configure_admin_queue(ndev);
 810         if (ret)
 811                 goto free_queue;
 812
 813         ret = nvme_setup_io_queues(ndev);
 814         if (ret)
 815                 goto free_queue;
 816
 817         nvme_get_info_from_identify(ndev);
 818         ndev->blk_dev_start = nvme_info->ns_num;
 819         list_add(&ndev->node, &nvme_info->dev_list);
 820
 821         return 0;
 822
 823 free_queue:
 824         free((void *)ndev->queues);
 825 free_nvme:
 826         return ret;
 827 }
 828
 829 U_BOOT_DRIVER(nvme) = {
 830         .name   = "nvme",
 831         .id     = UCLASS_NVME,
 832         .bind   = nvme_bind,
 833         .probe  = nvme_probe,
 834         .priv_auto_alloc_size = sizeof(struct nvme_dev),
 835 };
 836
 837 struct pci_device_id nvme_supported[] = {
 838         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, ~0) },
 839         {}
 840 };
 841
 842 U_BOOT_PCI_DEVICE(nvme, nvme_supported);