2 * Copyright 2007-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/fsl_serdes.h>
11 DECLARE_GLOBAL_DATA_PTR;
14 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
16 * Initialize controller and call the common driver/pci pci_hose_scan to
17 * scan for bridges and devices.
19 * Hose fields which need to be pre-initialized by board specific code:
29 #include <asm/fsl_pci.h>
31 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
32 #define CONFIG_SYS_PCI_MEMORY_BUS 0
35 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
36 #define CONFIG_SYS_PCI_MEMORY_PHYS 0
39 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
40 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
43 /* Setup one inbound ATMU window.
45 * We let the caller decide what the window size should be
47 static void set_inbound_window(volatile pit_t *pi,
51 u32 sz = (__ilog2_u64(size) - 1);
52 u32 flag = PIWAR_EN | PIWAR_LOCAL |
53 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
55 out_be32(&pi->pitar, r->phys_start >> 12);
56 out_be32(&pi->piwbar, r->bus_start >> 12);
57 #ifdef CONFIG_SYS_PCI_64BIT
58 out_be32(&pi->piwbear, r->bus_start >> 44);
60 out_be32(&pi->piwbear, 0);
62 if (r->flags & PCI_REGION_PREFETCH)
64 out_be32(&pi->piwar, flag | sz);
67 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
69 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
71 /* Reset hose to make sure its in a clean state */
72 memset(hose, 0, sizeof(struct pci_controller));
74 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
76 return fsl_is_pci_agent(hose);
79 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
80 u64 out_lo, u8 pcie_cap,
83 struct pci_region *r = hose->regions + hose->region_count;
84 u64 sz = min((u64)gd->ram_size, (1ull << 32));
86 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
87 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
90 /* we have no space available for inbound memory mapping */
91 if (bus_start > out_lo) {
92 printf ("no space for inbound mapping of memory\n");
97 if ((bus_start + sz) > out_lo) {
98 sz = out_lo - bus_start;
99 debug ("limiting size to %llx\n", sz);
102 pci_sz = 1ull << __ilog2_u64(sz);
104 * we can overlap inbound/outbound windows on PCI-E since RX & TX
107 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
108 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
109 (u64)bus_start, (u64)phys_start, (u64)sz);
110 pci_set_region(r, bus_start, phys_start, sz,
111 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
112 PCI_REGION_PREFETCH);
114 /* if we aren't an exact power of two match, pci_sz is smaller
115 * round it up to the next power of two. We report the actual
116 * size to pci region tracking.
119 sz = 2ull << __ilog2_u64(sz);
121 set_inbound_window(pi--, r++, sz);
122 sz = 0; /* make sure we dont set the R2 window */
124 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
125 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
126 pci_set_region(r, bus_start, phys_start, pci_sz,
127 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
128 PCI_REGION_PREFETCH);
129 set_inbound_window(pi--, r++, pci_sz);
133 phys_start += pci_sz;
135 pci_sz = 1ull << __ilog2_u64(sz);
137 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
138 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
139 pci_set_region(r, bus_start, phys_start, pci_sz,
140 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
141 PCI_REGION_PREFETCH);
142 set_inbound_window(pi--, r++, pci_sz);
145 phys_start += pci_sz;
149 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
151 * On 64-bit capable systems, set up a mapping for all of DRAM
152 * in high pci address space.
154 pci_sz = 1ull << __ilog2_u64(gd->ram_size);
155 /* round up to the next largest power of two */
156 if (gd->ram_size > pci_sz)
157 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
158 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
159 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
160 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
163 CONFIG_SYS_PCI64_MEMORY_BUS,
164 CONFIG_SYS_PCI_MEMORY_PHYS,
166 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
167 PCI_REGION_PREFETCH);
168 set_inbound_window(pi--, r++, pci_sz);
170 pci_sz = 1ull << __ilog2_u64(sz);
172 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
173 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
174 pci_set_region(r, bus_start, phys_start, pci_sz,
175 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
176 PCI_REGION_PREFETCH);
179 phys_start += pci_sz;
180 set_inbound_window(pi--, r++, pci_sz);
184 #ifdef CONFIG_PHYS_64BIT
185 if (sz && (((u64)gd->ram_size) < (1ull << 32)))
186 printf("Was not able to map all of memory via "
187 "inbound windows -- %lld remaining\n", sz);
190 hose->region_count = r - hose->regions;
195 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
196 static void fsl_pcie_boot_master(pit_t *pi)
198 /* configure inbound window for slave's u-boot image */
199 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
200 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
201 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
202 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
203 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
204 struct pci_region r_inbound;
205 u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)
207 pci_set_region(&r_inbound,
208 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
209 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
211 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
213 set_inbound_window(pi--, &r_inbound,
214 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
216 /* configure inbound window for slave's u-boot image */
217 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
218 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
219 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
220 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
221 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
222 pci_set_region(&r_inbound,
223 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
224 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
226 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
228 set_inbound_window(pi--, &r_inbound,
229 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
231 /* configure inbound window for slave's ucode and ENV */
232 debug("PCIEBOOT - MASTER: Inbound window for slave's "
234 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
235 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
236 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
237 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
238 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)
240 pci_set_region(&r_inbound,
241 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
242 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
244 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
246 set_inbound_window(pi--, &r_inbound,
247 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
250 static void fsl_pcie_boot_master_release_slave(int port)
252 unsigned long release_addr;
254 /* now release slave's core 0 */
257 release_addr = CONFIG_SYS_PCIE1_MEM_VIRT
258 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
260 #ifdef CONFIG_SYS_PCIE2_MEM_VIRT
262 release_addr = CONFIG_SYS_PCIE2_MEM_VIRT
263 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
266 #ifdef CONFIG_SYS_PCIE3_MEM_VIRT
268 release_addr = CONFIG_SYS_PCIE3_MEM_VIRT
269 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
276 if (release_addr != 0) {
277 out_be32((void *)release_addr,
278 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
279 debug("PCIEBOOT - MASTER: "
280 "Release slave successfully! Now the slave should start up!\n");
282 debug("PCIEBOOT - MASTER: "
283 "Release slave failed!\n");
288 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
290 u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
291 u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data;
295 int enabled, r, inbound = 0;
298 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
299 struct pci_region *reg = hose->regions + hose->region_count;
300 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
302 /* Initialize ATMU registers based on hose regions and flags */
303 volatile pot_t *po = &pci->pot[1]; /* skip 0 */
306 u64 out_hi = 0, out_lo = -1ULL;
307 u32 pcicsrbar, pcicsrbar_sz;
309 pci_setup_indirect(hose, cfg_addr, cfg_data);
311 block_rev = in_be32(&pci->block_rev1);
312 if (PEX_IP_BLK_REV_2_2 <= block_rev) {
313 pi = &pci->pit[2]; /* 0xDC0 */
315 pi = &pci->pit[3]; /* 0xDE0 */
318 /* Handle setup of outbound windows first */
319 for (r = 0; r < hose->region_count; r++) {
320 unsigned long flags = hose->regions[r].flags;
321 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
323 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
324 if (flags != PCI_REGION_SYS_MEMORY) {
325 u64 start = hose->regions[r].bus_start;
326 u64 end = start + hose->regions[r].size;
328 out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
329 out_be32(&po->potar, start >> 12);
330 #ifdef CONFIG_SYS_PCI_64BIT
331 out_be32(&po->potear, start >> 44);
333 out_be32(&po->potear, 0);
335 if (hose->regions[r].flags & PCI_REGION_IO) {
336 out_be32(&po->powar, POWAR_EN | sz |
337 POWAR_IO_READ | POWAR_IO_WRITE);
339 out_be32(&po->powar, POWAR_EN | sz |
340 POWAR_MEM_READ | POWAR_MEM_WRITE);
341 out_lo = min(start, out_lo);
342 out_hi = max(end, out_hi);
347 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
349 /* setup PCSRBAR/PEXCSRBAR */
350 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
351 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
352 pcicsrbar_sz = ~pcicsrbar_sz + 1;
354 if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
355 (out_lo > 0x100000000ull))
356 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
358 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
359 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
361 out_lo = min(out_lo, (u64)pcicsrbar);
363 debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
365 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
366 pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
367 hose->region_count++;
369 /* see if we are a PCIe or PCI controller */
370 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
372 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
373 /* boot from PCIE --master */
374 char *s = getenv("bootmaster");
376 sprintf(pcie, "PCIE%d", pci_info->pci_num);
378 if (s && (strcmp(s, pcie) == 0)) {
379 debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n",
381 fsl_pcie_boot_master((pit_t *)pi);
384 inbound = fsl_pci_setup_inbound_windows(hose,
385 out_lo, pcie_cap, pi);
389 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
392 for (r = 0; r < hose->region_count; r++)
393 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
394 (u64)hose->regions[r].phys_start,
395 (u64)hose->regions[r].bus_start,
396 (u64)hose->regions[r].size,
397 hose->regions[r].flags);
399 pci_register_hose(hose);
400 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
401 hose->current_busno = hose->first_busno;
403 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
404 out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except
405 * - Master abort (pci)
406 * - Master PERR (pci)
409 pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32);
410 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
411 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
413 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
415 pci_hose_read_config_dword(hose, dev, PCI_LCR, &temp32);
416 temp32 &= ~0x03; /* Disable ASPM */
417 pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32);
420 if (pcie_cap == PCI_CAP_ID_EXP) {
421 if (block_rev >= PEX_IP_BLK_REV_3_0) {
422 #define PEX_CSR0_LTSSM_MASK 0xFC
423 #define PEX_CSR0_LTSSM_SHIFT 2
424 ltssm = (in_be32(&pci->pex_csr0)
425 & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
426 enabled = (ltssm == 0x11) ? 1 : 0;
428 /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */
429 /* enabled = ltssm >= PCI_LTSSM_L0; */
430 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
431 enabled = ltssm >= PCI_LTSSM_L0;
433 #ifdef CONFIG_FSL_PCIE_RESET
436 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
437 /* assert PCIe reset */
438 setbits_be32(&pci->pdb_stat, 0x08000000);
439 (void) in_be32(&pci->pdb_stat);
441 debug(" Asserting PCIe reset @%p = %x\n",
442 &pci->pdb_stat, in_be32(&pci->pdb_stat));
443 /* clear PCIe reset */
444 clrbits_be32(&pci->pdb_stat, 0x08000000);
446 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
447 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
450 debug("....PCIe link error. "
451 "LTSSM=0x%02x.\n", ltssm);
453 enabled = ltssm >= PCI_LTSSM_L0;
455 /* we need to re-write the bar0 since a reset will
458 pci_hose_write_config_dword(hose, dev,
459 PCI_BASE_ADDRESS_0, pcicsrbar);
464 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
466 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
467 temp32 = in_be32(&srds_regs->srdspccr0);
469 if ((temp32 >> 28) == 3) {
472 out_be32(&srds_regs->srdspccr0, 2 << 28);
473 setbits_be32(&pci->pdb_stat, 0x08000000);
474 in_be32(&pci->pdb_stat);
476 clrbits_be32(&pci->pdb_stat, 0x08000000);
478 for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
479 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
482 enabled = ltssm >= PCI_LTSSM_L0;
487 /* Let the user know there's no PCIe link */
488 printf("no link, regs @ 0x%lx\n", pci_info->regs);
489 hose->last_busno = hose->first_busno;
493 out_be32(&pci->pme_msg_det, 0xffffffff);
494 out_be32(&pci->pme_msg_int_en, 0xffffffff);
496 /* Print the negotiated PCIe link width */
497 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
498 printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4,
501 hose->current_busno++; /* Start scan with secondary */
502 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
505 /* Use generic setup_device to initialize standard pci regs,
506 * but do not allocate any windows since any BAR found (such
507 * as PCSRBAR) is not in this cpu's memory space.
509 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
510 hose->pci_prefetch, hose->pci_io);
513 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
514 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
515 temp16 | PCI_COMMAND_MEMORY);
518 #ifndef CONFIG_PCI_NOSCAN
519 if (!fsl_is_pci_agent(hose)) {
520 debug(" Scanning PCI bus %02x\n",
521 hose->current_busno);
522 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
524 debug(" Not scanning PCI bus %02x. PI=%x\n",
525 hose->current_busno, temp8);
526 hose->last_busno = hose->current_busno;
529 /* if we are PCIe - update limit regs and subordinate busno
530 * for the virtual P2P bridge
532 if (pcie_cap == PCI_CAP_ID_EXP) {
533 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
536 hose->last_busno = hose->current_busno;
539 /* Clear all error indications */
540 if (pcie_cap == PCI_CAP_ID_EXP)
541 out_be32(&pci->pme_msg_det, 0xffffffff);
542 out_be32(&pci->pedr, 0xffffffff);
544 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
546 pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff);
549 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
551 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
555 int fsl_is_pci_agent(struct pci_controller *hose)
558 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
560 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
561 if (pcie_cap == PCI_CAP_ID_EXP) {
564 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE,
566 return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
570 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
571 /* Programming Interface (PCI_CLASS_PROG)
572 * 0 == pci host or pcie root-complex,
573 * 1 == pci agent or pcie end-point
575 return (prog_if == FSL_PROG_IF_AGENT);
579 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
580 struct pci_controller *hose, int busno)
582 volatile ccsr_fsl_pci_t *pci;
583 struct pci_region *r;
584 pci_dev_t dev = PCI_BDF(busno,0,0);
587 pci = (ccsr_fsl_pci_t *) pci_info->regs;
589 /* on non-PCIe controllers we don't have pme_msg_det so this code
590 * should do nothing since the read will return 0
592 if (in_be32(&pci->pme_msg_det)) {
593 out_be32(&pci->pme_msg_det, 0xffffffff);
594 debug (" with errors. Clearing. Now 0x%08x",
598 r = hose->regions + hose->region_count;
600 /* outbound memory */
614 hose->region_count = r - hose->regions;
615 hose->first_busno = busno;
617 fsl_pci_init(hose, pci_info);
619 if (fsl_is_pci_agent(hose)) {
620 fsl_pci_config_unlock(hose);
621 hose->last_busno = hose->first_busno;
622 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
624 /* boot from PCIE --master releases slave's core 0 */
625 char *s = getenv("bootmaster");
627 sprintf(pcie, "PCIE%d", pci_info->pci_num);
629 if (s && (strcmp(s, pcie) == 0))
630 fsl_pcie_boot_master_release_slave(pci_info->pci_num);
634 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
635 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
636 "e" : "", pci_info->pci_num,
637 hose->first_busno, hose->last_busno);
639 return(hose->last_busno + 1);
642 /* Enable inbound PCI config cycles for agent/endpoint interface */
643 void fsl_pci_config_unlock(struct pci_controller *hose)
645 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
649 if (!fsl_is_pci_agent(hose))
652 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
653 if (pcie_cap != 0x0) {
654 /* PCIe - set CFG_READY bit of Configuration Ready Register */
655 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
657 /* PCI - clear ACL bit of PBFR */
658 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
660 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
664 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
665 defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4)
666 int fsl_configure_pcie(struct fsl_pci_info *info,
667 struct pci_controller *hose,
668 const char *connected, int busno)
672 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
673 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
675 is_endpoint = fsl_setup_hose(hose, info->regs);
676 printf("PCIe%u: %s", info->pci_num,
677 is_endpoint ? "Endpoint" : "Root Complex");
679 printf(" of %s", connected);
682 return fsl_pci_init_port(info, hose, busno);
685 #if defined(CONFIG_FSL_CORENET)
686 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
687 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1
688 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2
689 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3
690 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4
692 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
693 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
694 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
695 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
697 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
698 #elif defined(CONFIG_MPC85xx)
699 #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
700 #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
701 #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
702 #define _DEVDISR_PCIE4 0
703 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
704 #elif defined(CONFIG_MPC86xx)
705 #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1
706 #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2
707 #define _DEVDISR_PCIE3 0
708 #define _DEVDISR_PCIE4 0
709 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
710 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
712 #error "No defines for DEVDISR_PCIE"
715 /* Implement a dummy function for those platforms w/o SERDES */
716 static const char *__board_serdes_name(enum srds_prtcl device)
719 #ifdef CONFIG_SYS_PCIE1_NAME
721 return CONFIG_SYS_PCIE1_NAME;
723 #ifdef CONFIG_SYS_PCIE2_NAME
725 return CONFIG_SYS_PCIE2_NAME;
727 #ifdef CONFIG_SYS_PCIE3_NAME
729 return CONFIG_SYS_PCIE3_NAME;
731 #ifdef CONFIG_SYS_PCIE4_NAME
733 return CONFIG_SYS_PCIE4_NAME;
742 __attribute__((weak, alias("__board_serdes_name"))) const char *
743 board_serdes_name(enum srds_prtcl device);
745 static u32 devdisr_mask[] = {
752 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
753 struct fsl_pci_info *pci_info)
755 struct pci_controller *hose;
756 int num = dev - PCIE1;
758 hose = calloc(1, sizeof(struct pci_controller));
762 if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) {
763 busno = fsl_configure_pcie(pci_info, hose,
764 board_serdes_name(dev), busno);
766 printf("PCIe%d: disabled\n", num + 1);
772 int fsl_pcie_init_board(int busno)
774 struct fsl_pci_info pci_info;
775 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
779 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
780 addr = &gur->devdisr3;
782 addr = &gur->devdisr;
784 devdisr = in_be32(addr);
787 SET_STD_PCIE_INFO(pci_info, 1);
788 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
790 setbits_be32(addr, _DEVDISR_PCIE1); /* disable */
794 SET_STD_PCIE_INFO(pci_info, 2);
795 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
797 setbits_be32(addr, _DEVDISR_PCIE2); /* disable */
801 SET_STD_PCIE_INFO(pci_info, 3);
802 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
804 setbits_be32(addr, _DEVDISR_PCIE3); /* disable */
808 SET_STD_PCIE_INFO(pci_info, 4);
809 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
811 setbits_be32(addr, _DEVDISR_PCIE4); /* disable */
817 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
818 struct fsl_pci_info *pci_info)
823 int fsl_pcie_init_board(int busno)
829 #ifdef CONFIG_OF_BOARD_SETUP
831 #include <fdt_support.h>
833 void ft_fsl_pci_setup(void *blob, const char *pci_compat,
834 unsigned long ctrl_addr)
838 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
839 struct pci_controller *hose;
841 hose = find_hose_by_cfg_addr((void *)(ctrl_addr));
843 /* convert ctrl_addr to true physical address */
844 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
845 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
847 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
852 /* We assume a cfg_addr not being set means we didn't setup the controller */
853 if ((hose == NULL) || (hose->cfg_addr == NULL)) {
854 fdt_del_node(blob, off);
857 bus_range[1] = hose->last_busno - hose->first_busno;
858 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
859 fdt_pci_dma_ranges(blob, off, hose);