git.sur5r.net Git - u-boot/blob - drivers/pci/fsl_pci_init.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  16  * MA 02111-1307 USA
  17  */
  18
  19 #include <common.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 /*
  24  * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
  25  *
  26  * Initialize controller and call the common driver/pci pci_hose_scan to
  27  * scan for bridges and devices.
  28  *
  29  * Hose fields which need to be pre-initialized by board specific code:
  30  *   regions[]
  31  *   first_busno
  32  *
  33  * Fields updated:
  34  *   last_busno
  35  */
  36
  37 #include <pci.h>
  38 #include <asm/immap_fsl_pci.h>
  39
  40 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
  41                                 pci_dev_t dev, int sub_bus);
  42 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
  43                                 pci_dev_t dev, int sub_bus);
  44 void pciauto_config_init(struct pci_controller *hose);
  45
  46 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
  47 #define CONFIG_SYS_PCI_MEMORY_BUS 0
  48 #endif
  49
  50 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
  51 #define CONFIG_SYS_PCI_MEMORY_PHYS 0
  52 #endif
  53
  54 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
  55 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
  56 #endif
  57
  58 int fsl_pci_setup_inbound_windows(struct pci_region *r)
  59 {
  60         struct pci_region *rgn_base = r;
  61         u64 sz = min((u64)gd->ram_size, 1ull << 32);
  62
  63         phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
  64         pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
  65         pci_size_t pci_sz = 1ull << __ilog2_u64(sz);
  66
  67         debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
  68                 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
  69         pci_set_region(r++, bus_start, phys_start, pci_sz,
  70                         PCI_REGION_MEM | PCI_REGION_MEMORY | \
  71                         PCI_REGION_PREFETCH);
  72
  73         sz -= pci_sz;
  74         bus_start += pci_sz;
  75         phys_start += pci_sz;
  76
  77         pci_sz = 1ull << __ilog2_u64(sz);
  78         if (sz) {
  79                 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
  80                         (u64)bus_start, (u64)phys_start, (u64)pci_sz);
  81                 pci_set_region(r++, bus_start, phys_start, pci_sz,
  82                                 PCI_REGION_MEM | PCI_REGION_MEMORY | \
  83                                 PCI_REGION_PREFETCH);
  84                 sz -= pci_sz;
  85                 bus_start += pci_sz;
  86                 phys_start += pci_sz;
  87         }
  88
  89 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
  90         pci_sz = 1ull << __ilog2_u64(gd->ram_size);
  91         /* round up to the next largest power of two */
  92         if (gd->ram_size > pci_sz)
  93                 sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
  94         debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
  95                 (u64)CONFIG_SYS_PCI_MEMORY_BUS,
  96                 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
  97                 (u64)pci_sz);
  98         pci_set_region(r++,
  99                         CONFIG_SYS_PCI_MEMORY_BUS,
 100                         CONFIG_SYS_PCI_MEMORY_PHYS,
 101                         pci_sz,
 102                         PCI_REGION_MEM | PCI_REGION_MEMORY | \
 103                         PCI_REGION_PREFETCH);
 104 #else
 105         pci_sz = 1ull << __ilog2_u64(sz);
 106         if (sz) {
 107                 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
 108                         (u64)bus_start, (u64)phys_start, (u64)pci_sz);
 109                 pci_set_region(r++, bus_start, phys_start, pci_sz,
 110                                 PCI_REGION_MEM | PCI_REGION_MEMORY | \
 111                                 PCI_REGION_PREFETCH);
 112                 sz -= pci_sz;
 113                 bus_start += pci_sz;
 114                 phys_start += pci_sz;
 115         }
 116 #endif
 117
 118         if (sz && (((u64)gd->ram_size) < (1ull << 32)))
 119                 printf("Was not able to map all of memory via "
 120                         "inbound windows -- %lld remaining\n", sz);
 121
 122         return r - rgn_base;
 123 }
 124
 125 void fsl_pci_init(struct pci_controller *hose)
 126 {
 127         u16 temp16;
 128         u32 temp32;
 129         int busno = hose->first_busno;
 130         int enabled;
 131         u16 ltssm;
 132         u8 temp8;
 133         int r;
 134         int bridge;
 135         int inbound = 0;
 136         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr;
 137         pci_dev_t dev = PCI_BDF(busno,0,0);
 138
 139         /* Initialize ATMU registers based on hose regions and flags */
 140         volatile pot_t *po = &pci->pot[1];      /* skip 0 */
 141         volatile pit_t *pi = &pci->pit[0];      /* ranges from: 3 to 1 */
 142
 143 #ifdef DEBUG
 144         int neg_link_w;
 145 #endif
 146
 147         for (r=0; r<hose->region_count; r++) {
 148                 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
 149                 if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */
 150                         u32 flag = PIWAR_EN | PIWAR_LOCAL | \
 151                                         PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
 152                         pi->pitar = (hose->regions[r].phys_start >> 12);
 153                         pi->piwbar = (hose->regions[r].bus_start >> 12);
 154 #ifdef CONFIG_SYS_PCI_64BIT
 155                         pi->piwbear = (hose->regions[r].bus_start >> 44);
 156 #else
 157                         pi->piwbear = 0;
 158 #endif
 159                         if (hose->regions[r].flags & PCI_REGION_PREFETCH)
 160                                 flag |= PIWAR_PF;
 161                         pi->piwar = flag | sz;
 162                         pi++;
 163                         inbound = hose->regions[r].size > 0;
 164                 } else { /* Outbound */
 165                         po->powbar = (hose->regions[r].phys_start >> 12);
 166                         po->potar = (hose->regions[r].bus_start >> 12);
 167 #ifdef CONFIG_SYS_PCI_64BIT
 168                         po->potear = (hose->regions[r].bus_start >> 44);
 169 #else
 170                         po->potear = 0;
 171 #endif
 172                         if (hose->regions[r].flags & PCI_REGION_IO)
 173                                 po->powar = POWAR_EN | sz | \
 174                                         POWAR_IO_READ | POWAR_IO_WRITE;
 175                         else
 176                                 po->powar = POWAR_EN | sz | \
 177                                         POWAR_MEM_READ | POWAR_MEM_WRITE;
 178                         po++;
 179                 }
 180         }
 181
 182         pci_register_hose(hose);
 183         pciauto_config_init(hose);      /* grab pci_{mem,prefetch,io} */
 184         hose->current_busno = hose->first_busno;
 185
 186         pci->pedr = 0xffffffff;         /* Clear any errors */
 187         pci->peer = ~0x20140;           /* Enable All Error Interupts except
 188                                          * - Master abort (pci)
 189                                          * - Master PERR (pci)
 190                                          * - ICCA (PCIe)
 191                                          */
 192         pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32);
 193         temp32 |= 0xf000e;              /* set URR, FER, NFER (but not CER) */
 194         pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
 195
 196         pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8);
 197         bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */
 198
 199         if ( bridge ) {
 200
 201                 pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
 202                 enabled = ltssm >= PCI_LTSSM_L0;
 203
 204 #ifdef CONFIG_FSL_PCIE_RESET
 205                 if (ltssm == 1) {
 206                         int i;
 207                         debug("....PCIe link error. "
 208                               "LTSSM=0x%02x.", ltssm);
 209                         pci->pdb_stat |= 0x08000000; /* assert PCIe reset */
 210                         temp32 = pci->pdb_stat;
 211                         udelay(100);
 212                         debug("  Asserting PCIe reset @%x = %x\n",
 213                               &pci->pdb_stat, pci->pdb_stat);
 214                         pci->pdb_stat &= ~0x08000000; /* clear reset */
 215                         asm("sync;isync");
 216                         for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
 217                                 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
 218                                                         &ltssm);
 219                                 udelay(1000);
 220                                 debug("....PCIe link error. "
 221                                       "LTSSM=0x%02x.\n", ltssm);
 222                         }
 223                         enabled = ltssm >= PCI_LTSSM_L0;
 224                 }
 225 #endif
 226
 227                 if (!enabled) {
 228                         debug("....PCIE link error.  Skipping scan."
 229                               "LTSSM=0x%02x\n", ltssm);
 230                         hose->last_busno = hose->first_busno;
 231                         return;
 232                 }
 233
 234                 pci->pme_msg_det = 0xffffffff;
 235                 pci->pme_msg_int_en = 0xffffffff;
 236 #ifdef DEBUG
 237                 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
 238                 neg_link_w = (temp16 & 0x3f0 ) >> 4;
 239                 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
 240                       ltssm, neg_link_w);
 241 #endif
 242                 hose->current_busno++; /* Start scan with secondary */
 243                 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 244
 245         }
 246
 247         /* Use generic setup_device to initialize standard pci regs,
 248          * but do not allocate any windows since any BAR found (such
 249          * as PCSRBAR) is not in this cpu's memory space.
 250          */
 251
 252         pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 253                              hose->pci_prefetch, hose->pci_io);
 254
 255         if (inbound) {
 256                 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
 257                 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
 258                                            temp16 | PCI_COMMAND_MEMORY);
 259         }
 260
 261 #ifndef CONFIG_PCI_NOSCAN
 262         pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
 263
 264         /* Programming Interface (PCI_CLASS_PROG)
 265          * 0 == pci host or pcie root-complex,
 266          * 1 == pci agent or pcie end-point
 267          */
 268         if (!temp8) {
 269                 printf("               Scanning PCI bus %02x\n",
 270                         hose->current_busno);
 271                 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
 272         } else {
 273                 debug("               Not scanning PCI bus %02x. PI=%x\n",
 274                         hose->current_busno, temp8);
 275                 hose->last_busno = hose->current_busno;
 276         }
 277
 278         if ( bridge ) { /* update limit regs and subordinate busno */
 279                 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
 280         }
 281 #else
 282         hose->last_busno = hose->current_busno;
 283 #endif
 284
 285         /* Clear all error indications */
 286
 287         if (bridge)
 288                 pci->pme_msg_det = 0xffffffff;
 289         pci->pedr = 0xffffffff;
 290
 291         pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
 292         if (temp16) {
 293                 pci_hose_write_config_word(hose, dev,
 294                                         PCI_DSR, 0xffff);
 295         }
 296
 297         pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
 298         if (temp16) {
 299                 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
 300         }
 301 }
 302
 303 #ifdef CONFIG_OF_BOARD_SETUP
 304 #include <libfdt.h>
 305 #include <fdt_support.h>
 306
 307 void ft_fsl_pci_setup(void *blob, const char *pci_alias,
 308                         struct pci_controller *hose)
 309 {
 310         int off = fdt_path_offset(blob, pci_alias);
 311
 312         if (off >= 0) {
 313                 u32 bus_range[2];
 314
 315                 bus_range[0] = 0;
 316                 bus_range[1] = hose->last_busno - hose->first_busno;
 317                 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
 318                 fdt_pci_dma_ranges(blob, off, hose);
 319         }
 320 }
 321 #endif