2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
5 * SPDX-License-Identifier: GPL-2.0+
17 #include <dm/device-internal.h>
18 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
19 #include <asm/fsp/fsp_support.h>
21 #include "pci_internal.h"
23 DECLARE_GLOBAL_DATA_PTR;
25 static int pci_get_bus(int busnum, struct udevice **busp)
29 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
31 /* Since buses may not be numbered yet try a little harder with bus 0 */
33 ret = uclass_first_device(UCLASS_PCI, busp);
38 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
44 struct pci_controller *pci_bus_to_hose(int busnum)
49 ret = pci_get_bus(busnum, &bus);
51 debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
55 return dev_get_uclass_priv(bus);
58 struct udevice *pci_get_controller(struct udevice *dev)
60 while (device_is_on_pci_bus(dev))
66 pci_dev_t dm_pci_get_bdf(struct udevice *dev)
68 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
69 struct udevice *bus = dev->parent;
71 return PCI_ADD_BUS(bus->seq, pplat->devfn);
75 * pci_get_bus_max() - returns the bus number of the last active bus
77 * @return last bus number, or -1 if no active buses
79 static int pci_get_bus_max(void)
85 ret = uclass_get(UCLASS_PCI, &uc);
86 uclass_foreach_dev(bus, uc) {
91 debug("%s: ret=%d\n", __func__, ret);
96 int pci_last_busno(void)
98 return pci_get_bus_max();
101 int pci_get_ff(enum pci_size_t size)
113 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
114 struct udevice **devp)
118 for (device_find_first_child(bus, &dev);
120 device_find_next_child(&dev)) {
121 struct pci_child_platdata *pplat;
123 pplat = dev_get_parent_platdata(dev);
124 if (pplat && pplat->devfn == find_devfn) {
133 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
138 ret = pci_get_bus(PCI_BUS(bdf), &bus);
141 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
144 static int pci_device_matches_ids(struct udevice *dev,
145 struct pci_device_id *ids)
147 struct pci_child_platdata *pplat;
150 pplat = dev_get_parent_platdata(dev);
153 for (i = 0; ids[i].vendor != 0; i++) {
154 if (pplat->vendor == ids[i].vendor &&
155 pplat->device == ids[i].device)
162 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
163 int *indexp, struct udevice **devp)
167 /* Scan all devices on this bus */
168 for (device_find_first_child(bus, &dev);
170 device_find_next_child(&dev)) {
171 if (pci_device_matches_ids(dev, ids) >= 0) {
172 if ((*indexp)-- <= 0) {
182 int pci_find_device_id(struct pci_device_id *ids, int index,
183 struct udevice **devp)
187 /* Scan all known buses */
188 for (uclass_first_device(UCLASS_PCI, &bus);
190 uclass_next_device(&bus)) {
191 if (!pci_bus_find_devices(bus, ids, &index, devp))
199 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
200 unsigned int device, int *indexp,
201 struct udevice **devp)
203 struct pci_child_platdata *pplat;
206 for (device_find_first_child(bus, &dev);
208 device_find_next_child(&dev)) {
209 pplat = dev_get_parent_platdata(dev);
210 if (pplat->vendor == vendor && pplat->device == device) {
221 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
222 struct udevice **devp)
226 /* Scan all known buses */
227 for (uclass_first_device(UCLASS_PCI, &bus);
229 uclass_next_device(&bus)) {
230 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
231 return device_probe(*devp);
238 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
242 /* Scan all known buses */
243 for (pci_find_first_device(&dev);
245 pci_find_next_device(&dev)) {
246 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
248 if (pplat->class == find_class && !index--) {
250 return device_probe(*devp);
258 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
259 unsigned long value, enum pci_size_t size)
261 struct dm_pci_ops *ops;
263 ops = pci_get_ops(bus);
264 if (!ops->write_config)
266 return ops->write_config(bus, bdf, offset, value, size);
269 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
270 enum pci_size_t size)
275 ret = pci_get_bus(PCI_BUS(bdf), &bus);
279 return pci_bus_write_config(bus, bdf, offset, value, size);
282 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
283 enum pci_size_t size)
287 for (bus = dev; device_is_on_pci_bus(bus);)
289 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
294 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
296 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
299 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
301 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
304 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
306 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
309 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
311 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
314 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
316 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
319 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
321 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
324 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
325 unsigned long *valuep, enum pci_size_t size)
327 struct dm_pci_ops *ops;
329 ops = pci_get_ops(bus);
330 if (!ops->read_config)
332 return ops->read_config(bus, bdf, offset, valuep, size);
335 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
336 enum pci_size_t size)
341 ret = pci_get_bus(PCI_BUS(bdf), &bus);
345 return pci_bus_read_config(bus, bdf, offset, valuep, size);
348 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
349 enum pci_size_t size)
353 for (bus = dev; device_is_on_pci_bus(bus);)
355 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
359 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
364 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
372 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
377 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
385 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
390 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
398 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
403 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
411 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
416 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
424 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
429 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
437 static void set_vga_bridge_bits(struct udevice *dev)
439 struct udevice *parent = dev->parent;
442 while (parent->seq != 0) {
443 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
444 bc |= PCI_BRIDGE_CTL_VGA;
445 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
446 parent = parent->parent;
450 int pci_auto_config_devices(struct udevice *bus)
452 struct pci_controller *hose = bus->uclass_priv;
453 struct pci_child_platdata *pplat;
454 unsigned int sub_bus;
459 debug("%s: start\n", __func__);
460 pciauto_config_init(hose);
461 for (ret = device_find_first_child(bus, &dev);
463 ret = device_find_next_child(&dev)) {
464 unsigned int max_bus;
467 debug("%s: device %s\n", __func__, dev->name);
468 ret = dm_pciauto_config_device(dev);
472 sub_bus = max(sub_bus, max_bus);
474 pplat = dev_get_parent_platdata(dev);
475 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
476 set_vga_bridge_bits(dev);
478 debug("%s: done\n", __func__);
483 int dm_pci_hose_probe_bus(struct udevice *bus)
488 debug("%s\n", __func__);
490 sub_bus = pci_get_bus_max() + 1;
491 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
492 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
494 ret = device_probe(bus);
496 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
500 if (sub_bus != bus->seq) {
501 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
502 __func__, bus->name, bus->seq, sub_bus);
505 sub_bus = pci_get_bus_max();
506 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
512 * pci_match_one_device - Tell if a PCI device structure has a matching
513 * PCI device id structure
514 * @id: single PCI device id structure to match
515 * @dev: the PCI device structure to match against
517 * Returns the matching pci_device_id structure or %NULL if there is no match.
519 static bool pci_match_one_id(const struct pci_device_id *id,
520 const struct pci_device_id *find)
522 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
523 (id->device == PCI_ANY_ID || id->device == find->device) &&
524 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
525 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
526 !((id->class ^ find->class) & id->class_mask))
533 * pci_find_and_bind_driver() - Find and bind the right PCI driver
535 * This only looks at certain fields in the descriptor.
537 * @parent: Parent bus
538 * @find_id: Specification of the driver to find
539 * @bdf: Bus/device/function addreess - see PCI_BDF()
540 * @devp: Returns a pointer to the device created
541 * @return 0 if OK, -EPERM if the device is not needed before relocation and
542 * therefore was not created, other -ve value on error
544 static int pci_find_and_bind_driver(struct udevice *parent,
545 struct pci_device_id *find_id,
546 pci_dev_t bdf, struct udevice **devp)
548 struct pci_driver_entry *start, *entry;
557 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
558 find_id->vendor, find_id->device);
559 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
560 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
561 for (entry = start; entry != start + n_ents; entry++) {
562 const struct pci_device_id *id;
564 const struct driver *drv;
566 for (id = entry->match;
567 id->vendor || id->subvendor || id->class_mask;
569 if (!pci_match_one_id(id, find_id))
575 * In the pre-relocation phase, we only bind devices
576 * whose driver has the DM_FLAG_PRE_RELOC set, to save
577 * precious memory space as on some platforms as that
578 * space is pretty limited (ie: using Cache As RAM).
580 if (!(gd->flags & GD_FLG_RELOC) &&
581 !(drv->flags & DM_FLAG_PRE_RELOC))
585 * We could pass the descriptor to the driver as
586 * platdata (instead of NULL) and allow its bind()
587 * method to return -ENOENT if it doesn't support this
588 * device. That way we could continue the search to
589 * find another driver. For now this doesn't seem
590 * necesssary, so just bind the first match.
592 ret = device_bind(parent, drv, drv->name, NULL, -1,
596 debug("%s: Match found: %s\n", __func__, drv->name);
597 dev->driver_data = find_id->driver_data;
603 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
605 * In the pre-relocation phase, we only bind bridge devices to save
606 * precious memory space as on some platforms as that space is pretty
607 * limited (ie: using Cache As RAM).
609 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
612 /* Bind a generic driver so that the device can be used */
613 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
618 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
620 ret = device_bind_driver(parent, drv, str, devp);
622 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
625 debug("%s: No match found: bound generic driver instead\n", __func__);
630 debug("%s: No match found: error %d\n", __func__, ret);
634 int pci_bind_bus_devices(struct udevice *bus)
636 ulong vendor, device;
643 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
644 PCI_MAX_PCI_FUNCTIONS - 1);
645 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end;
646 bdf += PCI_BDF(0, 0, 1)) {
647 struct pci_child_platdata *pplat;
651 if (PCI_FUNC(bdf) && !found_multi)
653 /* Check only the first access, we don't expect problems */
654 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
655 &header_type, PCI_SIZE_8);
658 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
660 if (vendor == 0xffff || vendor == 0x0000)
664 found_multi = header_type & 0x80;
666 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
667 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
668 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
670 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
674 /* Find this device in the device tree */
675 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
677 /* If nothing in the device tree, bind a device */
678 if (ret == -ENODEV) {
679 struct pci_device_id find_id;
682 memset(&find_id, '\0', sizeof(find_id));
683 find_id.vendor = vendor;
684 find_id.device = device;
685 find_id.class = class;
686 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
687 pci_bus_read_config(bus, bdf,
688 PCI_SUBSYSTEM_VENDOR_ID,
690 find_id.subvendor = val & 0xffff;
691 find_id.subdevice = val >> 16;
693 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
701 /* Update the platform data */
702 pplat = dev_get_parent_platdata(dev);
703 pplat->devfn = PCI_MASK_BUS(bdf);
704 pplat->vendor = vendor;
705 pplat->device = device;
706 pplat->class = class;
711 printf("Cannot read bus configuration: %d\n", ret);
716 static int pci_uclass_post_bind(struct udevice *bus)
719 * If there is no pci device listed in the device tree,
720 * don't bother scanning the device tree.
722 if (bus->of_offset == -1)
726 * Scan the device tree for devices. This does not probe the PCI bus,
727 * as this is not permitted while binding. It just finds devices
728 * mentioned in the device tree.
730 * Before relocation, only bind devices marked for pre-relocation
733 return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
734 gd->flags & GD_FLG_RELOC ? false : true);
737 static int decode_regions(struct pci_controller *hose, const void *blob,
738 int parent_node, int node)
740 int pci_addr_cells, addr_cells, size_cells;
741 phys_addr_t base = 0, size;
742 int cells_per_record;
747 prop = fdt_getprop(blob, node, "ranges", &len);
750 pci_addr_cells = fdt_address_cells(blob, node);
751 addr_cells = fdt_address_cells(blob, parent_node);
752 size_cells = fdt_size_cells(blob, node);
754 /* PCI addresses are always 3-cells */
756 cells_per_record = pci_addr_cells + addr_cells + size_cells;
757 hose->region_count = 0;
758 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
760 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
761 u64 pci_addr, addr, size;
767 if (len < cells_per_record)
769 flags = fdt32_to_cpu(prop[0]);
770 space_code = (flags >> 24) & 3;
771 pci_addr = fdtdec_get_number(prop + 1, 2);
772 prop += pci_addr_cells;
773 addr = fdtdec_get_number(prop, addr_cells);
775 size = fdtdec_get_number(prop, size_cells);
777 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
778 ", size=%" PRIx64 ", space_code=%d\n", __func__,
779 hose->region_count, pci_addr, addr, size, space_code);
780 if (space_code & 2) {
781 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
783 } else if (space_code & 1) {
784 type = PCI_REGION_IO;
789 for (i = 0; i < hose->region_count; i++) {
790 if (hose->regions[i].flags == type)
794 pos = hose->region_count++;
795 debug(" - type=%d, pos=%d\n", type, pos);
796 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
799 /* Add a region for our local memory */
801 #ifdef CONFIG_SYS_SDRAM_BASE
802 base = CONFIG_SYS_SDRAM_BASE;
804 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
805 size = gd->pci_ram_top - base;
806 pci_set_region(hose->regions + hose->region_count++, base, base,
807 size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
812 static int pci_uclass_pre_probe(struct udevice *bus)
814 struct pci_controller *hose;
817 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
819 hose = bus->uclass_priv;
821 /* For bridges, use the top-level PCI controller */
822 if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
824 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
827 debug("%s: Cannot decode regions\n", __func__);
831 struct pci_controller *parent_hose;
833 parent_hose = dev_get_uclass_priv(bus->parent);
834 hose->ctlr = parent_hose->bus;
837 hose->first_busno = bus->seq;
838 hose->last_busno = bus->seq;
843 static int pci_uclass_post_probe(struct udevice *bus)
847 debug("%s: probing bus %d\n", __func__, bus->seq);
848 ret = pci_bind_bus_devices(bus);
852 #ifdef CONFIG_PCI_PNP
853 ret = pci_auto_config_devices(bus);
858 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
860 * Per Intel FSP specification, we should call FSP notify API to
861 * inform FSP that PCI enumeration has been done so that FSP will
862 * do any necessary initialization as required by the chipset's
863 * BIOS Writer's Guide (BWG).
865 * Unfortunately we have to put this call here as with driver model,
866 * the enumeration is all done on a lazy basis as needed, so until
867 * something is touched on PCI it won't happen.
869 * Note we only call this 1) after U-Boot is relocated, and 2)
870 * root bus has finished probing.
872 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
873 ret = fsp_init_phase_pci();
882 static int pci_uclass_child_post_bind(struct udevice *dev)
884 struct pci_child_platdata *pplat;
885 struct fdt_pci_addr addr;
888 if (dev->of_offset == -1)
892 * We could read vendor, device, class if available. But for now we
893 * just check the address.
895 pplat = dev_get_parent_platdata(dev);
896 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
897 FDT_PCI_SPACE_CONFIG, "reg", &addr);
903 /* extract the devfn from fdt_pci_addr */
904 pplat->devfn = addr.phys_hi & 0xff00;
910 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
911 uint offset, ulong *valuep,
912 enum pci_size_t size)
914 struct pci_controller *hose = bus->uclass_priv;
916 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
919 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
920 uint offset, ulong value,
921 enum pci_size_t size)
923 struct pci_controller *hose = bus->uclass_priv;
925 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
928 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
934 * Scan through all the PCI controllers. On x86 there will only be one
935 * but that is not necessarily true on other hardware.
938 device_find_first_child(bus, &dev);
943 ret = uclass_next_device(&bus);
951 int pci_find_next_device(struct udevice **devp)
953 struct udevice *child = *devp;
954 struct udevice *bus = child->parent;
957 /* First try all the siblings */
960 device_find_next_child(&child);
967 /* We ran out of siblings. Try the next bus */
968 ret = uclass_next_device(&bus);
972 return bus ? skip_to_next_device(bus, devp) : 0;
975 int pci_find_first_device(struct udevice **devp)
981 ret = uclass_first_device(UCLASS_PCI, &bus);
985 return skip_to_next_device(bus, devp);
988 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
992 return (value >> ((offset & 3) * 8)) & 0xff;
994 return (value >> ((offset & 2) * 8)) & 0xffff;
1000 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1001 enum pci_size_t size)
1004 uint val_mask, shift;
1019 shift = (offset & off_mask) * 8;
1020 ldata = (value & val_mask) << shift;
1021 mask = val_mask << shift;
1022 value = (old & ~mask) | ldata;
1027 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1028 struct pci_region **memp, struct pci_region **prefp)
1030 struct udevice *bus = pci_get_controller(dev);
1031 struct pci_controller *hose = dev_get_uclass_priv(bus);
1037 for (i = 0; i < hose->region_count; i++) {
1038 switch (hose->regions[i].flags) {
1040 if (!*iop || (*iop)->size < hose->regions[i].size)
1041 *iop = hose->regions + i;
1043 case PCI_REGION_MEM:
1044 if (!*memp || (*memp)->size < hose->regions[i].size)
1045 *memp = hose->regions + i;
1047 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1048 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1049 *prefp = hose->regions + i;
1054 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1057 u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1062 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1063 dm_pci_read_config32(dev, bar, &addr);
1064 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1065 return addr & PCI_BASE_ADDRESS_IO_MASK;
1067 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1070 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1071 pci_addr_t bus_addr, unsigned long flags,
1072 unsigned long skip_mask, phys_addr_t *pa)
1074 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1075 struct pci_region *res;
1078 for (i = 0; i < hose->region_count; i++) {
1079 res = &hose->regions[i];
1081 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1084 if (res->flags & skip_mask)
1087 if (bus_addr >= res->bus_start &&
1088 (bus_addr - res->bus_start) < res->size) {
1089 *pa = (bus_addr - res->bus_start + res->phys_start);
1097 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1098 unsigned long flags)
1100 phys_addr_t phys_addr = 0;
1101 struct udevice *ctlr;
1104 /* The root controller has the region information */
1105 ctlr = pci_get_controller(dev);
1108 * if PCI_REGION_MEM is set we do a two pass search with preference
1109 * on matches that don't have PCI_REGION_SYS_MEMORY set
1111 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1112 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1113 flags, PCI_REGION_SYS_MEMORY,
1119 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1122 puts("pci_hose_bus_to_phys: invalid physical address\n");
1127 int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1128 unsigned long flags, unsigned long skip_mask,
1131 struct pci_region *res;
1132 struct udevice *ctlr;
1133 pci_addr_t bus_addr;
1135 struct pci_controller *hose;
1137 /* The root controller has the region information */
1138 ctlr = pci_get_controller(dev);
1139 hose = dev_get_uclass_priv(ctlr);
1141 for (i = 0; i < hose->region_count; i++) {
1142 res = &hose->regions[i];
1144 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1147 if (res->flags & skip_mask)
1150 bus_addr = phys_addr - res->phys_start + res->bus_start;
1152 if (bus_addr >= res->bus_start &&
1153 (bus_addr - res->bus_start) < res->size) {
1162 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1163 unsigned long flags)
1165 pci_addr_t bus_addr = 0;
1169 * if PCI_REGION_MEM is set we do a two pass search with preference
1170 * on matches that don't have PCI_REGION_SYS_MEMORY set
1172 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1173 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1174 PCI_REGION_SYS_MEMORY, &bus_addr);
1179 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1182 puts("pci_hose_phys_to_bus: invalid physical address\n");
1187 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1189 pci_addr_t pci_bus_addr;
1192 /* read BAR address */
1193 dm_pci_read_config32(dev, bar, &bar_response);
1194 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1197 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1198 * isn't actualy used on any platform because u-boot assumes a static
1199 * linear mapping. In the future, this could read the BAR size
1200 * and pass that as the size if needed.
1202 return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1205 UCLASS_DRIVER(pci) = {
1208 .flags = DM_UC_FLAG_SEQ_ALIAS,
1209 .post_bind = pci_uclass_post_bind,
1210 .pre_probe = pci_uclass_pre_probe,
1211 .post_probe = pci_uclass_post_probe,
1212 .child_post_bind = pci_uclass_child_post_bind,
1213 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1214 .per_child_platdata_auto_alloc_size =
1215 sizeof(struct pci_child_platdata),
1218 static const struct dm_pci_ops pci_bridge_ops = {
1219 .read_config = pci_bridge_read_config,
1220 .write_config = pci_bridge_write_config,
1223 static const struct udevice_id pci_bridge_ids[] = {
1224 { .compatible = "pci-bridge" },
1228 U_BOOT_DRIVER(pci_bridge_drv) = {
1229 .name = "pci_bridge_drv",
1231 .of_match = pci_bridge_ids,
1232 .ops = &pci_bridge_ops,
1235 UCLASS_DRIVER(pci_generic) = {
1236 .id = UCLASS_PCI_GENERIC,
1237 .name = "pci_generic",
1240 static const struct udevice_id pci_generic_ids[] = {
1241 { .compatible = "pci-generic" },
1245 U_BOOT_DRIVER(pci_generic_drv) = {
1246 .name = "pci_generic_drv",
1247 .id = UCLASS_PCI_GENERIC,
1248 .of_match = pci_generic_ids,