2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <dm/device-internal.h>
17 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
18 #include <asm/fsp/fsp_support.h>
20 #include "pci_internal.h"
22 DECLARE_GLOBAL_DATA_PTR;
24 static int pci_get_bus(int busnum, struct udevice **busp)
28 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
30 /* Since buses may not be numbered yet try a little harder with bus 0 */
32 ret = uclass_first_device(UCLASS_PCI, busp);
37 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
43 struct pci_controller *pci_bus_to_hose(int busnum)
48 ret = pci_get_bus(busnum, &bus);
50 debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
54 return dev_get_uclass_priv(bus);
57 struct udevice *pci_get_controller(struct udevice *dev)
59 while (device_is_on_pci_bus(dev))
65 pci_dev_t dm_pci_get_bdf(struct udevice *dev)
67 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
68 struct udevice *bus = dev->parent;
70 return PCI_ADD_BUS(bus->seq, pplat->devfn);
74 * pci_get_bus_max() - returns the bus number of the last active bus
76 * @return last bus number, or -1 if no active buses
78 static int pci_get_bus_max(void)
84 ret = uclass_get(UCLASS_PCI, &uc);
85 uclass_foreach_dev(bus, uc) {
90 debug("%s: ret=%d\n", __func__, ret);
95 int pci_last_busno(void)
97 return pci_get_bus_max();
100 int pci_get_ff(enum pci_size_t size)
112 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
113 struct udevice **devp)
117 for (device_find_first_child(bus, &dev);
119 device_find_next_child(&dev)) {
120 struct pci_child_platdata *pplat;
122 pplat = dev_get_parent_platdata(dev);
123 if (pplat && pplat->devfn == find_devfn) {
132 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
137 ret = pci_get_bus(PCI_BUS(bdf), &bus);
140 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
143 static int pci_device_matches_ids(struct udevice *dev,
144 struct pci_device_id *ids)
146 struct pci_child_platdata *pplat;
149 pplat = dev_get_parent_platdata(dev);
152 for (i = 0; ids[i].vendor != 0; i++) {
153 if (pplat->vendor == ids[i].vendor &&
154 pplat->device == ids[i].device)
161 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
162 int *indexp, struct udevice **devp)
166 /* Scan all devices on this bus */
167 for (device_find_first_child(bus, &dev);
169 device_find_next_child(&dev)) {
170 if (pci_device_matches_ids(dev, ids) >= 0) {
171 if ((*indexp)-- <= 0) {
181 int pci_find_device_id(struct pci_device_id *ids, int index,
182 struct udevice **devp)
186 /* Scan all known buses */
187 for (uclass_first_device(UCLASS_PCI, &bus);
189 uclass_next_device(&bus)) {
190 if (!pci_bus_find_devices(bus, ids, &index, devp))
198 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
199 unsigned int device, int *indexp,
200 struct udevice **devp)
202 struct pci_child_platdata *pplat;
205 for (device_find_first_child(bus, &dev);
207 device_find_next_child(&dev)) {
208 pplat = dev_get_parent_platdata(dev);
209 if (pplat->vendor == vendor && pplat->device == device) {
220 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
221 struct udevice **devp)
225 /* Scan all known buses */
226 for (uclass_first_device(UCLASS_PCI, &bus);
228 uclass_next_device(&bus)) {
229 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
230 return device_probe(*devp);
237 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
241 /* Scan all known buses */
242 for (pci_find_first_device(&dev);
244 pci_find_next_device(&dev)) {
245 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
247 if (pplat->class == find_class && !index--) {
249 return device_probe(*devp);
257 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
258 unsigned long value, enum pci_size_t size)
260 struct dm_pci_ops *ops;
262 ops = pci_get_ops(bus);
263 if (!ops->write_config)
265 return ops->write_config(bus, bdf, offset, value, size);
268 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
269 enum pci_size_t size)
274 ret = pci_get_bus(PCI_BUS(bdf), &bus);
278 return pci_bus_write_config(bus, bdf, offset, value, size);
281 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
282 enum pci_size_t size)
286 for (bus = dev; device_is_on_pci_bus(bus);)
288 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
293 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
295 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
298 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
300 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
303 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
305 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
308 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
310 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
313 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
315 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
318 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
320 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
323 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
324 unsigned long *valuep, enum pci_size_t size)
326 struct dm_pci_ops *ops;
328 ops = pci_get_ops(bus);
329 if (!ops->read_config)
331 return ops->read_config(bus, bdf, offset, valuep, size);
334 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
335 enum pci_size_t size)
340 ret = pci_get_bus(PCI_BUS(bdf), &bus);
344 return pci_bus_read_config(bus, bdf, offset, valuep, size);
347 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
348 enum pci_size_t size)
352 for (bus = dev; device_is_on_pci_bus(bus);)
354 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
358 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
363 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
371 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
376 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
384 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
389 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
397 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
402 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
410 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
415 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
423 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
428 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
436 static void set_vga_bridge_bits(struct udevice *dev)
438 struct udevice *parent = dev->parent;
441 while (parent->seq != 0) {
442 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
443 bc |= PCI_BRIDGE_CTL_VGA;
444 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
445 parent = parent->parent;
449 int pci_auto_config_devices(struct udevice *bus)
451 struct pci_controller *hose = bus->uclass_priv;
452 struct pci_child_platdata *pplat;
453 unsigned int sub_bus;
458 debug("%s: start\n", __func__);
459 pciauto_config_init(hose);
460 for (ret = device_find_first_child(bus, &dev);
462 ret = device_find_next_child(&dev)) {
463 unsigned int max_bus;
466 debug("%s: device %s\n", __func__, dev->name);
467 ret = dm_pciauto_config_device(dev);
471 sub_bus = max(sub_bus, max_bus);
473 pplat = dev_get_parent_platdata(dev);
474 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
475 set_vga_bridge_bits(dev);
477 debug("%s: done\n", __func__);
482 int dm_pci_hose_probe_bus(struct udevice *bus)
487 debug("%s\n", __func__);
489 sub_bus = pci_get_bus_max() + 1;
490 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
491 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
493 ret = device_probe(bus);
495 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
499 if (sub_bus != bus->seq) {
500 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
501 __func__, bus->name, bus->seq, sub_bus);
504 sub_bus = pci_get_bus_max();
505 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
511 * pci_match_one_device - Tell if a PCI device structure has a matching
512 * PCI device id structure
513 * @id: single PCI device id structure to match
514 * @dev: the PCI device structure to match against
516 * Returns the matching pci_device_id structure or %NULL if there is no match.
518 static bool pci_match_one_id(const struct pci_device_id *id,
519 const struct pci_device_id *find)
521 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
522 (id->device == PCI_ANY_ID || id->device == find->device) &&
523 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
524 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
525 !((id->class ^ find->class) & id->class_mask))
532 * pci_find_and_bind_driver() - Find and bind the right PCI driver
534 * This only looks at certain fields in the descriptor.
536 * @parent: Parent bus
537 * @find_id: Specification of the driver to find
538 * @bdf: Bus/device/function addreess - see PCI_BDF()
539 * @devp: Returns a pointer to the device created
540 * @return 0 if OK, -EPERM if the device is not needed before relocation and
541 * therefore was not created, other -ve value on error
543 static int pci_find_and_bind_driver(struct udevice *parent,
544 struct pci_device_id *find_id,
545 pci_dev_t bdf, struct udevice **devp)
547 struct pci_driver_entry *start, *entry;
556 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
557 find_id->vendor, find_id->device);
558 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
559 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
560 for (entry = start; entry != start + n_ents; entry++) {
561 const struct pci_device_id *id;
563 const struct driver *drv;
565 for (id = entry->match;
566 id->vendor || id->subvendor || id->class_mask;
568 if (!pci_match_one_id(id, find_id))
574 * In the pre-relocation phase, we only bind devices
575 * whose driver has the DM_FLAG_PRE_RELOC set, to save
576 * precious memory space as on some platforms as that
577 * space is pretty limited (ie: using Cache As RAM).
579 if (!(gd->flags & GD_FLG_RELOC) &&
580 !(drv->flags & DM_FLAG_PRE_RELOC))
584 * We could pass the descriptor to the driver as
585 * platdata (instead of NULL) and allow its bind()
586 * method to return -ENOENT if it doesn't support this
587 * device. That way we could continue the search to
588 * find another driver. For now this doesn't seem
589 * necesssary, so just bind the first match.
591 ret = device_bind(parent, drv, drv->name, NULL, -1,
595 debug("%s: Match found: %s\n", __func__, drv->name);
596 dev->driver_data = find_id->driver_data;
602 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
604 * In the pre-relocation phase, we only bind bridge devices to save
605 * precious memory space as on some platforms as that space is pretty
606 * limited (ie: using Cache As RAM).
608 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
611 /* Bind a generic driver so that the device can be used */
612 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
617 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
619 ret = device_bind_driver(parent, drv, str, devp);
621 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
624 debug("%s: No match found: bound generic driver instead\n", __func__);
629 debug("%s: No match found: error %d\n", __func__, ret);
633 int pci_bind_bus_devices(struct udevice *bus)
635 ulong vendor, device;
642 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
643 PCI_MAX_PCI_FUNCTIONS - 1);
644 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end;
645 bdf += PCI_BDF(0, 0, 1)) {
646 struct pci_child_platdata *pplat;
650 if (PCI_FUNC(bdf) && !found_multi)
652 /* Check only the first access, we don't expect problems */
653 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
654 &header_type, PCI_SIZE_8);
657 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
659 if (vendor == 0xffff || vendor == 0x0000)
663 found_multi = header_type & 0x80;
665 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
666 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
667 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
669 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
673 /* Find this device in the device tree */
674 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
676 /* Search for a driver */
678 /* If nothing in the device tree, bind a generic device */
679 if (ret == -ENODEV) {
680 struct pci_device_id find_id;
683 memset(&find_id, '\0', sizeof(find_id));
684 find_id.vendor = vendor;
685 find_id.device = device;
686 find_id.class = class;
687 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
688 pci_bus_read_config(bus, bdf,
689 PCI_SUBSYSTEM_VENDOR_ID,
691 find_id.subvendor = val & 0xffff;
692 find_id.subdevice = val >> 16;
694 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
702 /* Update the platform data */
703 pplat = dev_get_parent_platdata(dev);
704 pplat->devfn = PCI_MASK_BUS(bdf);
705 pplat->vendor = vendor;
706 pplat->device = device;
707 pplat->class = class;
712 printf("Cannot read bus configuration: %d\n", ret);
717 static int pci_uclass_post_bind(struct udevice *bus)
720 * If there is no pci device listed in the device tree,
721 * don't bother scanning the device tree.
723 if (bus->of_offset == -1)
727 * Scan the device tree for devices. This does not probe the PCI bus,
728 * as this is not permitted while binding. It just finds devices
729 * mentioned in the device tree.
731 * Before relocation, only bind devices marked for pre-relocation
734 return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
735 gd->flags & GD_FLG_RELOC ? false : true);
738 static int decode_regions(struct pci_controller *hose, const void *blob,
739 int parent_node, int node)
741 int pci_addr_cells, addr_cells, size_cells;
742 phys_addr_t base = 0, size;
743 int cells_per_record;
748 prop = fdt_getprop(blob, node, "ranges", &len);
751 pci_addr_cells = fdt_address_cells(blob, node);
752 addr_cells = fdt_address_cells(blob, parent_node);
753 size_cells = fdt_size_cells(blob, node);
755 /* PCI addresses are always 3-cells */
757 cells_per_record = pci_addr_cells + addr_cells + size_cells;
758 hose->region_count = 0;
759 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
761 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
762 u64 pci_addr, addr, size;
768 if (len < cells_per_record)
770 flags = fdt32_to_cpu(prop[0]);
771 space_code = (flags >> 24) & 3;
772 pci_addr = fdtdec_get_number(prop + 1, 2);
773 prop += pci_addr_cells;
774 addr = fdtdec_get_number(prop, addr_cells);
776 size = fdtdec_get_number(prop, size_cells);
778 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
779 ", size=%" PRIx64 ", space_code=%d\n", __func__,
780 hose->region_count, pci_addr, addr, size, space_code);
781 if (space_code & 2) {
782 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
784 } else if (space_code & 1) {
785 type = PCI_REGION_IO;
790 for (i = 0; i < hose->region_count; i++) {
791 if (hose->regions[i].flags == type)
795 pos = hose->region_count++;
796 debug(" - type=%d, pos=%d\n", type, pos);
797 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
800 /* Add a region for our local memory */
802 #ifdef CONFIG_SYS_SDRAM_BASE
803 base = CONFIG_SYS_SDRAM_BASE;
805 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
806 size = gd->pci_ram_top - base;
807 pci_set_region(hose->regions + hose->region_count++, base, base,
808 size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
813 static int pci_uclass_pre_probe(struct udevice *bus)
815 struct pci_controller *hose;
818 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
820 hose = bus->uclass_priv;
822 /* For bridges, use the top-level PCI controller */
823 if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
825 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
828 debug("%s: Cannot decode regions\n", __func__);
832 struct pci_controller *parent_hose;
834 parent_hose = dev_get_uclass_priv(bus->parent);
835 hose->ctlr = parent_hose->bus;
838 hose->first_busno = bus->seq;
839 hose->last_busno = bus->seq;
844 static int pci_uclass_post_probe(struct udevice *bus)
848 debug("%s: probing bus %d\n", __func__, bus->seq);
849 ret = pci_bind_bus_devices(bus);
853 #ifdef CONFIG_PCI_PNP
854 ret = pci_auto_config_devices(bus);
859 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
861 * Per Intel FSP specification, we should call FSP notify API to
862 * inform FSP that PCI enumeration has been done so that FSP will
863 * do any necessary initialization as required by the chipset's
864 * BIOS Writer's Guide (BWG).
866 * Unfortunately we have to put this call here as with driver model,
867 * the enumeration is all done on a lazy basis as needed, so until
868 * something is touched on PCI it won't happen.
870 * Note we only call this 1) after U-Boot is relocated, and 2)
871 * root bus has finished probing.
873 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
874 ret = fsp_init_phase_pci();
883 static int pci_uclass_child_post_bind(struct udevice *dev)
885 struct pci_child_platdata *pplat;
886 struct fdt_pci_addr addr;
889 if (dev->of_offset == -1)
893 * We could read vendor, device, class if available. But for now we
894 * just check the address.
896 pplat = dev_get_parent_platdata(dev);
897 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
898 FDT_PCI_SPACE_CONFIG, "reg", &addr);
904 /* extract the devfn from fdt_pci_addr */
905 pplat->devfn = addr.phys_hi & 0xff00;
911 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
912 uint offset, ulong *valuep,
913 enum pci_size_t size)
915 struct pci_controller *hose = bus->uclass_priv;
917 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
920 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
921 uint offset, ulong value,
922 enum pci_size_t size)
924 struct pci_controller *hose = bus->uclass_priv;
926 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
929 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
935 * Scan through all the PCI controllers. On x86 there will only be one
936 * but that is not necessarily true on other hardware.
939 device_find_first_child(bus, &dev);
944 ret = uclass_next_device(&bus);
952 int pci_find_next_device(struct udevice **devp)
954 struct udevice *child = *devp;
955 struct udevice *bus = child->parent;
958 /* First try all the siblings */
961 device_find_next_child(&child);
968 /* We ran out of siblings. Try the next bus */
969 ret = uclass_next_device(&bus);
973 return bus ? skip_to_next_device(bus, devp) : 0;
976 int pci_find_first_device(struct udevice **devp)
982 ret = uclass_first_device(UCLASS_PCI, &bus);
986 return skip_to_next_device(bus, devp);
989 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
993 return (value >> ((offset & 3) * 8)) & 0xff;
995 return (value >> ((offset & 2) * 8)) & 0xffff;
1001 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1002 enum pci_size_t size)
1005 uint val_mask, shift;
1020 shift = (offset & off_mask) * 8;
1021 ldata = (value & val_mask) << shift;
1022 mask = val_mask << shift;
1023 value = (old & ~mask) | ldata;
1028 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1029 struct pci_region **memp, struct pci_region **prefp)
1031 struct udevice *bus = pci_get_controller(dev);
1032 struct pci_controller *hose = dev_get_uclass_priv(bus);
1038 for (i = 0; i < hose->region_count; i++) {
1039 switch (hose->regions[i].flags) {
1041 if (!*iop || (*iop)->size < hose->regions[i].size)
1042 *iop = hose->regions + i;
1044 case PCI_REGION_MEM:
1045 if (!*memp || (*memp)->size < hose->regions[i].size)
1046 *memp = hose->regions + i;
1048 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1049 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1050 *prefp = hose->regions + i;
1055 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1058 u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1063 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1064 dm_pci_read_config32(dev, bar, &addr);
1065 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1066 return addr & PCI_BASE_ADDRESS_IO_MASK;
1068 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1071 UCLASS_DRIVER(pci) = {
1074 .flags = DM_UC_FLAG_SEQ_ALIAS,
1075 .post_bind = pci_uclass_post_bind,
1076 .pre_probe = pci_uclass_pre_probe,
1077 .post_probe = pci_uclass_post_probe,
1078 .child_post_bind = pci_uclass_child_post_bind,
1079 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1080 .per_child_platdata_auto_alloc_size =
1081 sizeof(struct pci_child_platdata),
1084 static const struct dm_pci_ops pci_bridge_ops = {
1085 .read_config = pci_bridge_read_config,
1086 .write_config = pci_bridge_write_config,
1089 static const struct udevice_id pci_bridge_ids[] = {
1090 { .compatible = "pci-bridge" },
1094 U_BOOT_DRIVER(pci_bridge_drv) = {
1095 .name = "pci_bridge_drv",
1097 .of_match = pci_bridge_ids,
1098 .ops = &pci_bridge_ops,
1101 UCLASS_DRIVER(pci_generic) = {
1102 .id = UCLASS_PCI_GENERIC,
1103 .name = "pci_generic",
1106 static const struct udevice_id pci_generic_ids[] = {
1107 { .compatible = "pci-generic" },
1111 U_BOOT_DRIVER(pci_generic_drv) = {
1112 .name = "pci_generic_drv",
1113 .id = UCLASS_PCI_GENERIC,
1114 .of_match = pci_generic_ids,