2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <dm/device-internal.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 struct pci_controller *pci_bus_to_hose(int busnum)
25 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
27 debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
30 return dev_get_uclass_priv(bus);
33 pci_dev_t pci_get_bdf(struct udevice *dev)
35 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
36 struct udevice *bus = dev->parent;
38 return PCI_ADD_BUS(bus->seq, pplat->devfn);
42 * pci_get_bus_max() - returns the bus number of the last active bus
44 * @return last bus number, or -1 if no active buses
46 static int pci_get_bus_max(void)
52 ret = uclass_get(UCLASS_PCI, &uc);
53 uclass_foreach_dev(bus, uc) {
58 debug("%s: ret=%d\n", __func__, ret);
63 int pci_last_busno(void)
65 struct pci_controller *hose;
70 debug("pci_last_busno\n");
71 ret = uclass_get(UCLASS_PCI, &uc);
72 if (ret || list_empty(&uc->dev_head))
75 /* Probe the last bus */
76 bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node);
77 debug("bus = %p, %s\n", bus, bus->name);
79 ret = device_probe(bus);
83 /* If that bus has bridges, we may have new buses now. Get the last */
84 bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node);
85 hose = dev_get_uclass_priv(bus);
86 debug("bus = %s, hose = %p\n", bus->name, hose);
88 return hose->last_busno;
91 int pci_get_ff(enum pci_size_t size)
103 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
104 struct udevice **devp)
108 for (device_find_first_child(bus, &dev);
110 device_find_next_child(&dev)) {
111 struct pci_child_platdata *pplat;
113 pplat = dev_get_parent_platdata(dev);
114 if (pplat && pplat->devfn == find_devfn) {
123 int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
128 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus);
131 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
134 static int pci_device_matches_ids(struct udevice *dev,
135 struct pci_device_id *ids)
137 struct pci_child_platdata *pplat;
140 pplat = dev_get_parent_platdata(dev);
143 for (i = 0; ids[i].vendor != 0; i++) {
144 if (pplat->vendor == ids[i].vendor &&
145 pplat->device == ids[i].device)
152 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
153 int *indexp, struct udevice **devp)
157 /* Scan all devices on this bus */
158 for (device_find_first_child(bus, &dev);
160 device_find_next_child(&dev)) {
161 if (pci_device_matches_ids(dev, ids) >= 0) {
162 if ((*indexp)-- <= 0) {
172 int pci_find_device_id(struct pci_device_id *ids, int index,
173 struct udevice **devp)
177 /* Scan all known buses */
178 for (uclass_first_device(UCLASS_PCI, &bus);
180 uclass_next_device(&bus)) {
181 if (!pci_bus_find_devices(bus, ids, &index, devp))
189 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
190 unsigned long value, enum pci_size_t size)
192 struct dm_pci_ops *ops;
194 ops = pci_get_ops(bus);
195 if (!ops->write_config)
197 return ops->write_config(bus, bdf, offset, value, size);
200 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
201 enum pci_size_t size)
206 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus);
210 return pci_bus_write_config(bus, bdf, offset, value, size);
213 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
214 enum pci_size_t size)
218 for (bus = dev; device_get_uclass_id(bus->parent) == UCLASS_PCI;)
220 return pci_bus_write_config(bus, pci_get_bdf(dev), offset, value, size);
224 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
226 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
229 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
231 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
234 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
236 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
239 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
241 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
244 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
246 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
249 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
251 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
254 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
255 unsigned long *valuep, enum pci_size_t size)
257 struct dm_pci_ops *ops;
259 ops = pci_get_ops(bus);
260 if (!ops->read_config)
262 return ops->read_config(bus, bdf, offset, valuep, size);
265 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
266 enum pci_size_t size)
271 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus);
275 return pci_bus_read_config(bus, bdf, offset, valuep, size);
278 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
279 enum pci_size_t size)
283 for (bus = dev; device_get_uclass_id(bus->parent) == UCLASS_PCI;)
285 return pci_bus_read_config(bus, pci_get_bdf(dev), offset, valuep,
289 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
294 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
302 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
307 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
315 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
320 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
328 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
333 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
341 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
346 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
354 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
359 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
367 int pci_auto_config_devices(struct udevice *bus)
369 struct pci_controller *hose = bus->uclass_priv;
370 unsigned int sub_bus;
375 debug("%s: start\n", __func__);
376 pciauto_config_init(hose);
377 for (ret = device_find_first_child(bus, &dev);
379 ret = device_find_next_child(&dev)) {
380 unsigned int max_bus;
382 debug("%s: device %s\n", __func__, dev->name);
383 max_bus = pciauto_config_device(hose, pci_get_bdf(dev));
384 sub_bus = max(sub_bus, max_bus);
386 debug("%s: done\n", __func__);
391 int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf)
393 struct udevice *parent, *bus;
397 debug("%s\n", __func__);
400 /* Find the bus within the parent */
401 ret = pci_bus_find_devfn(parent, PCI_MASK_BUS(bdf), &bus);
403 debug("%s: Cannot find device %x on bus %s: %d\n", __func__,
404 bdf, parent->name, ret);
408 sub_bus = pci_get_bus_max() + 1;
409 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
410 pciauto_prescan_setup_bridge(hose, bdf, sub_bus);
412 ret = device_probe(bus);
414 debug("%s: Cannot probe bus bus %s: %d\n", __func__, bus->name,
418 if (sub_bus != bus->seq) {
419 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
420 __func__, bus->name, bus->seq, sub_bus);
423 sub_bus = pci_get_bus_max();
424 pciauto_postscan_setup_bridge(hose, bdf, sub_bus);
430 * pci_match_one_device - Tell if a PCI device structure has a matching
431 * PCI device id structure
432 * @id: single PCI device id structure to match
433 * @dev: the PCI device structure to match against
435 * Returns the matching pci_device_id structure or %NULL if there is no match.
437 static bool pci_match_one_id(const struct pci_device_id *id,
438 const struct pci_device_id *find)
440 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
441 (id->device == PCI_ANY_ID || id->device == find->device) &&
442 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
443 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
444 !((id->class ^ find->class) & id->class_mask))
451 * pci_find_and_bind_driver() - Find and bind the right PCI driver
453 * This only looks at certain fields in the descriptor.
455 static int pci_find_and_bind_driver(struct udevice *parent,
456 struct pci_device_id *find_id, pci_dev_t bdf,
457 struct udevice **devp)
459 struct pci_driver_entry *start, *entry;
467 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
468 find_id->vendor, find_id->device);
469 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
470 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
471 for (entry = start; entry != start + n_ents; entry++) {
472 const struct pci_device_id *id;
474 const struct driver *drv;
476 for (id = entry->match;
477 id->vendor || id->subvendor || id->class_mask;
479 if (!pci_match_one_id(id, find_id))
484 * We could pass the descriptor to the driver as
485 * platdata (instead of NULL) and allow its bind()
486 * method to return -ENOENT if it doesn't support this
487 * device. That way we could continue the search to
488 * find another driver. For now this doesn't seem
489 * necesssary, so just bind the first match.
491 ret = device_bind(parent, drv, drv->name, NULL, -1,
495 debug("%s: Match found: %s\n", __func__, drv->name);
496 dev->driver_data = find_id->driver_data;
502 /* Bind a generic driver so that the device can be used */
503 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
508 drv = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI ? "pci_bridge_drv" :
510 ret = device_bind_driver(parent, drv, str, devp);
512 debug("%s: Failed to bind generic driver: %d", __func__, ret);
515 debug("%s: No match found: bound generic driver instead\n", __func__);
520 debug("%s: No match found: error %d\n", __func__, ret);
524 int pci_bind_bus_devices(struct udevice *bus)
526 ulong vendor, device;
533 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
534 PCI_MAX_PCI_FUNCTIONS - 1);
535 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end;
536 bdf += PCI_BDF(0, 0, 1)) {
537 struct pci_child_platdata *pplat;
541 if (PCI_FUNC(bdf) && !found_multi)
543 /* Check only the first access, we don't expect problems */
544 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
545 &header_type, PCI_SIZE_8);
548 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
550 if (vendor == 0xffff || vendor == 0x0000)
554 found_multi = header_type & 0x80;
556 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
557 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
558 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
560 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
564 /* Find this device in the device tree */
565 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
567 /* Search for a driver */
569 /* If nothing in the device tree, bind a generic device */
570 if (ret == -ENODEV) {
571 struct pci_device_id find_id;
574 memset(&find_id, '\0', sizeof(find_id));
575 find_id.vendor = vendor;
576 find_id.device = device;
577 find_id.class = class;
578 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
579 pci_bus_read_config(bus, bdf,
580 PCI_SUBSYSTEM_VENDOR_ID,
582 find_id.subvendor = val & 0xffff;
583 find_id.subdevice = val >> 16;
585 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
591 /* Update the platform data */
592 pplat = dev_get_parent_platdata(dev);
593 pplat->devfn = PCI_MASK_BUS(bdf);
594 pplat->vendor = vendor;
595 pplat->device = device;
596 pplat->class = class;
601 printf("Cannot read bus configuration: %d\n", ret);
606 static int pci_uclass_post_bind(struct udevice *bus)
609 * Scan the device tree for devices. This does not probe the PCI bus,
610 * as this is not permitted while binding. It just finds devices
611 * mentioned in the device tree.
613 * Before relocation, only bind devices marked for pre-relocation
616 return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
617 gd->flags & GD_FLG_RELOC ? false : true);
620 static int decode_regions(struct pci_controller *hose, const void *blob,
621 int parent_node, int node)
623 int pci_addr_cells, addr_cells, size_cells;
624 int cells_per_record;
630 prop = fdt_getprop(blob, node, "ranges", &len);
633 pci_addr_cells = fdt_address_cells(blob, node);
634 addr_cells = fdt_address_cells(blob, parent_node);
635 size_cells = fdt_size_cells(blob, node);
637 /* PCI addresses are always 3-cells */
639 cells_per_record = pci_addr_cells + addr_cells + size_cells;
640 hose->region_count = 0;
641 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
643 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
644 u64 pci_addr, addr, size;
649 if (len < cells_per_record)
651 flags = fdt32_to_cpu(prop[0]);
652 space_code = (flags >> 24) & 3;
653 pci_addr = fdtdec_get_number(prop + 1, 2);
654 prop += pci_addr_cells;
655 addr = fdtdec_get_number(prop, addr_cells);
657 size = fdtdec_get_number(prop, size_cells);
659 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
660 ", size=%" PRIx64 ", space_code=%d\n", __func__,
661 hose->region_count, pci_addr, addr, size, space_code);
662 if (space_code & 2) {
663 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
665 } else if (space_code & 1) {
666 type = PCI_REGION_IO;
670 debug(" - type=%d\n", type);
671 pci_set_region(hose->regions + hose->region_count++, pci_addr,
675 /* Add a region for our local memory */
677 if (gd->pci_ram_top && gd->pci_ram_top < addr)
678 addr = gd->pci_ram_top;
679 pci_set_region(hose->regions + hose->region_count++, 0, 0, addr,
680 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
685 static int pci_uclass_pre_probe(struct udevice *bus)
687 struct pci_controller *hose;
690 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
692 hose = bus->uclass_priv;
694 /* For bridges, use the top-level PCI controller */
695 if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
697 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
700 debug("%s: Cannot decode regions\n", __func__);
704 struct pci_controller *parent_hose;
706 parent_hose = dev_get_uclass_priv(bus->parent);
707 hose->ctlr = parent_hose->bus;
710 hose->first_busno = bus->seq;
711 hose->last_busno = bus->seq;
716 static int pci_uclass_post_probe(struct udevice *bus)
720 /* Don't scan buses before relocation */
721 if (!(gd->flags & GD_FLG_RELOC))
724 debug("%s: probing bus %d\n", __func__, bus->seq);
725 ret = pci_bind_bus_devices(bus);
729 #ifdef CONFIG_PCI_PNP
730 ret = pci_auto_config_devices(bus);
733 return ret < 0 ? ret : 0;
736 static int pci_uclass_child_post_bind(struct udevice *dev)
738 struct pci_child_platdata *pplat;
739 struct fdt_pci_addr addr;
742 if (dev->of_offset == -1)
746 * We could read vendor, device, class if available. But for now we
747 * just check the address.
749 pplat = dev_get_parent_platdata(dev);
750 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
751 FDT_PCI_SPACE_CONFIG, "reg", &addr);
757 /* extract the bdf from fdt_pci_addr */
758 pplat->devfn = addr.phys_hi & 0xffff00;
764 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
765 uint offset, ulong *valuep,
766 enum pci_size_t size)
768 struct pci_controller *hose = bus->uclass_priv;
770 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
773 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
774 uint offset, ulong value,
775 enum pci_size_t size)
777 struct pci_controller *hose = bus->uclass_priv;
779 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
782 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
788 * Scan through all the PCI controllers. On x86 there will only be one
789 * but that is not necessarily true on other hardware.
792 device_find_first_child(bus, &dev);
797 ret = uclass_next_device(&bus);
805 int pci_find_next_device(struct udevice **devp)
807 struct udevice *child = *devp;
808 struct udevice *bus = child->parent;
811 /* First try all the siblings */
814 device_find_next_child(&child);
821 /* We ran out of siblings. Try the next bus */
822 ret = uclass_next_device(&bus);
826 return bus ? skip_to_next_device(bus, devp) : 0;
829 int pci_find_first_device(struct udevice **devp)
835 ret = uclass_first_device(UCLASS_PCI, &bus);
839 return skip_to_next_device(bus, devp);
842 UCLASS_DRIVER(pci) = {
845 .flags = DM_UC_FLAG_SEQ_ALIAS,
846 .post_bind = pci_uclass_post_bind,
847 .pre_probe = pci_uclass_pre_probe,
848 .post_probe = pci_uclass_post_probe,
849 .child_post_bind = pci_uclass_child_post_bind,
850 .per_device_auto_alloc_size = sizeof(struct pci_controller),
851 .per_child_platdata_auto_alloc_size =
852 sizeof(struct pci_child_platdata),
855 static const struct dm_pci_ops pci_bridge_ops = {
856 .read_config = pci_bridge_read_config,
857 .write_config = pci_bridge_write_config,
860 static const struct udevice_id pci_bridge_ids[] = {
861 { .compatible = "pci-bridge" },
865 U_BOOT_DRIVER(pci_bridge_drv) = {
866 .name = "pci_bridge_drv",
868 .of_match = pci_bridge_ids,
869 .ops = &pci_bridge_ops,
872 UCLASS_DRIVER(pci_generic) = {
873 .id = UCLASS_PCI_GENERIC,
874 .name = "pci_generic",
877 static const struct udevice_id pci_generic_ids[] = {
878 { .compatible = "pci-generic" },
882 U_BOOT_DRIVER(pci_generic_drv) = {
883 .name = "pci_generic_drv",
884 .id = UCLASS_PCI_GENERIC,
885 .of_match = pci_generic_ids,