2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
5 * SPDX-License-Identifier: GPL-2.0+
17 #include <dm/device-internal.h>
18 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
19 #include <asm/fsp/fsp_support.h>
21 #include "pci_internal.h"
23 DECLARE_GLOBAL_DATA_PTR;
25 int pci_get_bus(int busnum, struct udevice **busp)
29 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
31 /* Since buses may not be numbered yet try a little harder with bus 0 */
33 ret = uclass_first_device_err(UCLASS_PCI, busp);
36 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
42 struct udevice *pci_get_controller(struct udevice *dev)
44 while (device_is_on_pci_bus(dev))
50 pci_dev_t dm_pci_get_bdf(struct udevice *dev)
52 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
53 struct udevice *bus = dev->parent;
55 return PCI_ADD_BUS(bus->seq, pplat->devfn);
59 * pci_get_bus_max() - returns the bus number of the last active bus
61 * @return last bus number, or -1 if no active buses
63 static int pci_get_bus_max(void)
69 ret = uclass_get(UCLASS_PCI, &uc);
70 uclass_foreach_dev(bus, uc) {
75 debug("%s: ret=%d\n", __func__, ret);
80 int pci_last_busno(void)
82 return pci_get_bus_max();
85 int pci_get_ff(enum pci_size_t size)
97 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
98 struct udevice **devp)
102 for (device_find_first_child(bus, &dev);
104 device_find_next_child(&dev)) {
105 struct pci_child_platdata *pplat;
107 pplat = dev_get_parent_platdata(dev);
108 if (pplat && pplat->devfn == find_devfn) {
117 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
122 ret = pci_get_bus(PCI_BUS(bdf), &bus);
125 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
128 static int pci_device_matches_ids(struct udevice *dev,
129 struct pci_device_id *ids)
131 struct pci_child_platdata *pplat;
134 pplat = dev_get_parent_platdata(dev);
137 for (i = 0; ids[i].vendor != 0; i++) {
138 if (pplat->vendor == ids[i].vendor &&
139 pplat->device == ids[i].device)
146 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
147 int *indexp, struct udevice **devp)
151 /* Scan all devices on this bus */
152 for (device_find_first_child(bus, &dev);
154 device_find_next_child(&dev)) {
155 if (pci_device_matches_ids(dev, ids) >= 0) {
156 if ((*indexp)-- <= 0) {
166 int pci_find_device_id(struct pci_device_id *ids, int index,
167 struct udevice **devp)
171 /* Scan all known buses */
172 for (uclass_first_device(UCLASS_PCI, &bus);
174 uclass_next_device(&bus)) {
175 if (!pci_bus_find_devices(bus, ids, &index, devp))
183 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
184 unsigned int device, int *indexp,
185 struct udevice **devp)
187 struct pci_child_platdata *pplat;
190 for (device_find_first_child(bus, &dev);
192 device_find_next_child(&dev)) {
193 pplat = dev_get_parent_platdata(dev);
194 if (pplat->vendor == vendor && pplat->device == device) {
205 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
206 struct udevice **devp)
210 /* Scan all known buses */
211 for (uclass_first_device(UCLASS_PCI, &bus);
213 uclass_next_device(&bus)) {
214 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
215 return device_probe(*devp);
222 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
226 /* Scan all known buses */
227 for (pci_find_first_device(&dev);
229 pci_find_next_device(&dev)) {
230 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
232 if (pplat->class == find_class && !index--) {
234 return device_probe(*devp);
242 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
243 unsigned long value, enum pci_size_t size)
245 struct dm_pci_ops *ops;
247 ops = pci_get_ops(bus);
248 if (!ops->write_config)
250 return ops->write_config(bus, bdf, offset, value, size);
253 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
259 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
265 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
268 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
269 enum pci_size_t size)
274 ret = pci_get_bus(PCI_BUS(bdf), &bus);
278 return pci_bus_write_config(bus, bdf, offset, value, size);
281 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
282 enum pci_size_t size)
286 for (bus = dev; device_is_on_pci_bus(bus);)
288 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
293 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
295 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
298 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
300 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
303 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
305 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
308 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
310 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
313 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
315 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
318 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
320 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
323 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
324 unsigned long *valuep, enum pci_size_t size)
326 struct dm_pci_ops *ops;
328 ops = pci_get_ops(bus);
329 if (!ops->read_config)
331 return ops->read_config(bus, bdf, offset, valuep, size);
334 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
335 enum pci_size_t size)
340 ret = pci_get_bus(PCI_BUS(bdf), &bus);
344 return pci_bus_read_config(bus, bdf, offset, valuep, size);
347 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
348 enum pci_size_t size)
352 for (bus = dev; device_is_on_pci_bus(bus);)
354 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
358 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
363 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
371 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
376 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
384 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
389 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
397 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
402 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
410 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
415 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
423 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
428 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
436 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
441 ret = dm_pci_read_config8(dev, offset, &val);
447 return dm_pci_write_config8(dev, offset, val);
450 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
455 ret = dm_pci_read_config16(dev, offset, &val);
461 return dm_pci_write_config16(dev, offset, val);
464 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
469 ret = dm_pci_read_config32(dev, offset, &val);
475 return dm_pci_write_config32(dev, offset, val);
478 static void set_vga_bridge_bits(struct udevice *dev)
480 struct udevice *parent = dev->parent;
483 while (parent->seq != 0) {
484 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
485 bc |= PCI_BRIDGE_CTL_VGA;
486 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
487 parent = parent->parent;
491 int pci_auto_config_devices(struct udevice *bus)
493 struct pci_controller *hose = bus->uclass_priv;
494 struct pci_child_platdata *pplat;
495 unsigned int sub_bus;
500 debug("%s: start\n", __func__);
501 pciauto_config_init(hose);
502 for (ret = device_find_first_child(bus, &dev);
504 ret = device_find_next_child(&dev)) {
505 unsigned int max_bus;
508 debug("%s: device %s\n", __func__, dev->name);
509 ret = dm_pciauto_config_device(dev);
513 sub_bus = max(sub_bus, max_bus);
515 pplat = dev_get_parent_platdata(dev);
516 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
517 set_vga_bridge_bits(dev);
519 debug("%s: done\n", __func__);
524 int dm_pci_hose_probe_bus(struct udevice *bus)
529 debug("%s\n", __func__);
531 sub_bus = pci_get_bus_max() + 1;
532 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
533 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
535 ret = device_probe(bus);
537 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
541 if (sub_bus != bus->seq) {
542 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
543 __func__, bus->name, bus->seq, sub_bus);
546 sub_bus = pci_get_bus_max();
547 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
553 * pci_match_one_device - Tell if a PCI device structure has a matching
554 * PCI device id structure
555 * @id: single PCI device id structure to match
556 * @dev: the PCI device structure to match against
558 * Returns the matching pci_device_id structure or %NULL if there is no match.
560 static bool pci_match_one_id(const struct pci_device_id *id,
561 const struct pci_device_id *find)
563 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
564 (id->device == PCI_ANY_ID || id->device == find->device) &&
565 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
566 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
567 !((id->class ^ find->class) & id->class_mask))
574 * pci_find_and_bind_driver() - Find and bind the right PCI driver
576 * This only looks at certain fields in the descriptor.
578 * @parent: Parent bus
579 * @find_id: Specification of the driver to find
580 * @bdf: Bus/device/function addreess - see PCI_BDF()
581 * @devp: Returns a pointer to the device created
582 * @return 0 if OK, -EPERM if the device is not needed before relocation and
583 * therefore was not created, other -ve value on error
585 static int pci_find_and_bind_driver(struct udevice *parent,
586 struct pci_device_id *find_id,
587 pci_dev_t bdf, struct udevice **devp)
589 struct pci_driver_entry *start, *entry;
598 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
599 find_id->vendor, find_id->device);
600 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
601 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
602 for (entry = start; entry != start + n_ents; entry++) {
603 const struct pci_device_id *id;
605 const struct driver *drv;
607 for (id = entry->match;
608 id->vendor || id->subvendor || id->class_mask;
610 if (!pci_match_one_id(id, find_id))
616 * In the pre-relocation phase, we only bind devices
617 * whose driver has the DM_FLAG_PRE_RELOC set, to save
618 * precious memory space as on some platforms as that
619 * space is pretty limited (ie: using Cache As RAM).
621 if (!(gd->flags & GD_FLG_RELOC) &&
622 !(drv->flags & DM_FLAG_PRE_RELOC))
626 * We could pass the descriptor to the driver as
627 * platdata (instead of NULL) and allow its bind()
628 * method to return -ENOENT if it doesn't support this
629 * device. That way we could continue the search to
630 * find another driver. For now this doesn't seem
631 * necesssary, so just bind the first match.
633 ret = device_bind(parent, drv, drv->name, NULL, -1,
637 debug("%s: Match found: %s\n", __func__, drv->name);
638 dev->driver_data = find_id->driver_data;
644 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
646 * In the pre-relocation phase, we only bind bridge devices to save
647 * precious memory space as on some platforms as that space is pretty
648 * limited (ie: using Cache As RAM).
650 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
653 /* Bind a generic driver so that the device can be used */
654 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
659 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
661 ret = device_bind_driver(parent, drv, str, devp);
663 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
666 debug("%s: No match found: bound generic driver instead\n", __func__);
671 debug("%s: No match found: error %d\n", __func__, ret);
675 int pci_bind_bus_devices(struct udevice *bus)
677 ulong vendor, device;
684 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
685 PCI_MAX_PCI_FUNCTIONS - 1);
686 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end;
687 bdf += PCI_BDF(0, 0, 1)) {
688 struct pci_child_platdata *pplat;
692 if (PCI_FUNC(bdf) && !found_multi)
694 /* Check only the first access, we don't expect problems */
695 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
696 &header_type, PCI_SIZE_8);
699 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
701 if (vendor == 0xffff || vendor == 0x0000)
705 found_multi = header_type & 0x80;
707 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
708 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
709 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
711 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
715 /* Find this device in the device tree */
716 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
718 /* If nothing in the device tree, bind a device */
719 if (ret == -ENODEV) {
720 struct pci_device_id find_id;
723 memset(&find_id, '\0', sizeof(find_id));
724 find_id.vendor = vendor;
725 find_id.device = device;
726 find_id.class = class;
727 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
728 pci_bus_read_config(bus, bdf,
729 PCI_SUBSYSTEM_VENDOR_ID,
731 find_id.subvendor = val & 0xffff;
732 find_id.subdevice = val >> 16;
734 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
742 /* Update the platform data */
743 pplat = dev_get_parent_platdata(dev);
744 pplat->devfn = PCI_MASK_BUS(bdf);
745 pplat->vendor = vendor;
746 pplat->device = device;
747 pplat->class = class;
752 printf("Cannot read bus configuration: %d\n", ret);
757 static int pci_uclass_post_bind(struct udevice *bus)
760 * If there is no pci device listed in the device tree,
761 * don't bother scanning the device tree.
763 if (bus->of_offset == -1)
767 * Scan the device tree for devices. This does not probe the PCI bus,
768 * as this is not permitted while binding. It just finds devices
769 * mentioned in the device tree.
771 * Before relocation, only bind devices marked for pre-relocation
774 return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
775 gd->flags & GD_FLG_RELOC ? false : true);
778 static int decode_regions(struct pci_controller *hose, const void *blob,
779 int parent_node, int node)
781 int pci_addr_cells, addr_cells, size_cells;
782 phys_addr_t base = 0, size;
783 int cells_per_record;
788 prop = fdt_getprop(blob, node, "ranges", &len);
791 pci_addr_cells = fdt_address_cells(blob, node);
792 addr_cells = fdt_address_cells(blob, parent_node);
793 size_cells = fdt_size_cells(blob, node);
795 /* PCI addresses are always 3-cells */
797 cells_per_record = pci_addr_cells + addr_cells + size_cells;
798 hose->region_count = 0;
799 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
801 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
802 u64 pci_addr, addr, size;
808 if (len < cells_per_record)
810 flags = fdt32_to_cpu(prop[0]);
811 space_code = (flags >> 24) & 3;
812 pci_addr = fdtdec_get_number(prop + 1, 2);
813 prop += pci_addr_cells;
814 addr = fdtdec_get_number(prop, addr_cells);
816 size = fdtdec_get_number(prop, size_cells);
818 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
819 ", size=%" PRIx64 ", space_code=%d\n", __func__,
820 hose->region_count, pci_addr, addr, size, space_code);
821 if (space_code & 2) {
822 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
824 } else if (space_code & 1) {
825 type = PCI_REGION_IO;
830 for (i = 0; i < hose->region_count; i++) {
831 if (hose->regions[i].flags == type)
835 pos = hose->region_count++;
836 debug(" - type=%d, pos=%d\n", type, pos);
837 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
840 /* Add a region for our local memory */
842 #ifdef CONFIG_SYS_SDRAM_BASE
843 base = CONFIG_SYS_SDRAM_BASE;
845 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
846 size = gd->pci_ram_top - base;
847 pci_set_region(hose->regions + hose->region_count++, base, base,
848 size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
853 static int pci_uclass_pre_probe(struct udevice *bus)
855 struct pci_controller *hose;
858 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
860 hose = bus->uclass_priv;
862 /* For bridges, use the top-level PCI controller */
863 if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
865 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
868 debug("%s: Cannot decode regions\n", __func__);
872 struct pci_controller *parent_hose;
874 parent_hose = dev_get_uclass_priv(bus->parent);
875 hose->ctlr = parent_hose->bus;
878 hose->first_busno = bus->seq;
879 hose->last_busno = bus->seq;
884 static int pci_uclass_post_probe(struct udevice *bus)
888 debug("%s: probing bus %d\n", __func__, bus->seq);
889 ret = pci_bind_bus_devices(bus);
893 #ifdef CONFIG_PCI_PNP
894 ret = pci_auto_config_devices(bus);
899 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
901 * Per Intel FSP specification, we should call FSP notify API to
902 * inform FSP that PCI enumeration has been done so that FSP will
903 * do any necessary initialization as required by the chipset's
904 * BIOS Writer's Guide (BWG).
906 * Unfortunately we have to put this call here as with driver model,
907 * the enumeration is all done on a lazy basis as needed, so until
908 * something is touched on PCI it won't happen.
910 * Note we only call this 1) after U-Boot is relocated, and 2)
911 * root bus has finished probing.
913 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
914 ret = fsp_init_phase_pci();
923 static int pci_uclass_child_post_bind(struct udevice *dev)
925 struct pci_child_platdata *pplat;
926 struct fdt_pci_addr addr;
929 if (dev->of_offset == -1)
933 * We could read vendor, device, class if available. But for now we
934 * just check the address.
936 pplat = dev_get_parent_platdata(dev);
937 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
938 FDT_PCI_SPACE_CONFIG, "reg", &addr);
944 /* extract the devfn from fdt_pci_addr */
945 pplat->devfn = addr.phys_hi & 0xff00;
951 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
952 uint offset, ulong *valuep,
953 enum pci_size_t size)
955 struct pci_controller *hose = bus->uclass_priv;
957 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
960 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
961 uint offset, ulong value,
962 enum pci_size_t size)
964 struct pci_controller *hose = bus->uclass_priv;
966 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
969 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
975 * Scan through all the PCI controllers. On x86 there will only be one
976 * but that is not necessarily true on other hardware.
979 device_find_first_child(bus, &dev);
984 ret = uclass_next_device(&bus);
992 int pci_find_next_device(struct udevice **devp)
994 struct udevice *child = *devp;
995 struct udevice *bus = child->parent;
998 /* First try all the siblings */
1001 device_find_next_child(&child);
1008 /* We ran out of siblings. Try the next bus */
1009 ret = uclass_next_device(&bus);
1013 return bus ? skip_to_next_device(bus, devp) : 0;
1016 int pci_find_first_device(struct udevice **devp)
1018 struct udevice *bus;
1022 ret = uclass_first_device(UCLASS_PCI, &bus);
1026 return skip_to_next_device(bus, devp);
1029 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1033 return (value >> ((offset & 3) * 8)) & 0xff;
1035 return (value >> ((offset & 2) * 8)) & 0xffff;
1041 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1042 enum pci_size_t size)
1045 uint val_mask, shift;
1060 shift = (offset & off_mask) * 8;
1061 ldata = (value & val_mask) << shift;
1062 mask = val_mask << shift;
1063 value = (old & ~mask) | ldata;
1068 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1069 struct pci_region **memp, struct pci_region **prefp)
1071 struct udevice *bus = pci_get_controller(dev);
1072 struct pci_controller *hose = dev_get_uclass_priv(bus);
1078 for (i = 0; i < hose->region_count; i++) {
1079 switch (hose->regions[i].flags) {
1081 if (!*iop || (*iop)->size < hose->regions[i].size)
1082 *iop = hose->regions + i;
1084 case PCI_REGION_MEM:
1085 if (!*memp || (*memp)->size < hose->regions[i].size)
1086 *memp = hose->regions + i;
1088 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1089 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1090 *prefp = hose->regions + i;
1095 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1098 u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1103 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1104 dm_pci_read_config32(dev, bar, &addr);
1105 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1106 return addr & PCI_BASE_ADDRESS_IO_MASK;
1108 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1111 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1115 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1116 dm_pci_write_config32(dev, bar, addr);
1119 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1120 pci_addr_t bus_addr, unsigned long flags,
1121 unsigned long skip_mask, phys_addr_t *pa)
1123 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1124 struct pci_region *res;
1127 for (i = 0; i < hose->region_count; i++) {
1128 res = &hose->regions[i];
1130 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1133 if (res->flags & skip_mask)
1136 if (bus_addr >= res->bus_start &&
1137 (bus_addr - res->bus_start) < res->size) {
1138 *pa = (bus_addr - res->bus_start + res->phys_start);
1146 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1147 unsigned long flags)
1149 phys_addr_t phys_addr = 0;
1150 struct udevice *ctlr;
1153 /* The root controller has the region information */
1154 ctlr = pci_get_controller(dev);
1157 * if PCI_REGION_MEM is set we do a two pass search with preference
1158 * on matches that don't have PCI_REGION_SYS_MEMORY set
1160 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1161 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1162 flags, PCI_REGION_SYS_MEMORY,
1168 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1171 puts("pci_hose_bus_to_phys: invalid physical address\n");
1176 int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1177 unsigned long flags, unsigned long skip_mask,
1180 struct pci_region *res;
1181 struct udevice *ctlr;
1182 pci_addr_t bus_addr;
1184 struct pci_controller *hose;
1186 /* The root controller has the region information */
1187 ctlr = pci_get_controller(dev);
1188 hose = dev_get_uclass_priv(ctlr);
1190 for (i = 0; i < hose->region_count; i++) {
1191 res = &hose->regions[i];
1193 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1196 if (res->flags & skip_mask)
1199 bus_addr = phys_addr - res->phys_start + res->bus_start;
1201 if (bus_addr >= res->bus_start &&
1202 (bus_addr - res->bus_start) < res->size) {
1211 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1212 unsigned long flags)
1214 pci_addr_t bus_addr = 0;
1218 * if PCI_REGION_MEM is set we do a two pass search with preference
1219 * on matches that don't have PCI_REGION_SYS_MEMORY set
1221 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1222 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1223 PCI_REGION_SYS_MEMORY, &bus_addr);
1228 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1231 puts("pci_hose_phys_to_bus: invalid physical address\n");
1236 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1238 pci_addr_t pci_bus_addr;
1241 /* read BAR address */
1242 dm_pci_read_config32(dev, bar, &bar_response);
1243 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1246 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1247 * isn't actualy used on any platform because u-boot assumes a static
1248 * linear mapping. In the future, this could read the BAR size
1249 * and pass that as the size if needed.
1251 return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1254 UCLASS_DRIVER(pci) = {
1257 .flags = DM_UC_FLAG_SEQ_ALIAS,
1258 .post_bind = pci_uclass_post_bind,
1259 .pre_probe = pci_uclass_pre_probe,
1260 .post_probe = pci_uclass_post_probe,
1261 .child_post_bind = pci_uclass_child_post_bind,
1262 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1263 .per_child_platdata_auto_alloc_size =
1264 sizeof(struct pci_child_platdata),
1267 static const struct dm_pci_ops pci_bridge_ops = {
1268 .read_config = pci_bridge_read_config,
1269 .write_config = pci_bridge_write_config,
1272 static const struct udevice_id pci_bridge_ids[] = {
1273 { .compatible = "pci-bridge" },
1277 U_BOOT_DRIVER(pci_bridge_drv) = {
1278 .name = "pci_bridge_drv",
1280 .of_match = pci_bridge_ids,
1281 .ops = &pci_bridge_ops,
1284 UCLASS_DRIVER(pci_generic) = {
1285 .id = UCLASS_PCI_GENERIC,
1286 .name = "pci_generic",
1289 static const struct udevice_id pci_generic_ids[] = {
1290 { .compatible = "pci-generic" },
1294 U_BOOT_DRIVER(pci_generic_drv) = {
1295 .name = "pci_generic_drv",
1296 .id = UCLASS_PCI_GENERIC,
1297 .of_match = pci_generic_ids,
1302 struct udevice *bus;
1305 * Enumerate all known controller devices. Enumeration has the side-
1306 * effect of probing them, so PCIe devices will be enumerated too.
1308 for (uclass_first_device(UCLASS_PCI, &bus);
1310 uclass_next_device(&bus)) {