2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <dm/device-internal.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 struct pci_controller *pci_bus_to_hose(int busnum)
25 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
27 debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
30 return dev_get_uclass_priv(bus);
34 * pci_get_bus_max() - returns the bus number of the last active bus
36 * @return last bus number, or -1 if no active buses
38 static int pci_get_bus_max(void)
44 ret = uclass_get(UCLASS_PCI, &uc);
45 uclass_foreach_dev(bus, uc) {
50 debug("%s: ret=%d\n", __func__, ret);
55 int pci_last_busno(void)
57 struct pci_controller *hose;
62 debug("pci_last_busno\n");
63 ret = uclass_get(UCLASS_PCI, &uc);
64 if (ret || list_empty(&uc->dev_head))
67 /* Probe the last bus */
68 bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node);
69 debug("bus = %p, %s\n", bus, bus->name);
71 ret = device_probe(bus);
75 /* If that bus has bridges, we may have new buses now. Get the last */
76 bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node);
77 hose = dev_get_uclass_priv(bus);
78 debug("bus = %s, hose = %p\n", bus->name, hose);
80 return hose->last_busno;
83 int pci_get_ff(enum pci_size_t size)
95 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
96 struct udevice **devp)
100 for (device_find_first_child(bus, &dev);
102 device_find_next_child(&dev)) {
103 struct pci_child_platdata *pplat;
105 pplat = dev_get_parent_platdata(dev);
106 if (pplat && pplat->devfn == find_devfn) {
115 int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
120 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus);
123 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
126 static int pci_device_matches_ids(struct udevice *dev,
127 struct pci_device_id *ids)
129 struct pci_child_platdata *pplat;
132 pplat = dev_get_parent_platdata(dev);
135 for (i = 0; ids[i].vendor != 0; i++) {
136 if (pplat->vendor == ids[i].vendor &&
137 pplat->device == ids[i].device)
144 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
145 int *indexp, struct udevice **devp)
149 /* Scan all devices on this bus */
150 for (device_find_first_child(bus, &dev);
152 device_find_next_child(&dev)) {
153 if (pci_device_matches_ids(dev, ids) >= 0) {
154 if ((*indexp)-- <= 0) {
164 int pci_find_device_id(struct pci_device_id *ids, int index,
165 struct udevice **devp)
169 /* Scan all known buses */
170 for (uclass_first_device(UCLASS_PCI, &bus);
172 uclass_next_device(&bus)) {
173 if (!pci_bus_find_devices(bus, ids, &index, devp))
181 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
182 unsigned long value, enum pci_size_t size)
184 struct dm_pci_ops *ops;
186 ops = pci_get_ops(bus);
187 if (!ops->write_config)
189 return ops->write_config(bus, bdf, offset, value, size);
192 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
193 enum pci_size_t size)
198 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus);
202 return pci_bus_write_config(bus, PCI_MASK_BUS(bdf), offset, value,
206 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
208 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
211 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
213 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
216 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
218 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
221 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
222 unsigned long *valuep, enum pci_size_t size)
224 struct dm_pci_ops *ops;
226 ops = pci_get_ops(bus);
227 if (!ops->read_config)
229 return ops->read_config(bus, bdf, offset, valuep, size);
232 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
233 enum pci_size_t size)
238 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus);
242 return pci_bus_read_config(bus, PCI_MASK_BUS(bdf), offset, valuep,
246 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
251 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
259 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
264 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
272 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
277 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
285 int pci_auto_config_devices(struct udevice *bus)
287 struct pci_controller *hose = bus->uclass_priv;
288 unsigned int sub_bus;
293 debug("%s: start\n", __func__);
294 pciauto_config_init(hose);
295 for (ret = device_find_first_child(bus, &dev);
297 ret = device_find_next_child(&dev)) {
298 struct pci_child_platdata *pplat;
299 struct pci_controller *ctlr_hose;
301 pplat = dev_get_parent_platdata(dev);
302 unsigned int max_bus;
305 bdf = PCI_ADD_BUS(bus->seq, pplat->devfn);
306 debug("%s: device %s\n", __func__, dev->name);
308 /* The root controller has the region information */
309 ctlr_hose = hose->ctlr->uclass_priv;
310 max_bus = pciauto_config_device(ctlr_hose, bdf);
311 sub_bus = max(sub_bus, max_bus);
313 debug("%s: done\n", __func__);
318 int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf)
320 struct udevice *parent, *bus;
324 debug("%s\n", __func__);
327 /* Find the bus within the parent */
328 ret = pci_bus_find_devfn(parent, bdf, &bus);
330 debug("%s: Cannot find device %x on bus %s: %d\n", __func__,
331 bdf, parent->name, ret);
335 sub_bus = pci_get_bus_max() + 1;
336 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
337 pciauto_prescan_setup_bridge(hose, bdf, sub_bus);
339 ret = device_probe(bus);
341 debug("%s: Cannot probe bus bus %s: %d\n", __func__, bus->name,
345 if (sub_bus != bus->seq) {
346 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
347 __func__, bus->name, bus->seq, sub_bus);
350 sub_bus = pci_get_bus_max();
351 pciauto_postscan_setup_bridge(hose, bdf, sub_bus);
356 int pci_bind_bus_devices(struct udevice *bus)
358 ulong vendor, device;
360 pci_dev_t devfn, end;
365 end = PCI_DEVFN(PCI_MAX_PCI_DEVICES - 1, PCI_MAX_PCI_FUNCTIONS - 1);
366 for (devfn = PCI_DEVFN(0, 0); devfn < end; devfn += PCI_DEVFN(0, 1)) {
367 struct pci_child_platdata *pplat;
371 if (PCI_FUNC(devfn) && !found_multi)
373 /* Check only the first access, we don't expect problems */
374 ret = pci_bus_read_config(bus, devfn, PCI_HEADER_TYPE,
375 &header_type, PCI_SIZE_8);
378 pci_bus_read_config(bus, devfn, PCI_VENDOR_ID, &vendor,
380 if (vendor == 0xffff || vendor == 0x0000)
383 if (!PCI_FUNC(devfn))
384 found_multi = header_type & 0x80;
386 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
387 bus->seq, bus->name, PCI_DEV(devfn), PCI_FUNC(devfn));
388 pci_bus_read_config(bus, devfn, PCI_DEVICE_ID, &device,
390 pci_bus_read_config(bus, devfn, PCI_CLASS_DEVICE, &class,
393 /* Find this device in the device tree */
394 ret = pci_bus_find_devfn(bus, devfn, &dev);
396 /* If nothing in the device tree, bind a generic device */
397 if (ret == -ENODEV) {
401 sprintf(name, "pci_%x:%x.%x", bus->seq,
402 PCI_DEV(devfn), PCI_FUNC(devfn));
406 drv = class == PCI_CLASS_BRIDGE_PCI ?
407 "pci_bridge_drv" : "pci_generic_drv";
408 ret = device_bind_driver(bus, drv, str, &dev);
413 /* Update the platform data */
414 pplat = dev_get_parent_platdata(dev);
415 pplat->devfn = devfn;
416 pplat->vendor = vendor;
417 pplat->device = device;
418 pplat->class = class;
423 printf("Cannot read bus configuration: %d\n", ret);
428 static int pci_uclass_post_bind(struct udevice *bus)
431 * Scan the device tree for devices. This does not probe the PCI bus,
432 * as this is not permitted while binding. It just finds devices
433 * mentioned in the device tree.
435 * Before relocation, only bind devices marked for pre-relocation
438 return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
439 gd->flags & GD_FLG_RELOC ? false : true);
442 static int decode_regions(struct pci_controller *hose, const void *blob,
443 int parent_node, int node)
445 int pci_addr_cells, addr_cells, size_cells;
446 int cells_per_record;
452 prop = fdt_getprop(blob, node, "ranges", &len);
455 pci_addr_cells = fdt_address_cells(blob, node);
456 addr_cells = fdt_address_cells(blob, parent_node);
457 size_cells = fdt_size_cells(blob, node);
459 /* PCI addresses are always 3-cells */
461 cells_per_record = pci_addr_cells + addr_cells + size_cells;
462 hose->region_count = 0;
463 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
465 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
466 u64 pci_addr, addr, size;
471 if (len < cells_per_record)
473 flags = fdt32_to_cpu(prop[0]);
474 space_code = (flags >> 24) & 3;
475 pci_addr = fdtdec_get_number(prop + 1, 2);
476 prop += pci_addr_cells;
477 addr = fdtdec_get_number(prop, addr_cells);
479 size = fdtdec_get_number(prop, size_cells);
481 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
482 ", size=%" PRIx64 ", space_code=%d\n", __func__,
483 hose->region_count, pci_addr, addr, size, space_code);
484 if (space_code & 2) {
485 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
487 } else if (space_code & 1) {
488 type = PCI_REGION_IO;
492 debug(" - type=%d\n", type);
493 pci_set_region(hose->regions + hose->region_count++, pci_addr,
497 /* Add a region for our local memory */
499 if (gd->pci_ram_top && gd->pci_ram_top < addr)
500 addr = gd->pci_ram_top;
501 pci_set_region(hose->regions + hose->region_count++, 0, 0, addr,
502 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
507 static int pci_uclass_pre_probe(struct udevice *bus)
509 struct pci_controller *hose;
512 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
514 hose = bus->uclass_priv;
516 /* For bridges, use the top-level PCI controller */
517 if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
519 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
522 debug("%s: Cannot decode regions\n", __func__);
526 struct pci_controller *parent_hose;
528 parent_hose = dev_get_uclass_priv(bus->parent);
529 hose->ctlr = parent_hose->bus;
532 hose->first_busno = bus->seq;
533 hose->last_busno = bus->seq;
538 static int pci_uclass_post_probe(struct udevice *bus)
542 /* Don't scan buses before relocation */
543 if (!(gd->flags & GD_FLG_RELOC))
546 debug("%s: probing bus %d\n", __func__, bus->seq);
547 ret = pci_bind_bus_devices(bus);
551 #ifdef CONFIG_PCI_PNP
552 ret = pci_auto_config_devices(bus);
555 return ret < 0 ? ret : 0;
558 static int pci_uclass_child_post_bind(struct udevice *dev)
560 struct pci_child_platdata *pplat;
561 struct fdt_pci_addr addr;
564 if (dev->of_offset == -1)
568 * We could read vendor, device, class if available. But for now we
569 * just check the address.
571 pplat = dev_get_parent_platdata(dev);
572 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
573 FDT_PCI_SPACE_CONFIG, "reg", &addr);
579 /* extract the bdf from fdt_pci_addr */
580 pplat->devfn = addr.phys_hi & 0xffff00;
586 int pci_bridge_read_config(struct udevice *bus, pci_dev_t devfn, uint offset,
587 ulong *valuep, enum pci_size_t size)
589 struct pci_controller *hose = bus->uclass_priv;
590 pci_dev_t bdf = PCI_ADD_BUS(bus->seq, devfn);
592 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
595 int pci_bridge_write_config(struct udevice *bus, pci_dev_t devfn, uint offset,
596 ulong value, enum pci_size_t size)
598 struct pci_controller *hose = bus->uclass_priv;
599 pci_dev_t bdf = PCI_ADD_BUS(bus->seq, devfn);
601 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
604 UCLASS_DRIVER(pci) = {
607 .flags = DM_UC_FLAG_SEQ_ALIAS,
608 .post_bind = pci_uclass_post_bind,
609 .pre_probe = pci_uclass_pre_probe,
610 .post_probe = pci_uclass_post_probe,
611 .child_post_bind = pci_uclass_child_post_bind,
612 .per_device_auto_alloc_size = sizeof(struct pci_controller),
613 .per_child_platdata_auto_alloc_size =
614 sizeof(struct pci_child_platdata),
617 static const struct dm_pci_ops pci_bridge_ops = {
618 .read_config = pci_bridge_read_config,
619 .write_config = pci_bridge_write_config,
622 static const struct udevice_id pci_bridge_ids[] = {
623 { .compatible = "pci-bridge" },
627 U_BOOT_DRIVER(pci_bridge_drv) = {
628 .name = "pci_bridge_drv",
630 .of_match = pci_bridge_ids,
631 .ops = &pci_bridge_ops,
634 UCLASS_DRIVER(pci_generic) = {
635 .id = UCLASS_PCI_GENERIC,
636 .name = "pci_generic",
639 static const struct udevice_id pci_generic_ids[] = {
640 { .compatible = "pci-generic" },
644 U_BOOT_DRIVER(pci_generic_drv) = {
645 .name = "pci_generic_drv",
646 .id = UCLASS_PCI_GENERIC,
647 .of_match = pci_generic_ids,