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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4  * Andreas Heppel <aheppel@sysgo.de>
5  *
6  * (C) Copyright 2002, 2003
7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8  */
9
10 /*
11  * Old PCI routines
12  *
13  * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
14  * and change pci-uclass.c.
15  */
16
17 #include <common.h>
18
19 #include <command.h>
20 #include <errno.h>
21 #include <asm/processor.h>
22 #include <asm/io.h>
23 #include <pci.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 #define PCI_HOSE_OP(rw, size, type)                                     \
28 int pci_hose_##rw##_config_##size(struct pci_controller *hose,          \
29                                   pci_dev_t dev,                        \
30                                   int offset, type value)               \
31 {                                                                       \
32         return hose->rw##_##size(hose, dev, offset, value);             \
33 }
34
35 PCI_HOSE_OP(read, byte, u8 *)
36 PCI_HOSE_OP(read, word, u16 *)
37 PCI_HOSE_OP(read, dword, u32 *)
38 PCI_HOSE_OP(write, byte, u8)
39 PCI_HOSE_OP(write, word, u16)
40 PCI_HOSE_OP(write, dword, u32)
41
42 #define PCI_OP(rw, size, type, error_code)                              \
43 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)     \
44 {                                                                       \
45         struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));    \
46                                                                         \
47         if (!hose)                                                      \
48         {                                                               \
49                 error_code;                                             \
50                 return -1;                                              \
51         }                                                               \
52                                                                         \
53         return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
54 }
55
56 PCI_OP(read, byte, u8 *, *value = 0xff)
57 PCI_OP(read, word, u16 *, *value = 0xffff)
58 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
59 PCI_OP(write, byte, u8, )
60 PCI_OP(write, word, u16, )
61 PCI_OP(write, dword, u32, )
62
63 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)                     \
64 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
65                                         pci_dev_t dev,                  \
66                                         int offset, type val)           \
67 {                                                                       \
68         u32 val32;                                                      \
69                                                                         \
70         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
71                 *val = -1;                                              \
72                 return -1;                                              \
73         }                                                               \
74                                                                         \
75         *val = (val32 >> ((offset & (int)off_mask) * 8));               \
76                                                                         \
77         return 0;                                                       \
78 }
79
80 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)          \
81 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
82                                              pci_dev_t dev,             \
83                                              int offset, type val)      \
84 {                                                                       \
85         u32 val32, mask, ldata, shift;                                  \
86                                                                         \
87         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
88                 return -1;                                              \
89                                                                         \
90         shift = ((offset & (int)off_mask) * 8);                         \
91         ldata = (((unsigned long)val) & val_mask) << shift;             \
92         mask = val_mask << shift;                                       \
93         val32 = (val32 & ~mask) | ldata;                                \
94                                                                         \
95         if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
96                 return -1;                                              \
97                                                                         \
98         return 0;                                                       \
99 }
100
101 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
102 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
103 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
104 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
105
106 /*
107  *
108  */
109
110 static struct pci_controller* hose_head;
111
112 struct pci_controller *pci_get_hose_head(void)
113 {
114         if (gd->hose)
115                 return gd->hose;
116
117         return hose_head;
118 }
119
120 void pci_register_hose(struct pci_controller* hose)
121 {
122         struct pci_controller **phose = &hose_head;
123
124         while(*phose)
125                 phose = &(*phose)->next;
126
127         hose->next = NULL;
128
129         *phose = hose;
130 }
131
132 struct pci_controller *pci_bus_to_hose(int bus)
133 {
134         struct pci_controller *hose;
135
136         for (hose = pci_get_hose_head(); hose; hose = hose->next) {
137                 if (bus >= hose->first_busno && bus <= hose->last_busno)
138                         return hose;
139         }
140
141         printf("pci_bus_to_hose() failed\n");
142         return NULL;
143 }
144
145 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
146 {
147         struct pci_controller *hose;
148
149         for (hose = pci_get_hose_head(); hose; hose = hose->next) {
150                 if (hose->cfg_addr == cfg_addr)
151                         return hose;
152         }
153
154         return NULL;
155 }
156
157 int pci_last_busno(void)
158 {
159         struct pci_controller *hose = pci_get_hose_head();
160
161         if (!hose)
162                 return -1;
163
164         while (hose->next)
165                 hose = hose->next;
166
167         return hose->last_busno;
168 }
169
170 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
171 {
172         struct pci_controller * hose;
173         pci_dev_t bdf;
174         int bus;
175
176         for (hose = pci_get_hose_head(); hose; hose = hose->next) {
177                 for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
178                         bdf = pci_hose_find_devices(hose, bus, ids, &index);
179                         if (bdf != -1)
180                                 return bdf;
181                 }
182         }
183
184         return -1;
185 }
186
187 int pci_hose_config_device(struct pci_controller *hose,
188                            pci_dev_t dev,
189                            unsigned long io,
190                            pci_addr_t mem,
191                            unsigned long command)
192 {
193         u32 bar_response;
194         unsigned int old_command;
195         pci_addr_t bar_value;
196         pci_size_t bar_size;
197         unsigned char pin;
198         int bar, found_mem64;
199
200         debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
201                 (u64)mem, command);
202
203         pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
204
205         for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
206                 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
207                 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
208
209                 if (!bar_response)
210                         continue;
211
212                 found_mem64 = 0;
213
214                 /* Check the BAR type and set our address mask */
215                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
216                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
217                         /* round up region base address to a multiple of size */
218                         io = ((io - 1) | (bar_size - 1)) + 1;
219                         bar_value = io;
220                         /* compute new region base address */
221                         io = io + bar_size;
222                 } else {
223                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
224                                 PCI_BASE_ADDRESS_MEM_TYPE_64) {
225                                 u32 bar_response_upper;
226                                 u64 bar64;
227                                 pci_hose_write_config_dword(hose, dev, bar + 4,
228                                         0xffffffff);
229                                 pci_hose_read_config_dword(hose, dev, bar + 4,
230                                         &bar_response_upper);
231
232                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
233
234                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
235                                 found_mem64 = 1;
236                         } else {
237                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
238                         }
239
240                         /* round up region base address to multiple of size */
241                         mem = ((mem - 1) | (bar_size - 1)) + 1;
242                         bar_value = mem;
243                         /* compute new region base address */
244                         mem = mem + bar_size;
245                 }
246
247                 /* Write it out and update our limit */
248                 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
249
250                 if (found_mem64) {
251                         bar += 4;
252 #ifdef CONFIG_SYS_PCI_64BIT
253                         pci_hose_write_config_dword(hose, dev, bar,
254                                 (u32)(bar_value >> 32));
255 #else
256                         pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
257 #endif
258                 }
259         }
260
261         /* Configure Cache Line Size Register */
262         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
263
264         /* Configure Latency Timer */
265         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
266
267         /* Disable interrupt line, if device says it wants to use interrupts */
268         pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
269         if (pin != 0) {
270                 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
271                                            PCI_INTERRUPT_LINE_DISABLE);
272         }
273
274         pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
275         pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
276                                      (old_command & 0xffff0000) | command);
277
278         return 0;
279 }
280
281 /*
282  *
283  */
284
285 struct pci_config_table *pci_find_config(struct pci_controller *hose,
286                                          unsigned short class,
287                                          unsigned int vendor,
288                                          unsigned int device,
289                                          unsigned int bus,
290                                          unsigned int dev,
291                                          unsigned int func)
292 {
293         struct pci_config_table *table;
294
295         for (table = hose->config_table; table && table->vendor; table++) {
296                 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
297                     (table->device == PCI_ANY_ID || table->device == device) &&
298                     (table->class  == PCI_ANY_ID || table->class  == class)  &&
299                     (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
300                     (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
301                     (table->func   == PCI_ANY_ID || table->func   == func)) {
302                         return table;
303                 }
304         }
305
306         return NULL;
307 }
308
309 void pci_cfgfunc_config_device(struct pci_controller *hose,
310                                pci_dev_t dev,
311                                struct pci_config_table *entry)
312 {
313         pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
314                 entry->priv[2]);
315 }
316
317 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
318                             pci_dev_t dev, struct pci_config_table *entry)
319 {
320 }
321
322 /*
323  * HJF: Changed this to return int. I think this is required
324  * to get the correct result when scanning bridges
325  */
326 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
327
328 #ifdef CONFIG_PCI_SCAN_SHOW
329 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
330 {
331         if (dev == PCI_BDF(hose->first_busno, 0, 0))
332                 return 0;
333
334         return 1;
335 }
336 #endif /* CONFIG_PCI_SCAN_SHOW */
337
338 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
339 {
340         unsigned int sub_bus, found_multi = 0;
341         unsigned short vendor, device, class;
342         unsigned char header_type;
343 #ifndef CONFIG_PCI_PNP
344         struct pci_config_table *cfg;
345 #endif
346         pci_dev_t dev;
347 #ifdef CONFIG_PCI_SCAN_SHOW
348         static int indent = 0;
349 #endif
350
351         sub_bus = bus;
352
353         for (dev =  PCI_BDF(bus,0,0);
354              dev <  PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
355                                 PCI_MAX_PCI_FUNCTIONS - 1);
356              dev += PCI_BDF(0, 0, 1)) {
357
358                 if (pci_skip_dev(hose, dev))
359                         continue;
360
361                 if (PCI_FUNC(dev) && !found_multi)
362                         continue;
363
364                 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
365
366                 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
367
368                 if (vendor == 0xffff || vendor == 0x0000)
369                         continue;
370
371                 if (!PCI_FUNC(dev))
372                         found_multi = header_type & 0x80;
373
374                 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
375                         PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
376
377                 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
378                 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
379
380 #ifdef CONFIG_PCI_FIXUP_DEV
381                 board_pci_fixup_dev(hose, dev, vendor, device, class);
382 #endif
383
384 #ifdef CONFIG_PCI_SCAN_SHOW
385                 indent++;
386
387                 /* Print leading space, including bus indentation */
388                 printf("%*c", indent + 1, ' ');
389
390                 if (pci_print_dev(hose, dev)) {
391                         printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
392                                PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
393                                vendor, device, pci_class_str(class >> 8));
394                 }
395 #endif
396
397 #ifdef CONFIG_PCI_PNP
398                 sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
399                               sub_bus);
400 #else
401                 cfg = pci_find_config(hose, class, vendor, device,
402                                       PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
403                 if (cfg) {
404                         cfg->config_device(hose, dev, cfg);
405                         sub_bus = max(sub_bus,
406                                       (unsigned int)hose->current_busno);
407                 }
408 #endif
409
410 #ifdef CONFIG_PCI_SCAN_SHOW
411                 indent--;
412 #endif
413
414                 if (hose->fixup_irq)
415                         hose->fixup_irq(hose, dev);
416         }
417
418         return sub_bus;
419 }
420
421 int pci_hose_scan(struct pci_controller *hose)
422 {
423 #if defined(CONFIG_PCI_BOOTDELAY)
424         char *s;
425         int i;
426
427         if (!gd->pcidelay_done) {
428                 /* wait "pcidelay" ms (if defined)... */
429                 s = env_get("pcidelay");
430                 if (s) {
431                         int val = simple_strtoul(s, NULL, 10);
432                         for (i = 0; i < val; i++)
433                                 udelay(1000);
434                 }
435                 gd->pcidelay_done = 1;
436         }
437 #endif /* CONFIG_PCI_BOOTDELAY */
438
439 #ifdef CONFIG_PCI_SCAN_SHOW
440         puts("PCI:\n");
441 #endif
442
443         /*
444          * Start scan at current_busno.
445          * PCIe will start scan at first_busno+1.
446          */
447         /* For legacy support, ensure current >= first */
448         if (hose->first_busno > hose->current_busno)
449                 hose->current_busno = hose->first_busno;
450 #ifdef CONFIG_PCI_PNP
451         pciauto_config_init(hose);
452 #endif
453         return pci_hose_scan_bus(hose, hose->current_busno);
454 }
455
456 void pci_init(void)
457 {
458         hose_head = NULL;
459
460         /* allow env to disable pci init/enum */
461         if (env_get("pcidisable") != NULL)
462                 return;
463
464         /* now call board specific pci_init()... */
465         pci_init_board();
466 }
467
468 /* Returns the address of the requested capability structure within the
469  * device's PCI configuration space or 0 in case the device does not
470  * support it.
471  * */
472 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
473                              int cap)
474 {
475         int pos;
476         u8 hdr_type;
477
478         pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
479
480         pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
481
482         if (pos)
483                 pos = pci_find_cap(hose, dev, pos, cap);
484
485         return pos;
486 }
487
488 /* Find the header pointer to the Capabilities*/
489 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
490                             u8 hdr_type)
491 {
492         u16 status;
493
494         pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
495
496         if (!(status & PCI_STATUS_CAP_LIST))
497                 return 0;
498
499         switch (hdr_type) {
500         case PCI_HEADER_TYPE_NORMAL:
501         case PCI_HEADER_TYPE_BRIDGE:
502                 return PCI_CAPABILITY_LIST;
503         case PCI_HEADER_TYPE_CARDBUS:
504                 return PCI_CB_CAPABILITY_LIST;
505         default:
506                 return 0;
507         }
508 }
509
510 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
511 {
512         int ttl = PCI_FIND_CAP_TTL;
513         u8 id;
514         u8 next_pos;
515
516         while (ttl--) {
517                 pci_hose_read_config_byte(hose, dev, pos, &next_pos);
518                 if (next_pos < CAP_START_POS)
519                         break;
520                 next_pos &= ~3;
521                 pos = (int) next_pos;
522                 pci_hose_read_config_byte(hose, dev,
523                                           pos + PCI_CAP_LIST_ID, &id);
524                 if (id == 0xff)
525                         break;
526                 if (id == cap)
527                         return pos;
528                 pos += PCI_CAP_LIST_NEXT;
529         }
530         return 0;
531 }
532
533 /**
534  * pci_find_next_ext_capability - Find an extended capability
535  *
536  * Returns the address of the next matching extended capability structure
537  * within the device's PCI configuration space or 0 if the device does
538  * not support it.  Some capabilities can occur several times, e.g., the
539  * vendor-specific capability, and this provides a way to find them all.
540  */
541 int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev,
542                                  int start, int cap)
543 {
544         u32 header;
545         int ttl, pos = PCI_CFG_SPACE_SIZE;
546
547         /* minimum 8 bytes per capability */
548         ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
549
550         if (start)
551                 pos = start;
552
553         pci_hose_read_config_dword(hose, dev, pos, &header);
554         if (header == 0xffffffff || header == 0)
555                 return 0;
556
557         while (ttl-- > 0) {
558                 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
559                         return pos;
560
561                 pos = PCI_EXT_CAP_NEXT(header);
562                 if (pos < PCI_CFG_SPACE_SIZE)
563                         break;
564
565                 pci_hose_read_config_dword(hose, dev, pos, &header);
566                 if (header == 0xffffffff || header == 0)
567                         break;
568         }
569
570         return 0;
571 }
572
573 /**
574  * pci_hose_find_ext_capability - Find an extended capability
575  *
576  * Returns the address of the requested extended capability structure
577  * within the device's PCI configuration space or 0 if the device does
578  * not support it.
579  */
580 int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev,
581                                  int cap)
582 {
583         return pci_find_next_ext_capability(hose, dev, 0, cap);
584 }