2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
5 * (C) Copyright 2002, 2003
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/processor.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 #define PCI_HOSE_OP(rw, size, type) \
25 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
27 int offset, type value) \
29 return hose->rw##_##size(hose, dev, offset, value); \
32 PCI_HOSE_OP(read, byte, u8 *)
33 PCI_HOSE_OP(read, word, u16 *)
34 PCI_HOSE_OP(read, dword, u32 *)
35 PCI_HOSE_OP(write, byte, u8)
36 PCI_HOSE_OP(write, word, u16)
37 PCI_HOSE_OP(write, dword, u32)
39 #define PCI_OP(rw, size, type, error_code) \
40 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
42 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
50 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
53 PCI_OP(read, byte, u8 *, *value = 0xff)
54 PCI_OP(read, word, u16 *, *value = 0xffff)
55 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
56 PCI_OP(write, byte, u8, )
57 PCI_OP(write, word, u16, )
58 PCI_OP(write, dword, u32, )
60 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
61 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
63 int offset, type val) \
67 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
72 *val = (val32 >> ((offset & (int)off_mask) * 8)); \
77 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
78 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
80 int offset, type val) \
82 u32 val32, mask, ldata, shift; \
84 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
87 shift = ((offset & (int)off_mask) * 8); \
88 ldata = (((unsigned long)val) & val_mask) << shift; \
89 mask = val_mask << shift; \
90 val32 = (val32 & ~mask) | ldata; \
92 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
98 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
99 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
100 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
101 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
103 /* Get a virtual address associated with a BAR region */
104 void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
106 pci_addr_t pci_bus_addr;
109 /* read BAR address */
110 pci_read_config_dword(pdev, bar, &bar_response);
111 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
114 * Pass "0" as the length argument to pci_bus_to_virt. The arg
115 * isn't actualy used on any platform because u-boot assumes a static
116 * linear mapping. In the future, this could read the BAR size
117 * and pass that as the size if needed.
119 return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
126 static struct pci_controller* hose_head;
128 struct pci_controller *pci_get_hose_head(void)
136 void pci_register_hose(struct pci_controller* hose)
138 struct pci_controller **phose = &hose_head;
141 phose = &(*phose)->next;
148 struct pci_controller *pci_bus_to_hose(int bus)
150 struct pci_controller *hose;
152 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
153 if (bus >= hose->first_busno && bus <= hose->last_busno)
157 printf("pci_bus_to_hose() failed\n");
161 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
163 struct pci_controller *hose;
165 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
166 if (hose->cfg_addr == cfg_addr)
173 int pci_last_busno(void)
175 struct pci_controller *hose = pci_get_hose_head();
183 return hose->last_busno;
186 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
188 struct pci_controller * hose;
192 int i, bus, found_multi = 0;
194 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
195 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
196 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
198 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
200 for (bdf = PCI_BDF(bus, 0, 0);
201 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
202 bdf < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
203 PCI_MAX_PCI_FUNCTIONS - 1);
205 bdf < PCI_BDF(bus + 1, 0, 0);
207 bdf += PCI_BDF(0, 0, 1)) {
208 if (pci_skip_dev(hose, bdf))
211 if (!PCI_FUNC(bdf)) {
212 pci_read_config_byte(bdf,
216 found_multi = header_type & 0x80;
222 pci_read_config_word(bdf,
225 pci_read_config_word(bdf,
229 for (i = 0; ids[i].vendor != 0; i++) {
230 if (vendor == ids[i].vendor &&
231 device == ids[i].device) {
244 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
246 struct pci_device_id ids[2] = { {}, {0, 0} };
248 ids[0].vendor = vendor;
249 ids[0].device = device;
251 return pci_find_devices(ids, index);
258 int __pci_hose_phys_to_bus(struct pci_controller *hose,
259 phys_addr_t phys_addr,
261 unsigned long skip_mask,
264 struct pci_region *res;
268 for (i = 0; i < hose->region_count; i++) {
269 res = &hose->regions[i];
271 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
274 if (res->flags & skip_mask)
277 bus_addr = phys_addr - res->phys_start + res->bus_start;
279 if (bus_addr >= res->bus_start &&
280 bus_addr < res->bus_start + res->size) {
289 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
290 phys_addr_t phys_addr,
293 pci_addr_t bus_addr = 0;
297 puts("pci_hose_phys_to_bus: invalid hose\n");
302 * if PCI_REGION_MEM is set we do a two pass search with preference
303 * on matches that don't have PCI_REGION_SYS_MEMORY set
305 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
306 ret = __pci_hose_phys_to_bus(hose, phys_addr,
307 flags, PCI_REGION_SYS_MEMORY, &bus_addr);
312 ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
315 puts("pci_hose_phys_to_bus: invalid physical address\n");
320 int __pci_hose_bus_to_phys(struct pci_controller *hose,
323 unsigned long skip_mask,
326 struct pci_region *res;
329 for (i = 0; i < hose->region_count; i++) {
330 res = &hose->regions[i];
332 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
335 if (res->flags & skip_mask)
338 if (bus_addr >= res->bus_start &&
339 (bus_addr - res->bus_start) < res->size) {
340 *pa = (bus_addr - res->bus_start + res->phys_start);
348 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
352 phys_addr_t phys_addr = 0;
356 puts("pci_hose_bus_to_phys: invalid hose\n");
361 * if PCI_REGION_MEM is set we do a two pass search with preference
362 * on matches that don't have PCI_REGION_SYS_MEMORY set
364 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
365 ret = __pci_hose_bus_to_phys(hose, bus_addr,
366 flags, PCI_REGION_SYS_MEMORY, &phys_addr);
371 ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
374 puts("pci_hose_bus_to_phys: invalid physical address\n");
379 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
384 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
385 pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl);
388 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum)
393 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
394 pci_hose_read_config_dword(hose, dev, bar, &addr);
395 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
396 return addr & PCI_BASE_ADDRESS_IO_MASK;
398 return addr & PCI_BASE_ADDRESS_MEM_MASK;
401 int pci_hose_config_device(struct pci_controller *hose,
405 unsigned long command)
408 unsigned int old_command;
409 pci_addr_t bar_value;
412 int bar, found_mem64;
414 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
417 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
419 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
420 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
421 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
428 /* Check the BAR type and set our address mask */
429 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
430 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
431 /* round up region base address to a multiple of size */
432 io = ((io - 1) | (bar_size - 1)) + 1;
434 /* compute new region base address */
437 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
438 PCI_BASE_ADDRESS_MEM_TYPE_64) {
439 u32 bar_response_upper;
441 pci_hose_write_config_dword(hose, dev, bar + 4,
443 pci_hose_read_config_dword(hose, dev, bar + 4,
444 &bar_response_upper);
446 bar64 = ((u64)bar_response_upper << 32) | bar_response;
448 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
451 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
454 /* round up region base address to multiple of size */
455 mem = ((mem - 1) | (bar_size - 1)) + 1;
457 /* compute new region base address */
458 mem = mem + bar_size;
461 /* Write it out and update our limit */
462 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
466 #ifdef CONFIG_SYS_PCI_64BIT
467 pci_hose_write_config_dword(hose, dev, bar,
468 (u32)(bar_value >> 32));
470 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
475 /* Configure Cache Line Size Register */
476 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
478 /* Configure Latency Timer */
479 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
481 /* Disable interrupt line, if device says it wants to use interrupts */
482 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
484 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff);
487 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
488 pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
489 (old_command & 0xffff0000) | command);
498 struct pci_config_table *pci_find_config(struct pci_controller *hose,
499 unsigned short class,
506 struct pci_config_table *table;
508 for (table = hose->config_table; table && table->vendor; table++) {
509 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
510 (table->device == PCI_ANY_ID || table->device == device) &&
511 (table->class == PCI_ANY_ID || table->class == class) &&
512 (table->bus == PCI_ANY_ID || table->bus == bus) &&
513 (table->dev == PCI_ANY_ID || table->dev == dev) &&
514 (table->func == PCI_ANY_ID || table->func == func)) {
522 void pci_cfgfunc_config_device(struct pci_controller *hose,
524 struct pci_config_table *entry)
526 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
530 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
531 pci_dev_t dev, struct pci_config_table *entry)
536 * HJF: Changed this to return int. I think this is required
537 * to get the correct result when scanning bridges
539 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
541 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
542 const char * pci_class_str(u8 class)
545 case PCI_CLASS_NOT_DEFINED:
546 return "Build before PCI Rev2.0";
548 case PCI_BASE_CLASS_STORAGE:
549 return "Mass storage controller";
551 case PCI_BASE_CLASS_NETWORK:
552 return "Network controller";
554 case PCI_BASE_CLASS_DISPLAY:
555 return "Display controller";
557 case PCI_BASE_CLASS_MULTIMEDIA:
558 return "Multimedia device";
560 case PCI_BASE_CLASS_MEMORY:
561 return "Memory controller";
563 case PCI_BASE_CLASS_BRIDGE:
564 return "Bridge device";
566 case PCI_BASE_CLASS_COMMUNICATION:
567 return "Simple comm. controller";
569 case PCI_BASE_CLASS_SYSTEM:
570 return "Base system peripheral";
572 case PCI_BASE_CLASS_INPUT:
573 return "Input device";
575 case PCI_BASE_CLASS_DOCKING:
576 return "Docking station";
578 case PCI_BASE_CLASS_PROCESSOR:
581 case PCI_BASE_CLASS_SERIAL:
582 return "Serial bus controller";
584 case PCI_BASE_CLASS_INTELLIGENT:
585 return "Intelligent controller";
587 case PCI_BASE_CLASS_SATELLITE:
588 return "Satellite controller";
590 case PCI_BASE_CLASS_CRYPT:
591 return "Cryptographic device";
593 case PCI_BASE_CLASS_SIGNAL_PROCESSING:
596 case PCI_CLASS_OTHERS:
597 return "Does not fit any class";
604 #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
606 __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
609 * Check if pci device should be skipped in configuration
611 if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
612 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
614 * Only skip configuration if "pciconfighost" is not set
616 if (getenv("pciconfighost") == NULL)
626 #ifdef CONFIG_PCI_SCAN_SHOW
627 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
629 if (dev == PCI_BDF(hose->first_busno, 0, 0))
634 #endif /* CONFIG_PCI_SCAN_SHOW */
636 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
638 unsigned int sub_bus, found_multi = 0;
639 unsigned short vendor, device, class;
640 unsigned char header_type;
641 #ifndef CONFIG_PCI_PNP
642 struct pci_config_table *cfg;
645 #ifdef CONFIG_PCI_SCAN_SHOW
646 static int indent = 0;
651 for (dev = PCI_BDF(bus,0,0);
652 dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
653 PCI_MAX_PCI_FUNCTIONS - 1);
654 dev += PCI_BDF(0, 0, 1)) {
656 if (pci_skip_dev(hose, dev))
659 if (PCI_FUNC(dev) && !found_multi)
662 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
664 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
666 if (vendor == 0xffff || vendor == 0x0000)
670 found_multi = header_type & 0x80;
672 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
673 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
675 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
676 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
678 #ifdef CONFIG_PCI_FIXUP_DEV
679 board_pci_fixup_dev(hose, dev, vendor, device, class);
682 #ifdef CONFIG_PCI_SCAN_SHOW
685 /* Print leading space, including bus indentation */
686 printf("%*c", indent + 1, ' ');
688 if (pci_print_dev(hose, dev)) {
689 printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
690 PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
691 vendor, device, pci_class_str(class >> 8));
695 #ifdef CONFIG_PCI_PNP
696 sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
699 cfg = pci_find_config(hose, class, vendor, device,
700 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
702 cfg->config_device(hose, dev, cfg);
703 sub_bus = max(sub_bus,
704 (unsigned int)hose->current_busno);
708 #ifdef CONFIG_PCI_SCAN_SHOW
713 hose->fixup_irq(hose, dev);
719 int pci_hose_scan(struct pci_controller *hose)
721 #if defined(CONFIG_PCI_BOOTDELAY)
725 if (!gd->pcidelay_done) {
726 /* wait "pcidelay" ms (if defined)... */
727 s = getenv("pcidelay");
729 int val = simple_strtoul(s, NULL, 10);
730 for (i = 0; i < val; i++)
733 gd->pcidelay_done = 1;
735 #endif /* CONFIG_PCI_BOOTDELAY */
738 * Start scan at current_busno.
739 * PCIe will start scan at first_busno+1.
741 /* For legacy support, ensure current >= first */
742 if (hose->first_busno > hose->current_busno)
743 hose->current_busno = hose->first_busno;
744 #ifdef CONFIG_PCI_PNP
745 pciauto_config_init(hose);
747 return pci_hose_scan_bus(hose, hose->current_busno);
754 /* now call board specific pci_init()... */
758 /* Returns the address of the requested capability structure within the
759 * device's PCI configuration space or 0 in case the device does not
762 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
768 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
770 pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
773 pos = pci_find_cap(hose, dev, pos, cap);
778 /* Find the header pointer to the Capabilities*/
779 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
784 pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
786 if (!(status & PCI_STATUS_CAP_LIST))
790 case PCI_HEADER_TYPE_NORMAL:
791 case PCI_HEADER_TYPE_BRIDGE:
792 return PCI_CAPABILITY_LIST;
793 case PCI_HEADER_TYPE_CARDBUS:
794 return PCI_CB_CAPABILITY_LIST;
800 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
802 int ttl = PCI_FIND_CAP_TTL;
807 pci_hose_read_config_byte(hose, dev, pos, &next_pos);
808 if (next_pos < CAP_START_POS)
811 pos = (int) next_pos;
812 pci_hose_read_config_byte(hose, dev,
813 pos + PCI_CAP_LIST_ID, &id);
818 pos += PCI_CAP_LIST_NEXT;