git.sur5r.net Git - u-boot/blob - drivers/pci/pci.c

   1 /*
   2  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   3  * Andreas Heppel <aheppel@sysgo.de>
   4  *
   5  * (C) Copyright 2002, 2003
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * PCI routines
  29  */
  30
  31 #include <common.h>
  32
  33 #include <command.h>
  34 #include <asm/processor.h>
  35 #include <asm/io.h>
  36 #include <pci.h>
  37
  38 #define PCI_HOSE_OP(rw, size, type)                                     \
  39 int pci_hose_##rw##_config_##size(struct pci_controller *hose,          \
  40                                   pci_dev_t dev,                        \
  41                                   int offset, type value)               \
  42 {                                                                       \
  43         return hose->rw##_##size(hose, dev, offset, value);             \
  44 }
  45
  46 PCI_HOSE_OP(read, byte, u8 *)
  47 PCI_HOSE_OP(read, word, u16 *)
  48 PCI_HOSE_OP(read, dword, u32 *)
  49 PCI_HOSE_OP(write, byte, u8)
  50 PCI_HOSE_OP(write, word, u16)
  51 PCI_HOSE_OP(write, dword, u32)
  52
  53 #ifndef CONFIG_IXP425
  54 #define PCI_OP(rw, size, type, error_code)                              \
  55 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)     \
  56 {                                                                       \
  57         struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));    \
  58                                                                         \
  59         if (!hose)                                                      \
  60         {                                                               \
  61                 error_code;                                             \
  62                 return -1;                                              \
  63         }                                                               \
  64                                                                         \
  65         return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
  66 }
  67
  68 PCI_OP(read, byte, u8 *, *value = 0xff)
  69 PCI_OP(read, word, u16 *, *value = 0xffff)
  70 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
  71 PCI_OP(write, byte, u8, )
  72 PCI_OP(write, word, u16, )
  73 PCI_OP(write, dword, u32, )
  74 #endif  /* CONFIG_IXP425 */
  75
  76 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)                     \
  77 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
  78                                         pci_dev_t dev,                  \
  79                                         int offset, type val)           \
  80 {                                                                       \
  81         u32 val32;                                                      \
  82                                                                         \
  83         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
  84                 *val = -1;                                              \
  85                 return -1;                                              \
  86         }                                                               \
  87                                                                         \
  88         *val = (val32 >> ((offset & (int)off_mask) * 8));               \
  89                                                                         \
  90         return 0;                                                       \
  91 }
  92
  93 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)          \
  94 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
  95                                              pci_dev_t dev,             \
  96                                              int offset, type val)      \
  97 {                                                                       \
  98         u32 val32, mask, ldata, shift;                                  \
  99                                                                         \
 100         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
 101                 return -1;                                              \
 102                                                                         \
 103         shift = ((offset & (int)off_mask) * 8);                         \
 104         ldata = (((unsigned long)val) & val_mask) << shift;             \
 105         mask = val_mask << shift;                                       \
 106         val32 = (val32 & ~mask) | ldata;                                \
 107                                                                         \
 108         if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
 109                 return -1;                                              \
 110                                                                         \
 111         return 0;                                                       \
 112 }
 113
 114 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
 115 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
 116 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
 117 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
 118
 119 /* Get a virtual address associated with a BAR region */
 120 void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
 121 {
 122         pci_addr_t pci_bus_addr;
 123         u32 bar_response;
 124
 125         /* read BAR address */
 126         pci_read_config_dword(pdev, bar, &bar_response);
 127         pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
 128
 129         /*
 130          * Pass "0" as the length argument to pci_bus_to_virt.  The arg
 131          * isn't actualy used on any platform because u-boot assumes a static
 132          * linear mapping.  In the future, this could read the BAR size
 133          * and pass that as the size if needed.
 134          */
 135         return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
 136 }
 137
 138 /*
 139  *
 140  */
 141
 142 static struct pci_controller* hose_head;
 143
 144 void pci_register_hose(struct pci_controller* hose)
 145 {
 146         struct pci_controller **phose = &hose_head;
 147
 148         while(*phose)
 149                 phose = &(*phose)->next;
 150
 151         hose->next = NULL;
 152
 153         *phose = hose;
 154 }
 155
 156 struct pci_controller *pci_bus_to_hose (int bus)
 157 {
 158         struct pci_controller *hose;
 159
 160         for (hose = hose_head; hose; hose = hose->next)
 161                 if (bus >= hose->first_busno && bus <= hose->last_busno)
 162                         return hose;
 163
 164         printf("pci_bus_to_hose() failed\n");
 165         return NULL;
 166 }
 167
 168 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
 169 {
 170         struct pci_controller *hose;
 171
 172         for (hose = hose_head; hose; hose = hose->next) {
 173                 if (hose->cfg_addr == cfg_addr)
 174                         return hose;
 175         }
 176
 177         return NULL;
 178 }
 179
 180 int pci_last_busno(void)
 181 {
 182         struct pci_controller *hose = hose_head;
 183
 184         if (!hose)
 185                 return -1;
 186
 187         while (hose->next)
 188                 hose = hose->next;
 189
 190         return hose->last_busno;
 191 }
 192
 193 #ifndef CONFIG_IXP425
 194 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 195 {
 196         struct pci_controller * hose;
 197         u16 vendor, device;
 198         u8 header_type;
 199         pci_dev_t bdf;
 200         int i, bus, found_multi = 0;
 201
 202         for (hose = hose_head; hose; hose = hose->next)
 203         {
 204 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
 205                 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
 206 #else
 207                 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
 208 #endif
 209                         for (bdf = PCI_BDF(bus,0,0);
 210 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
 211                              bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
 212 #else
 213                              bdf < PCI_BDF(bus+1,0,0);
 214 #endif
 215                              bdf += PCI_BDF(0,0,1))
 216                         {
 217                                 if (!PCI_FUNC(bdf)) {
 218                                         pci_read_config_byte(bdf,
 219                                                              PCI_HEADER_TYPE,
 220                                                              &header_type);
 221
 222                                         found_multi = header_type & 0x80;
 223                                 } else {
 224                                         if (!found_multi)
 225                                                 continue;
 226                                 }
 227
 228                                 pci_read_config_word(bdf,
 229                                                      PCI_VENDOR_ID,
 230                                                      &vendor);
 231                                 pci_read_config_word(bdf,
 232                                                      PCI_DEVICE_ID,
 233                                                      &device);
 234
 235                                 for (i=0; ids[i].vendor != 0; i++)
 236                                         if (vendor == ids[i].vendor &&
 237                                             device == ids[i].device)
 238                                         {
 239                                                 if (index <= 0)
 240                                                         return bdf;
 241
 242                                                 index--;
 243                                         }
 244                         }
 245         }
 246
 247         return (-1);
 248 }
 249 #endif  /* CONFIG_IXP425 */
 250
 251 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
 252 {
 253         static struct pci_device_id ids[2] = {{}, {0, 0}};
 254
 255         ids[0].vendor = vendor;
 256         ids[0].device = device;
 257
 258         return pci_find_devices(ids, index);
 259 }
 260
 261 /*
 262  *
 263  */
 264
 265 int __pci_hose_phys_to_bus (struct pci_controller *hose,
 266                                 phys_addr_t phys_addr,
 267                                 unsigned long flags,
 268                                 unsigned long skip_mask,
 269                                 pci_addr_t *ba)
 270 {
 271         struct pci_region *res;
 272         pci_addr_t bus_addr;
 273         int i;
 274
 275         for (i = 0; i < hose->region_count; i++) {
 276                 res = &hose->regions[i];
 277
 278                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 279                         continue;
 280
 281                 if (res->flags & skip_mask)
 282                         continue;
 283
 284                 bus_addr = phys_addr - res->phys_start + res->bus_start;
 285
 286                 if (bus_addr >= res->bus_start &&
 287                         bus_addr < res->bus_start + res->size) {
 288                         *ba = bus_addr;
 289                         return 0;
 290                 }
 291         }
 292
 293         return 1;
 294 }
 295
 296 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
 297                                     phys_addr_t phys_addr,
 298                                     unsigned long flags)
 299 {
 300         pci_addr_t bus_addr = 0;
 301         int ret;
 302
 303         if (!hose) {
 304                 puts ("pci_hose_phys_to_bus: invalid hose\n");
 305                 return bus_addr;
 306         }
 307
 308         /* if PCI_REGION_MEM is set we do a two pass search with preference
 309          * on matches that don't have PCI_REGION_SYS_MEMORY set */
 310         if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
 311                 ret = __pci_hose_phys_to_bus(hose, phys_addr,
 312                                 flags, PCI_REGION_SYS_MEMORY, &bus_addr);
 313                 if (!ret)
 314                         return bus_addr;
 315         }
 316
 317         ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
 318
 319         if (ret)
 320                 puts ("pci_hose_phys_to_bus: invalid physical address\n");
 321
 322         return bus_addr;
 323 }
 324
 325 int __pci_hose_bus_to_phys (struct pci_controller *hose,
 326                                 pci_addr_t bus_addr,
 327                                 unsigned long flags,
 328                                 unsigned long skip_mask,
 329                                 phys_addr_t *pa)
 330 {
 331         struct pci_region *res;
 332         int i;
 333
 334         for (i = 0; i < hose->region_count; i++) {
 335                 res = &hose->regions[i];
 336
 337                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 338                         continue;
 339
 340                 if (res->flags & skip_mask)
 341                         continue;
 342
 343                 if (bus_addr >= res->bus_start &&
 344                         bus_addr < res->bus_start + res->size) {
 345                         *pa = (bus_addr - res->bus_start + res->phys_start);
 346                         return 0;
 347                 }
 348         }
 349
 350         return 1;
 351 }
 352
 353 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
 354                                  pci_addr_t bus_addr,
 355                                  unsigned long flags)
 356 {
 357         phys_addr_t phys_addr = 0;
 358         int ret;
 359
 360         if (!hose) {
 361                 puts ("pci_hose_bus_to_phys: invalid hose\n");
 362                 return phys_addr;
 363         }
 364
 365         /* if PCI_REGION_MEM is set we do a two pass search with preference
 366          * on matches that don't have PCI_REGION_SYS_MEMORY set */
 367         if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
 368                 ret = __pci_hose_bus_to_phys(hose, bus_addr,
 369                                 flags, PCI_REGION_SYS_MEMORY, &phys_addr);
 370                 if (!ret)
 371                         return phys_addr;
 372         }
 373
 374         ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
 375
 376         if (ret)
 377                 puts ("pci_hose_bus_to_phys: invalid physical address\n");
 378
 379         return phys_addr;
 380 }
 381
 382 /*
 383  *
 384  */
 385
 386 int pci_hose_config_device(struct pci_controller *hose,
 387                            pci_dev_t dev,
 388                            unsigned long io,
 389                            pci_addr_t mem,
 390                            unsigned long command)
 391 {
 392         unsigned int bar_response, old_command;
 393         pci_addr_t bar_value;
 394         pci_size_t bar_size;
 395         unsigned char pin;
 396         int bar, found_mem64;
 397
 398         debug ("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n",
 399                 io, (u64)mem, command);
 400
 401         pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
 402
 403         for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
 404                 pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
 405                 pci_hose_read_config_dword (hose, dev, bar, &bar_response);
 406
 407                 if (!bar_response)
 408                         continue;
 409
 410                 found_mem64 = 0;
 411
 412                 /* Check the BAR type and set our address mask */
 413                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 414                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
 415                         /* round up region base address to a multiple of size */
 416                         io = ((io - 1) | (bar_size - 1)) + 1;
 417                         bar_value = io;
 418                         /* compute new region base address */
 419                         io = io + bar_size;
 420                 } else {
 421                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 422                                 PCI_BASE_ADDRESS_MEM_TYPE_64) {
 423                                 u32 bar_response_upper;
 424                                 u64 bar64;
 425                                 pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
 426                                 pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
 427
 428                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
 429
 430                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 431                                 found_mem64 = 1;
 432                         } else {
 433                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
 434                         }
 435
 436                         /* round up region base address to multiple of size */
 437                         mem = ((mem - 1) | (bar_size - 1)) + 1;
 438                         bar_value = mem;
 439                         /* compute new region base address */
 440                         mem = mem + bar_size;
 441                 }
 442
 443                 /* Write it out and update our limit */
 444                 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
 445
 446                 if (found_mem64) {
 447                         bar += 4;
 448 #ifdef CONFIG_SYS_PCI_64BIT
 449                         pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
 450 #else
 451                         pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
 452 #endif
 453                 }
 454         }
 455
 456         /* Configure Cache Line Size Register */
 457         pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 458
 459         /* Configure Latency Timer */
 460         pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);
 461
 462         /* Disable interrupt line, if device says it wants to use interrupts */
 463         pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
 464         if (pin != 0) {
 465                 pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
 466         }
 467
 468         pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
 469         pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
 470                                      (old_command & 0xffff0000) | command);
 471
 472         return 0;
 473 }
 474
 475 /*
 476  *
 477  */
 478
 479 struct pci_config_table *pci_find_config(struct pci_controller *hose,
 480                                          unsigned short class,
 481                                          unsigned int vendor,
 482                                          unsigned int device,
 483                                          unsigned int bus,
 484                                          unsigned int dev,
 485                                          unsigned int func)
 486 {
 487         struct pci_config_table *table;
 488
 489         for (table = hose->config_table; table && table->vendor; table++) {
 490                 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
 491                     (table->device == PCI_ANY_ID || table->device == device) &&
 492                     (table->class  == PCI_ANY_ID || table->class  == class)  &&
 493                     (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
 494                     (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
 495                     (table->func   == PCI_ANY_ID || table->func   == func)) {
 496                         return table;
 497                 }
 498         }
 499
 500         return NULL;
 501 }
 502
 503 void pci_cfgfunc_config_device(struct pci_controller *hose,
 504                                pci_dev_t dev,
 505                                struct pci_config_table *entry)
 506 {
 507         pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
 508 }
 509
 510 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
 511                             pci_dev_t dev, struct pci_config_table *entry)
 512 {
 513 }
 514
 515 /*
 516  *
 517  */
 518
 519 /* HJF: Changed this to return int. I think this is required
 520  * to get the correct result when scanning bridges
 521  */
 522 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
 523 extern void pciauto_config_init(struct pci_controller *hose);
 524
 525 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
 526 const char * pci_class_str(u8 class)
 527 {
 528         switch (class) {
 529         case PCI_CLASS_NOT_DEFINED:
 530                 return "Build before PCI Rev2.0";
 531                 break;
 532         case PCI_BASE_CLASS_STORAGE:
 533                 return "Mass storage controller";
 534                 break;
 535         case PCI_BASE_CLASS_NETWORK:
 536                 return "Network controller";
 537                 break;
 538         case PCI_BASE_CLASS_DISPLAY:
 539                 return "Display controller";
 540                 break;
 541         case PCI_BASE_CLASS_MULTIMEDIA:
 542                 return "Multimedia device";
 543                 break;
 544         case PCI_BASE_CLASS_MEMORY:
 545                 return "Memory controller";
 546                 break;
 547         case PCI_BASE_CLASS_BRIDGE:
 548                 return "Bridge device";
 549                 break;
 550         case PCI_BASE_CLASS_COMMUNICATION:
 551                 return "Simple comm. controller";
 552                 break;
 553         case PCI_BASE_CLASS_SYSTEM:
 554                 return "Base system peripheral";
 555                 break;
 556         case PCI_BASE_CLASS_INPUT:
 557                 return "Input device";
 558                 break;
 559         case PCI_BASE_CLASS_DOCKING:
 560                 return "Docking station";
 561                 break;
 562         case PCI_BASE_CLASS_PROCESSOR:
 563                 return "Processor";
 564                 break;
 565         case PCI_BASE_CLASS_SERIAL:
 566                 return "Serial bus controller";
 567                 break;
 568         case PCI_BASE_CLASS_INTELLIGENT:
 569                 return "Intelligent controller";
 570                 break;
 571         case PCI_BASE_CLASS_SATELLITE:
 572                 return "Satellite controller";
 573                 break;
 574         case PCI_BASE_CLASS_CRYPT:
 575                 return "Cryptographic device";
 576                 break;
 577         case PCI_BASE_CLASS_SIGNAL_PROCESSING:
 578                 return "DSP";
 579                 break;
 580         case PCI_CLASS_OTHERS:
 581                 return "Does not fit any class";
 582                 break;
 583         default:
 584         return  "???";
 585                 break;
 586         };
 587 }
 588 #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
 589
 590 int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 591 {
 592         /*
 593          * Check if pci device should be skipped in configuration
 594          */
 595         if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
 596 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
 597                 /*
 598                  * Only skip configuration if "pciconfighost" is not set
 599                  */
 600                 if (getenv("pciconfighost") == NULL)
 601                         return 1;
 602 #else
 603                 return 1;
 604 #endif
 605         }
 606
 607         return 0;
 608 }
 609 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 610         __attribute__((weak, alias("__pci_skip_dev")));
 611
 612 #ifdef CONFIG_PCI_SCAN_SHOW
 613 int __pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
 614 {
 615         if (dev == PCI_BDF(hose->first_busno, 0, 0))
 616                 return 0;
 617
 618         return 1;
 619 }
 620 int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
 621         __attribute__((weak, alias("__pci_print_dev")));
 622 #endif /* CONFIG_PCI_SCAN_SHOW */
 623
 624 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
 625 {
 626         unsigned int sub_bus, found_multi=0;
 627         unsigned short vendor, device, class;
 628         unsigned char header_type;
 629         struct pci_config_table *cfg;
 630         pci_dev_t dev;
 631 #ifdef CONFIG_PCI_SCAN_SHOW
 632         static int indent = 0;
 633 #endif
 634
 635         sub_bus = bus;
 636
 637         for (dev =  PCI_BDF(bus,0,0);
 638              dev <  PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
 639              dev += PCI_BDF(0,0,1)) {
 640
 641                 if (pci_skip_dev(hose, dev))
 642                         continue;
 643
 644                 if (PCI_FUNC(dev) && !found_multi)
 645                         continue;
 646
 647                 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 648
 649                 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
 650
 651                 if (vendor == 0xffff || vendor == 0x0000)
 652                         continue;
 653
 654                 if (!PCI_FUNC(dev))
 655                         found_multi = header_type & 0x80;
 656
 657                 debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
 658                         PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
 659
 660                 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
 661                 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 662
 663 #ifdef CONFIG_PCI_SCAN_SHOW
 664                 indent++;
 665
 666                 /* Print leading space, including bus indentation */
 667                 printf("%*c", indent + 1, ' ');
 668
 669                 if (pci_print_dev(hose, dev)) {
 670                         printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
 671                                PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
 672                                vendor, device, pci_class_str(class >> 8));
 673                 }
 674 #endif
 675
 676                 cfg = pci_find_config(hose, class, vendor, device,
 677                                       PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
 678                 if (cfg) {
 679                         cfg->config_device(hose, dev, cfg);
 680                         sub_bus = max(sub_bus, hose->current_busno);
 681 #ifdef CONFIG_PCI_PNP
 682                 } else {
 683                         int n = pciauto_config_device(hose, dev);
 684
 685                         sub_bus = max(sub_bus, n);
 686 #endif
 687                 }
 688
 689 #ifdef CONFIG_PCI_SCAN_SHOW
 690                 indent--;
 691 #endif
 692
 693                 if (hose->fixup_irq)
 694                         hose->fixup_irq(hose, dev);
 695         }
 696
 697         return sub_bus;
 698 }
 699
 700 int pci_hose_scan(struct pci_controller *hose)
 701 {
 702         /* Start scan at current_busno.
 703          * PCIe will start scan at first_busno+1.
 704          */
 705         /* For legacy support, ensure current>=first */
 706         if (hose->first_busno > hose->current_busno)
 707                 hose->current_busno = hose->first_busno;
 708 #ifdef CONFIG_PCI_PNP
 709         pciauto_config_init(hose);
 710 #endif
 711         return pci_hose_scan_bus(hose, hose->current_busno);
 712 }
 713
 714 void pci_init(void)
 715 {
 716 #if defined(CONFIG_PCI_BOOTDELAY)
 717         char *s;
 718         int i;
 719
 720         /* wait "pcidelay" ms (if defined)... */
 721         s = getenv ("pcidelay");
 722         if (s) {
 723                 int val = simple_strtoul (s, NULL, 10);
 724                 for (i=0; i<val; i++)
 725                         udelay (1000);
 726         }
 727 #endif /* CONFIG_PCI_BOOTDELAY */
 728
 729         hose_head = NULL;
 730
 731         /* now call board specific pci_init()... */
 732         pci_init_board();
 733 }